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EL1508

®

Data Sheet

March 26, 2007

FN7014.5

Differential DSL Line Driver

Features

The EL1508 is designed for driving full rate ADSL signals in

both CO and CPE applications at very low power dissipation.

The high drive capability of 450mA makes this driver ideal

for both CAP and DMT designs. It contains two wideband,

high-voltage, current mode feedback amplifiers with a

number of power dissipation reduction features.

• 450mA output drive capability

• 43.6V differential output drive into 100Ω

P-P

nd rd

• 2 /3 harmonics of -85dBc/-75dBc

• MTPR of -70dB

• Operates down to 3mA per amplifier supply current

• Power control features

These drivers achieve an MTPR distortion measurement of

better than 70dB, while consuming typically 6mA of total

supply current. This supply current can be set using a

• Pin-compatible with EL1503

resistor on the I

pin. Two other pins (C and C ) can

ADJ

0 1

• Pb-free plus anneal available (RoHS compliant)

also be used to adjust supply current to one of four pre-set

modes (full-I , 2/3-I , 1/3-I , and full power-down). The

S

Applications

EL1508 operates on ±5V to ±12V supplies and retains its

bandwidth and linearity over the complete supply range.

• ADSL line driver

• HDSL line driver

The device is supplied in a thermally-enhanced 20 Ld SOIC

(0.300”), a thermally-enhanced 16 Ld SOIC (0.150”), and the

small footprint (4x5mm) 24 Ld QFN packages. The EL1508

is specified for operation over the full -40°C to +85°C

temperature range.

• Video distribution amplifier

• Video twisted-pair line driver

Pinouts

EL1508

[20 LD SOIC (0.300”)]

[16 LD SOIC (0.150”)]

(24 LD QFN)

TOP VIEW

VIN-A

VOUTA

VS-

1

2

3

4

5

6

7

8

9

20 VIN-B

VIN-A

VOUTA

VS-

1

2

3

4

5

6

7

8

16 VIN-B

19 VOUTB

18 VS+

15 VOUTB

14 VS+

NC 1

NC 2

VS- 3

NC 4

NC 5

NC 6

GND 7

19 NC

18 NC

17 VS+

16 NC

15 NC

14 NC

13 GND

A

B

+

-

+

-

+

-

+

GND*

VIN+A

C1

17 GND*

16 GND*

15 GND*

14 GND*

13 VIN+B

12 IADJ

11 NC

GND*

VIN+A

C1

13 GND*

12 GND*

11 VIN+B

10 IADJ

THERMAL

PAD

POWER

CONTROL

LOGIC

C0

9 NC

POWER

CONTROL

LOGIC

C0 10

*GND PINS ARE HEAT SPREADERS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

EL1508

Ordering Information

PART NUMBER

PART MARKING

EL1508CS

EL1508CSZ

EL1508CM

EL1508CMZ

1508CL

TAPE & REEL

PACKAGE

16 Ld SOIC (0.150”)

PKG. DWG. #

MDP0027

EL1508CS

-

7”

13”

-

EL1508CS-T7

16 Ld SOIC (0.150”)

16 Ld SOIC (0.150”) (Pb-Free)

20 Ld SOIC (0.300”)

20 Ld SOIC (0.300”) (Pb-Free)

24 Ld QFN

MDP0027

MDP0046

EL1508CS-T13

EL1508CSZ (See Note)

EL1508CSZ-T7 (See Note)

EL1508CSZ-T13 (See Note)

EL1508CM

7”

13”

-

EL1508CM-T13

13”

-

EL1508CMZ (See Note)

EL1508CMZ-T13 (See Note)

EL1508CL

13”

-

EL1508CL-T7

1508CL

7”

13”

-

24 Ld QFN

EL1508CL-T13

1508CL

24 Ld QFN

EL1508CLZ (See Note)

EL1508CLZ-T7 (See Note)

EL1508CLZ-T13 (See Note)

1508CLZ

24 Ld QFN (Pb-Free)

1508CLZ

7”

13”

1508CLZ

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN7014.5

March 26, 2007

2

EL1508

Absolute Maximum Ratings (T = 25°C)

A

V + to V - Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V

Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA

Output Current from Driver (Static) . . . . . . . . . . . . . . . . . . . . 100mA

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

S

V + Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V

S

V - Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -28V to 0.3V

S

Driver V + Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - to V +

IN

S

C , C Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

0

1

I

Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V

ADJ

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at

the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

Electrical Specifications

PARAMETER

V

= ±12V, R = 2.2kΩ, R = 65Ω, I = C = C = 0V, T = 25°C. Amplifiers tested separately.

ADJL 0 1 A

S

F

L

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CHARACTERISTICS

I + (Full I )

Positive Supply Current per Amplifier

Negative Supply Current per Amplifier

Positive Supply Current per Amplifier

Negative Supply Current per Amplifier

Positive Supply Current per Amplifier

Negative Supply Current per Amplifier

Positive Supply Current per Amplifier

All outputs at 0V, C = C = 0V

10

-9.5

7

14.5

-13.5

10

18

-17.5

12.5

-12

7

mA

S

0

1

I - (Full I )

All outputs at 0V, C = C = 0V

0 1

S

I + (2/3 I )

All outputs at 0V, C = 5V, C = 0V

0 1

S

I - (2/3 I )

All outputs at 0V, C = 5V, C = 0V

-6

-9

S

0

1

I + (1/3 I )

All outputs at 0V, C = 0V, C = 5V

3.75

-2.75

3

5.25

-4.25

3.75

S

0

1

I - (1/3 I )

All outputs at 0V, C = 0V, C = 5V

-6

S

0

1

I + (6.8k)

All outputs at 0V, C = C = 0V,

4.5

S

0

1

R

= 6.8k

ADJ

I - (6.8k)

Negative Supply Current per Amplifier

All outputs at 0V, C = C = 0V,

-3.75

-2.9

-2.25

mA

S

0

1

R

= 6.8k

ADJ

I + (Power-down) Positive Supply Current per Amplifier

All outputs at 0V, C = C = 5V

0.75

0

1.2

-0.25

1

2

mA

S

0

1

I - (Power-down)

Negative Supply Current per Amplifier

GND Supply Current per Amplifier

All outputs at 0V, C = C = 5V

-2

S

0

1

I

All outputs at 0V

GND

INPUT CHARACTERISTICS

Input Offset Voltage

Mismatch

V

-10

-5

1

0

10

5

mV

µA

OS

ΔV

V

OS

I +

OS

Non-Inverting Input Bias Current

Inverting Input Bias Current

-15

-50

-25

1.1

15

50

25

5

B

I -

µA

B

ΔI -

I - Mismatch

B

0

µA

B

R

e

Transimpedance

2.9

3.5

13

MΩ

OL

Input Noise Voltage

-Input Noise Current

Input High Voltage

Input Low Voltage

nV/ Hz

√

N

i

pA/ Hz

√

N

V

C

and C inputs

2.25

V

IH

IL

0

1

0

1

and C inputs

1

0.8

6

V

I

Input High Current for C

= 5V

1

2

1

µA

IH1

IH0

IL

1

0

0.5

-1

3

Input Low Current for C or C

0

= 0V, C = 0V

1

FN7014.5

March 26, 2007

3

EL1508

Electrical Specifications

PARAMETER

V

= ±12V, R = 2.2kΩ, R = 65Ω, I

ADJL

= C = C = 0V, T = 25°C. Amplifiers tested separately. (Continued)

S

F

L

0

1

A

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT CHARACTERISTICS

V

Loaded Output Swing

R

= 100Ω

±10.6

±9.8

±10.8

±10.2

450

±11.5

±10.6

V

OUT

L

= 25Ω

= 5, R = 10Ω, f = 100kHz,

L

I

Linear Output Current

Output Current

A

mA

OL

V

L

THD = -60dBc

V

= 1V, R = 1Ω

1

A

OUT

L

DYNAMIC PERFORMANCE

BW

-3 dB Bandwidth

A

= +5

80

MHz

dBc

V

HD2

2nd Harmonic Distortion

f

= 1MHz, R = 100Ω, V

= 2V

-90

-80

-90

-75

-70

C

L

OUT

P-P

= 1MHz, R = 25Ω, V

= 2V

C

L

OUT

P-P

HD3

3rd Harmonic Distortion

= 1MHz, R = 100Ω, V

= 2V

L

= 1MHz, R = 25Ω, V

L

OUT

= 100Ω,

P-P

MTPR

SR

Multi-Tone Power Ratio

Slewrate

26kHz to 1.1MHz, R

LINE

P

= 20.4dBM

LINE

V

from -8V to +8V measured at ±4V

450

600

800

V/µs

OUT

FN7014.5

March 26, 2007

4

EL1508

Pin Descriptions

16 Ld SOIC 20 Ld SOIC

(0.150")

(0.300")

24 Ld QFN

PIN NAME

FUNCTION

CIRCUIT

1

23

VIN-A

Channel A Inverting Input

CIRCUIT 1

2

3

2

24

3

VOUTA

VS-

Channel A Output

(Reference Circuit 1)

3

4, 5, 6, 7

8

Negative Supply

4, 5

6

7

GND

Ground Connection

Channel A Non-inverting Input

8

VIN+A

V +

S

V -

S

CIRCUIT 2

7

9

C1

Current Control Bit 1

V +

S

6.7V

CIRCUIT 3

(Reference Circuit 3)

8

9

10

11

10

C0

Current Control Bit 2

Not Connected

1, 2, 4, 5, 6, 14,

NC

15, 16, 18, 19, 22

10

12

11

IADJ

Supply Current Control Pin

V +

S

I

ADJ

GND

CIRCUIT 4

11

12, 13

14

13

12

13

17

20

21

VIN+B

GND

Channel B Non-inverting Input

Ground Connection

(Reference Circuit 2)

14, 15, 16, 17

18

19

20

VS+

Positive Supply

15

VOUTB

VIN-B

Channel B Output

(Reference Circuit 1)

16

Channel B Inverting Input

FN7014.5

March 26, 2007

5

EL1508

Typical Performance Curves

24

18

A =10

A =5

V

S

L

V

R =2kΩ

R =1.5kΩ

F

R =3kΩ

F

R =2kΩ

V =±12V

F

S

R =100Ω

22

20

18

16

16 R =100Ω

L

ADJ

R =2.5kΩ

R

=0Ω

F

R =2.5kΩ

F

14

12

10

R =4kΩ

F

R =3kΩ

F

R =3.5kΩ

F

14

100K

8

1M

10M

FREQUENCY (Hz)

100M

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs R

(1/3 POWER MODE)

FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE

(1/3 POWER MODE)

F

24

18

A =10

V

A =5

V

V =±12V

S

R =100Ω

22

20

18

16

14

L

ADJ

16

14

12

10

8

L

R

=0Ω

R =2kΩ

R =1.5kΩ

R =4kΩ

F

R =2kΩ

F

R =3.5kΩ

F

R =2.5kΩ

F

R =3kΩ

F

R =3kΩ

F

R =2.5kΩ

F

100K

1M

10M

100M

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs R

(2/3 POWER MODE)

FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE

(2/3 POWER MODE)

24

18

A =5

V

A =10

V

V =±12V

S

R =100Ω

22

20

18

16

14

16

14

12

10

8

L

ADJ

R

=0Ω

R =1.5kΩ

F

R =4kΩ

F

R =2kΩ

F

R =2kΩ

R =3kΩ

F

R =2.5kΩ

F

R =2.5kΩ

F

R =3.5kΩ

F

R =3kΩ

F

100K

1M

10M

100M

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs R

(FULL POWER MODE)

FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE

(FULL POWER MODE)

FN7014.5

March 26, 2007

6

EL1508

Typical Performance Curves (Continued)

26

22

18

14

10

6

V =±12V

S

V =±12V

S

R

=3kΩ

R

A =5

R =83Ω

R

=3kΩ

FB

V

L

100pF

68pF

A =5

V

22

18

14

10

6

R =83Ω

150pF

100pF

62pF

L

SET

R

=0Ω

SET

50pF

22pF

0pF

39pF

22pF

0pF

10K

100K

1M

FREQUENCY (Hz)

10M

100M

10K

100K

1M

FREQUENCY (Hz)

10M

100M

FIGURE 7. EL1508CM SINGLE-ENDED CONFIGURATION

FIGURE 8. EL1508CM SINGLE-ENDED CONFIGURATION

FREQUENCY RESPONSE vs C

(1/3 POWER MODE)

FREQUENCY RESPONSE vs C

(1/3 POWER MODE)

L

26

22

18

14

10

6

5

4

3

2

1

0

V =±12V

S

R

=3kΩ

R

=3kΩ

FB

V

L

FB

A =10

R =100Ω

A =5

V

150pF

100pF

62pF

R =83Ω

L

SET

R

=0Ω

39pF

22pF

5pF

10K

100K

1M

FREQUENCY (Hz)

10M

100M

5

6

7

8

9

10

TOTAL I (mA)

S

FIGURE 9. EL1508CM SINGLE-ENDED CONFIGURATION

FREQUENCY RESPONSE vs C

FIGURE 10. PEAKING vs I +

S

L

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

V =±12V

V =±7.5V

S

R

=3kΩ

R

=3kΩ

FB

V

L

FB

A =10

R =100Ω

A =10

V

R =100Ω

L

0

2

4

6

8

10

5

7

9

11

13

15

R

(kΩ)

I

(mA)

ADJ

SUPPLY

FIGURE 11. PEAKING vs R

FIGURE 12. PEAKING vs I +

S

ADJ

FN7014.5

March 26, 2007

7

EL1508

Typical Performance Curves (Continued)

0

-20

40

30

20

10

0

-40

A to B

-60

B to A

-80

-100

10K

100K

1M

10M

100M

10K

100K

1M

FREQUENCY (Hz)

10M

100M

FREQUENCY (Hz)

FIGURE 13. OUTPUT IMPEDANCE

FIGURE 14. CHANNEL SEPARATION

1.4

100

V =±12V

S

R

A =2

R

=3kΩ

FB

V

1.2

1.0

0.8

0.6

0.4

0.2

0

=0Ω

SET

DIFF GAIN

CURRENT NOISE

VOLTAGE NOISE

10

DIFF PHASE

1

10

100

1K

10K

100K

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FREQUENCY (Hz)

NUMBER of 150Ω RESISTOR LOADS

FIGURE 15. VOLTAGE AND CURRENT NOISE vs FREQUENCY

FIGURE 16. DIFFERENTIAL GAIN/PHASE, F =3.58MHz

O

(2/3 POWER MODE)

0.30

0.08

V =±12V

S

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

R

A =2

R

=3kΩ

R

=3kΩ

FB

V

FB

DIFF PHASE

0.25

0.20

0.15

0.10

0.05

0

A =2

V

DIFF GAIN

=0Ω

R

=0Ω

SET

DIFF GAIN

DIFF PHASE

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1

2

3

4

5

NUMBER of 150Ω RESISTOR LOADS

FIGURE 17. DIFFERENTIAL GAIN/PHASE, F =3.58MHz

O

FIGURE 18. DIFFERENTIAL GAIN/PHASE, F =3.58MHz

O

(2/3 POWER MODE)

(FULL POWER MODE)

FN7014.5

March 26, 2007

8

EL1508

Typical Performance Curves - 24 Ld QFN Package

FREQ=1MHz

0

-20

FREQ=1MHz

-10

V =±5V

V =±12V

S

R

=0

R

=0

SET

R =100Ω

L

GAIN=10

-30

-50

-70

-90

GAIN=10

-40

HD3

-60

HD2

-80

-100

0

1

2

3

4

5

6

7

8

9

0

5

10

V

15

20

25

V

(V)

OUTP-P

FIGURE 19. HARMONIC DISTORTION TEST

(1/3 POWER MODE)

FIGURE 20. HARMONIC DISTORTION TEST

(1/3 POWER MODE)

0

FREQ=1MHz

-10

V =±5V

V =±12V

S

R

=0

R

=0

SET

L

-20

-40

SET

-20

-30

-40

-50

-60

-70

-80

-90

R =100Ω

GAIN=10

HD3

L

GAIN=10

HD3

HD2

-60

HD2

7

-80

-100

0

1

2

3

4

5

6

8

9

0

5

10

15

V

(V)

V

(V)

OUTP-P

OUTp-p

FIGURE 21. HARMONIC DISTORTION TEST

(2/3 POWER MODE)

FIGURE 22. HARMONIC DISTORTION TEST

(2/3 POWER MODE)

0

FREQ=1MHz

-10

V =±5V

V =±12V

S

R

=0

R

=0

SET

L

-20

-30

-40

-50

-60

-70

-80

-90

-100

-20

-40

SET

R =100Ω

GAIN=10

L

HD3

GAIN=10

HD3

HD2

-60

-80

HD2

6

-100

0

1

2

3

4

5

7

8

9

0

5

10

15

V

(V)

V

(V)

OUTP-P

OUTp-p

FIGURE 23. HARMONIC DISTORTION TEST

(FULL POWER MODE)

FIGURE 24. HARMONIC DISTORTION TEST

(FULL POWER MODE)

FN7014.5

March 26, 2007

9

EL1508

Typical Performance Curves - 20 Ld SOIC (0.300") Package

0

FREQ=1MHz

V =±12V

FREQ=1MHz

V =±5V

-10

-30

-50

-70

-90

S

R

=0

SET

L

R

=0

SET

L

R =100Ω

GAIN=10

-20

-40

-60

-80

R =100Ω

GAIN=10

HD 2

HD2

3

HD 3

20

HD3

0

5

10

V

15

(V)

25

0

1

2

4

5

6

7

8

9

V

(V)

OUTP-P

FIGURE 25. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (1/3 POWER MODE)

FIGURE 26. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (1/3 POWER MODE)

FREQ=1MHz

-10

-30

-50

-70

-90

V =±12V

V =±5V

S

R

=0

R

=0

SET

R =100Ω

L

GAIN=10

-30

-50

-70

-90

HD 2

HD2

3

HD 3

HD3

5

0

1

2

4

6

7

8

9

0

5

10

15

(V)

20

25

V

(V)

V

OUTP-P

FIGURE 27. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (2/3 POWER MODE)

FIGURE 28. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (2/3 POWER MODE)

0

FREQ=1MHz

-10

-30

-50

-70

-90

V =±12V

V =±5V

S

R =0

R

=0

SET

-20

-40

SET

R =100Ω

L

GAIN=10

HD 2

HD 3

-60

HD2

-80

HD3

4

-100

0

5

10

V

15

(V)

20

25

0

1

2

3

5

6

7

8

V

(V)

OUTP-P

FIGURE 29. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (FULL POWER MODE)

FIGURE 30. HARMONIC DISTORTION vs DIFFERENTIAL

OUTPUT VOLTAGE (FULL POWER MODE)

FN7014.5

March 26, 2007

10

EL1508

Typical Performance Curves

FREQ=1MHz

V =±5V

FREQ=1MHz

-10

-30

-50

-70

-90

V =±5V

-10

-30

-50

-70

S

R

=6.81kΩ

R

=6.81kΩ

SET

L

SET

R =100Ω

GAIN=10

R =100Ω

L

GAIN=10

HD3

HD 3

HD 2

2

HD2

7

0

1

3

4

5

6

7

8

9

0

1

2

3

4

5

6

8

9

V

(V)

V

(V)

OUTP-P

FIGURE 31. EL1508CM HARMONIC DISTORTION vs

DIFFERENTIAL OUTPUT VOLTAGE

(FULL POWER MODE)

FIGURE 32. EL1508CL HARMONIC DISTORTION TEST

(FULL POWER MODE)

0

FREQ=1MHz

V =±12V

S

R

=6.81kΩ

R

=6.81kΩ

-20

-40

SET

-20

-40

-60

-80

R =100Ω

L

HD3

GAIN=10

HD 2

-60

HD2

-80

HD 3

20

-100

0

5

10

15

(V)

25

0

5

10

15

20

25

V

(V)

OUTP-P

FIGURE 33. EL1508CM HARMONIC DISTORTION vs

DIFFERENTIAL OUTPUT VOLTAGE

(FULL POWER MODE)

FIGURE 34. EL1508CL HARMONIC DISTORTION TEST

(FULL POWER MODE)

V

OUT

V

OUT

C , C

0

1

C , C

0

1

2V/DIV

40ns/DIV

FIGURE 35. DISABLE TIME

FIGURE 36. ENABLE TIME

FN7014.5

March 26, 2007

11

EL1508

Typical Performance Curves (Continued)

21.6

21.4

21.2

25

21

17

13

9

V =±12V

S

R

=10

FB

V

A =10

R =100Ω

L

21.0

FREQ=100kHz

V =±12V

20.8

S

R

=0

SET

A =10

V

20.6

5

50

70

90

110

130

150

170

190

0

2

4

6

8

10

DIFFERENTIAL LOAD RESISTANCE (Ω)

R

(kΩ)

ADJ

FIGURE 37. LOAD RESISTANCE vs OUTPUT VOLTAGE

(ALL POWER MODES)

FIGURE 38. I + vs R

(FULL POWER MODE)

ADJ

S

30

4.5

4.0

+

-

25

20

15

10

5

θ

= 30°C/W

JA

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

+

-

θ

= 43°C/W

= 53°C/W

JA

θ

JA

+

-

θ

= 80°C/W

JA

0

2

4

6

8

10

12

-40

-20

0

20

40

60

80

100

AMBIENT TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

FIGURE 39. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 40. POWER DISSIPATION vs AMBIENT

TEMPERATURE for VARIOUS MOUNTED θ

s

JA

(See Thermal Resistance Curve on page 15)

USING ELANTEC EL1503CS DEMO BOARD, 2”X2”

(4-LAYER). DEMO BOARD WITH HEATSINK VIA

INTERNAL GROUND PLANE

USING JEDEC JESD51-3 HIGH EFFECTIVE THERMAL

CONDUCTIVITY. (4-LAYER) TEST BOARD, QFN

EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5

4

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3

3.378W

2.5

2

1.5

1

0.5

0

-40

-20

0

20

40

60

80

100

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 41. 16 LD SOIC POWER DISSIPATION and THERMAL

RESISTANCE

FIGURE 42. 24 LD QFN POWER DISSIPATION vs AMBIENT

TEMPERATURE

FN7014.5

March 26, 2007

12

EL1508

the average output current, I , or 1/2 I , whichever is the

Applications Information

O

Q

lowest. We’ll call this term I .

X

The EL1508 consists of two high-power line driver amplifiers

that can be connected for full duplex differential line

transmission. The amplifiers are designed to be used with

signals up to 4MHz and produce low distortion levels. The

EL1508 has been optimized as a line driver for ADSL CO

application. The driver output stage has been sized to

provide full ADSL CO power level of 20dBM onto the

telephone lines. Realizing that the actual peak output

voltages and currents vary with the line transformer turns

ratio, the EL1508 is designed to support 450mA of output

current which exceeds the level required for 1:2 transformer

ratio. A typical ADSL interface circuit is shown in Figure 43

below. Each amplifier has identical positive gain

Therefore, we can determine a quiescent current with the

equation:

P

= V × (I – 21 )

S S X

Dquiescent

where:

V is the supply voltage (V + to V -)

S

I

is the operating supply current (I + - I -) / 2

S S

S

is the lesser of I or 1/2 I

X

O

Q

The dissipation in the output stage has two main

contributors. Firstly, we have the average voltage drop

across the output transistor and secondly, the average

output current. For minimal power dissipation, the user

should select the supply voltage and the line transformer

ratio accordingly. The supply voltage should be kept as low

as possible, while the transformer ratio should be selected

so that the peak voltage required from the EL1508 is close to

the maximum available output swing. There is a trade off,

however, with the selection of transformer ratio. As the ratio

is increased, the receive signal available to the receivers is

reduced.

connections, and optimum common-mode rejection occurs.

Further, DC input errors are duplicated and create common-

mode rather than differential line errors.

DRIVER

INPUT+

R

LINE +

OUT

+

-

R

F

2R

Z

LINE

G

R

OUT

-

DRIVER

INPUT-

+

LINE -

Once the user has selected the transformer ratio, the

dissipation in the output stages can be selected with the

following equation:

R

F

R

IN

-

RECEIVE

OUT +

V

S

+

⎛

⎝

⎞

– V

-------

P

= 2 × I

×

Dtransistors

O

⎠

RECEIVE

2

AMPLIFIERS

+

-

F

R

where:

R

IN

RECEIVE

OUT -

V is the supply voltage (V + to V -)

S

V

is the average output voltage per channel

FIGURE 43. TYPICAL LINE INTERFACE CONNECTION

O

I

is the average output current per channel

O

Input Connections

The overall power dissipation (P

) is obtained by adding

DISS

The EL1508 amplifiers are somewhat sensitive to source

impedance. In particular, they do not like being driven by

inductive sources. More than 100nH of source impedance

can cause ringing or even oscillations. This inductance is

equivalent to about 4” of unshielded wiring, or 6” of

unterminated transmission line. Normal high-frequency

construction obviates any such problem.

P

and P .

Dtransistor

Dquiescent

Estimating Line Driver Power Dissipation in ADSL

CO Applications

Figure 44 on the following page shows a typical ADSL CO

line driver implementation. The average line power

requirement for the ADSL CO application is 20dBM

(100mW) into a 100Ω line. The average line voltage is

Power Supplies and Dissipation

3.16V

. The ADSL DMT peak to average ratio (crest

RMS

Due to the high power drive capability of the EL1508, much

attention needs to be paid to power dissipation. The power

that needs to be dissipated in the EL1508 has two main

contributors. The first is the quiescent current dissipation.

The second is the dissipation of the output stage.

factor) of 5.3 implies peak voltage of 16.7V into the line.

Using a differential drive configuration and transformer

coupling with standard back termination, a transformer ratio

of 1:1 is selected. With 1:1 transformer ratio, the impedance

across the driver side of the transformer is 100Ω, the

The quiescent power in the EL1508 is not constant with

varying outputs. In reality, 50% of the total quiescent supply

current needed to power each driver is converted in to output

current. Therefore, in the equation below we should subtract

average voltage is 3.16V

and the average current is

RMA

31.6mA. The power dissipated in the EL1508 is a

FN7014.5

March 26, 2007

13

EL1508

combination of the quiescent power and the output stage

power when driving the line:

PCB Layout Considerations for QFN and SOIC

Packages

The EL1508 die is packaged in three different thermally-

efficient packages: a 20 Ld SOIC (0.300”), a 16 Ld SOIC

(0.150”), and a 24 Ld QFN. The 16 Ld SOIC has the same

external dimensions as a standard 0.150” width SOIC

package, but has the center four leads (two per side)

internally-fused for heat transfer purposes. Both packages

can use PCB surface metal vias areas and internal ground

planes, to spread heat away from the package. The larger

the PCB area the lower the junction temperature of the

device will be. In XDSL applications, multiple layer circuit

boards with internal ground plane are generally used. 13 mil

vias are recommended to connect the metal area under the

device with the internal ground plane. Examples of the PCB

layouts are shown in the figures below that result in thermal

Pd = P

+ P

output-stage

quiescent

Pd = V × I + (V – 2 × V

) × I

OUT-RMS

S

Q

S

OUT-RMS

In the full power mode and with 6.8k R

registers, the

ADJ

EL1508 consumes typically 7mA quiescent current and still

able to maintain very low distortion. The distortion results are

shown in typical performance section of the data sheet.

When driving a load, a large portion (about 50%) of the

quiescent current becomes output load current:

Pd = 12 × (7mA × 50%) + (12V – 3.16) × 31.6mA × 2

where:

resistance θ of 37°C/W for the QFN package and 47°C/W

JA

Pd = 598mW

for the SOIC package. The thermal resistance is obtained

with the EL1508CL and CS demo boards. The demo board

is a 4-layer board built with 2oz. copper and has a dimension

The θ requirement needs to be calculated. This is done

using the equation:

JA

2

of 4in . Note, the user must follow the thermal layout

T

– T

AMB

JUNCT

--------------------------------------------

Θ

=

guideline to achieve these results. In addition to lower

thermal resistance, the QFN package exhibits much lower

2nd harmonic distortion.

JA

P

DISS

where:

A separate Application Note for the QFN package and layout

recommendations is also available.

T

is the maximum die temperature (150°C)

JUNCT

T

is the maximum ambient temperature (85°C)

is the dissipation calculated above

AMB

P

DISS

θ

is the junction to ambient thermal resistance for the

JA

package when mounted on the PCB

150 – 85

598mW

----------------------

= 108°C/W

Θ

=

JA

V +

R

T

S

T +

X

+

-

10

0.22µF

V -

S

TXFR 1:1

R

F

FROM

AFE

3k

100

2R

G

TOP (24 LD QFN)

1.5kΩ

T -

V +

R

T

S

+

-

X

10

V -

0.22µF

S

R

F

3k

FIGURE 44. TYPICAL ADSL CO LINE DRIVER

IMPLEMENTATION

INTERNAL GROUND PLANE (24 LD QFN)

FN7014.5

March 26, 2007

14

EL1508

55

50

Note: 2OZ COPPER USED

TOP FOIL ONLY-WITH SOLDER MASK

2

TOP FOIL-WITH 0.45in

BOTTOM FOIL WITH MANY

FEEDTHROUGHS

45

40

35

TOP FOIL ONLY-NO SOLDER MASK

30

0

2

4

6

8

10

2

AREA OF CIRCUIT BOARD HEAT SINK (in )

TOP (16 Ld SO)

FIGURE 45. THERMAL RESISTANCE of 20 LD SO (0.300")

EL1508 vs BOARD COPPER AREA

Power Control Function

The EL1508 contains two forms of power control operation.

Two digital inputs, C and C , can be used to control the

0

1

supply current of the EL1508 drive amplifiers. As the supply

current is reduced, the EL1508 will start to exhibit slightly

higher levels of distortion and the frequency response will be

limited. The 4 power modes of the EL1508 are set up as

shown in the following table:

TABLE 1. POWER MODES OF THE EL1508

C

OPERATION

I full power mode

S

1

0

INTERNAL GROUND PLANE (16 Ld SO)

0

1

0

1

2/3 I power mode

S

1/3 I power mode

S

EL1508CM PCB Layout Considerations

The 20 Ld SOIC (0.300") Power Package is designed so that

heat may be conducted away from the device in an efficient

manner. To disperse this heat, the center four leads on either

side of the package are internally fused to the mounting

platform of the die. Heat flows through the leads into the

circuit board copper, then spreads and convects to air. Thus,

the ground plane on the component side of the board

becomes the heatsink. This has proven to be a very effective

technique, but several aspects of board layout should be

noted. First, the heat should not be shunted to internal

copper layers of the board nor backside foil, since the

feedthroughs and fiberglass of the board are not very

thermally conductive. To obtain the best thermal resistance

Power-down

Another method for controlling the power consumption of the

EL1508 is to connect a resistor from the I pin to ground.

When the I

current per channel is as per the specifications table on page

2. When a resistor is inserted, the supply current is scaled

according to the “R

Curves section.

ADJ

pin is grounded (the normal state), the supply

ADJ

vs I ” graphs in the Performance

S

SET

Both methods of power control can be used simultaneously.

In this case, positive and negative supply currents (per amp)

are given by the equations below:

of the mounted part, θ , the topside copper ground plane

12.4mA

JA

------------------------------------------------------

I + = 0.9mA +

× (2/3C + 1/3C )

1 0

S

(1 + R

÷ 1574Ω)

should have as much area as possible and be as thick as

practical. If possible, the solder mask should be cut away

from the EL1508 to improve thermal resistance. Finally,

metal heatsinks can be placed against the board close to the

part to draw heat toward the chassis. The graph below

SET

12.4mA

------------------------------------------------------

I - =

× (2/3C + 1/3C )

1 0

S

(1 + R

÷ 1574Ω)

SET

Output Loading

shows various θ s for the 20 Ld SOIC mounted on different

JA

While the drive amplifiers can output in excess of 500mA

transiently, the internal metallization is not designed to carry

more than 100mA of steady DC current and there is no

copper foil areas.

FN7014.5

March 26, 2007

15

EL1508

current-limit mechanism. This allows safely driving rms

sinusoidal currents of 2 x 100mA, or 200mA. This current is

more than that required to drive line impedances to large

output levels, but output short circuits cannot be tolerated.

The series output resistor will usually limit currents to safe

values in the event of line shorts. Driving lines with no series

resistor is a serious hazard.

Single Supply Operation

The EL1508 can also be powered from a single supply

voltage. When operating in this mode, the GND pins can still

be connected directly to GND. To calculate power

dissipation, the equations in the previous section should be

used, with V equal to half the supply rail.

S

Feedback Resistor Value

The amplifiers are sensitive to capacitive loading. More than

25pF will cause peaking of the frequency response. The

same is true of badly terminated lines connected without a

series matching resistor.

The bandwidth and peaking of the amplifiers varies with

supply voltage somewhat and with gain settings. The

feedback resistor values can be adjusted to produce an

optimal frequency response. Here is a series of resistor

values that produce an optimal driver frequency response

(1dB peaking) for different supply voltages and gains:

Output AC Coupling

When in power-down mode, several volts of differential

voltage may appear across the line driver outputs. If DC

current path exists between the two outputs, large DC

current can flow from the positive supply rail to the negative

supply rail through the outputs. To avoid DC current flow, the

most effective solution is to place DC blocking capacitors in

series at the outputs, as shown by the 0.22µF capacitors in

Figure 44.

TABLE 2. OPTIMUM DRIVER FEEDBACK RESISTOR FOR

VARIOUS GAINS AND SUPPLY VOLTAGES

DRIVER VOLTAGE GAIN

SUPPLY

VOLTAGE

2.5

5

10

3k

±5V

3.5k

3.25k

±12V

Power Supplies

The power supplies should be well bypassed close to the

EL1508. A 2.2µF tantalum capacitor and a 0.1µF ceramic

capacitor for each supply works well. Since the load currents

are differential, they should not travel through the board

copper and set up ground loops that can return to amplifier

inputs. Due to the class AB output stage design, these

currents have heavy harmonic content. If the ground

terminal of the positive and negative bypass capacitors are

connected to each other directly and then returned to circuit

ground, no such ground loops will occur. This scheme is

employed in the layout of the EL1508 demonstration board,

and documentation can be obtained from the factory.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7014.5

March 26, 2007

16

EL1508

Small Outline Package Family (SO)

A

D

h X 45°

(N/2)+1

N

A

PIN #1

I.D. MARK

E1

E

c

SEE DETAIL “X”

1

(N/2)

B

L1

0.010 M

C A B

e

H

C

A2

A1

GAUGE

PLANE

SEATING

PLANE

0.010

L

4° ±4°

0.004 C

b

0.010 M

C

A

B

DETAIL X

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

SO24

(SOL-24)

SO28

(SOL-28)

SYMBOL

SO-8

0.068

0.006

0.057

0.017

0.009

0.193

0.236

0.154

0.050

0.025

0.041

0.013

8

SO-14

0.068

0.006

0.057

0.017

0.009

0.341

0.236

0.154

0.050

0.025

0.041

0.013

14

(SOL-20)

0.104

0.007

0.092

0.017

0.011

0.504

0.406

0.295

0.050

0.030

0.056

0.020

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.068

0.006

0.057

0.017

0.009

0.390

0.236

0.154

0.050

0.025

0.041

0.013

16

0.104

0.007

0.092

0.017

0.011

0.406

0.295

0.050

0.030

0.056

0.020

16

0.104

0.007

0.092

0.017

0.011

0.606

0.406

0.295

0.050

0.030

0.056

0.020

24

0.104

0.007

0.092

0.017

0.011

0.704

0.406

0.295

0.050

0.030

0.056

0.020

28

-

±0.003

±0.002

±0.003

±0.001

±0.004

±0.008

±0.004

Basic

-

c

-

D

1, 3

E

-

E1

e

2, 3

-

L

±0.009

Basic

-

L1

h

-

Reference

-

N

-

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

FN7014.5

March 26, 2007

17

EL1508

QFN (Quad Flat No-Lead) Package Family

MDP0046

QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY

(COMPLIANT TO JEDEC MO-220)

A

MILLIMETERS

D

B

SYMBOL QFN44 QFN3

QFN32

TOLERANCE

±0.10

NOTES

A

A1

b

0.90

0.02

0.25

0.20

7.00

5.10

7.00

5.10

0.50

0.55

44

0.90 0.90

0.90

0.02

0.22

0.20

5.00

-

0.02 0.02

0.25 0.23

0.20 0.20

5.00 8.00

+0.03/-0.02

±0.02

1

2

3

PIN #1

I.D. MARK

-

c

Reference

Basic

-

E

D

-

D2

E

3.80 5.80 3.60/2.48

7.00 8.00 6.00

5.80 5.80 4.60/3.40

Reference

Basic

8

-

2X

0.075 C

E2

e

Reference

Basic

8

-

0.50 0.80

0.40 0.53

0.50

32

2X

0.075 C

L

±0.05

-

TOP VIEW

N

38

7

32

8

Reference

4

6

5

ND

NE

11

7

11

12

8

9

0.10 M C A B

b

L

MILLIMETERS

SYMBOL QFN28 QFN2 QFN20

PIN #1 I.D.

TOLER-

ANCE NOTES

3

QFN16

0.90

1

2

3

A

0.90

0.02

0.90 0.90

0.90

0.02

±0.10

-

A1

0.02 0.02

0.02

+0.03/

-0.02

(E2)

b

c

0.25

0.20

4.00

2.65

5.00

3.65

0.50

0.40

28

0.25 0.30

0.20 0.20

4.00 5.00

2.80 3.70

5.00 5.00

3.80 3.70

0.50 0.65

0.40 0.40

0.25

0.20

4.00

2.70

4.00

2.70

0.50

0.40

20

0.33

±0.02

-

0.20 Reference

4.00 Basic

2.40 Reference

4.00 Basic

2.40 Reference

5

NE

D

-

D2

E

-

7

(D2)

E2

e

-

BOTTOM VIEW

0.65

0.60

16

Basic

-

L

±0.05

-

0.10 C

e

N

24

5

20

5

Reference

4

6

5

C

ND

NE

6

5

4

SEATING

PLANE

8

7

5

4

Rev 11 2/07

0.08 C

NOTES:

SEE DETAIL "X"

N LEADS

& EXPOSED PAD

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Tiebar view shown is a non-functional feature.

SIDE VIEW

3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.

4. N is the total number of terminals on the device.

(c)

2

5. NE is the number of terminals on the “E” side of the package

(or Y-direction).

A

C

6. ND is the number of terminals on the “D” side of the package

(or X-direction). ND = (N/2)-NE.

(L)

A1

7. Inward end of terminal may be square or circular in shape with radius

(b/2) as shown.

N LEADS

DETAIL X

8. If two values are listed, multiple exposed pad options are available.

Refer to device-specific datasheet.

FN7014.5

March 26, 2007

18

型号:	EL1508CMZ
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	INTERSIL CORP
零件包装代码：	SOIC
包装说明：	0.300 INCH, ROHS COMPLIANT, MS-013, SO-20
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.59
Is Samacsys：	N
差分输出：	NO
驱动器位数：	2
高电平输入电流最大值：	0.000006 A
输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE DRIVER
接口标准：	GENERAL PURPOSE
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3
长度：	12.8 mm
湿度敏感等级：	3
标称负供电电压：	-12 V
功能数量：	2
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
最小输出摆幅：	19.6 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	+-12 V
认证状态：	Not Qualified
最大接收延迟：
座面最大高度：	2.65 mm
子类别：	Line Driver or Receivers
最大供电电压：	12 V
最小供电电压：	5 V
标称供电电压：	12 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm
Base Number Matches：	1

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