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产品型号EL1883ISZ-T7的概述

芯片EL1883ISZ-T7概述 EL1883ISZ-T7是一款由美国信号处理器制造商Intersil（现为Renesas Electronics的一部分）推出的高性能电压控制振荡器（VCO）线性放大器。该芯片以其较好的频率响应和低失真特点，广泛应用于信号处理、通信设备、电视接收器及其他多种电子设备中。根据其目标应用，EL1883ISZ-T7可提供稳定的增益特性和可靠的电信号转换功能。作为一种双极型集成电路，EL1883ISZ-T7具有优良的噪声表现和线性响应，适用于各种频率信号的放大。该芯片的设计使其能够在极低功耗下高效运行，满足当今电子产品对节能的需求。无论是在消费电子还是在工业设备中，其稳定性和适应性使其成为客户的优先选择。芯片EL1883ISZ-T7的详细参数 EL1883ISZ-T7的主要参数包括： - 电源电压范围：3V至15V。 - 增益带宽积：高达100MHz，这使...

产品型号EL1883ISZ-T7的Datasheet PDF文件预览

EL1883

Data Sheet

July 26, 2004

FN7010.1

Sync Separator with Horizontal Output

Features

The EL1883 video sync separator is

manufactured using Elantec’s high

• NTSC, PAL, SECAM, non-standard video sync separation

• Fixed 70mV slicing of video input levels from 0.5V to

P-P

performance analog CMOS process.

This device extracts sync timing information from both

standard and non-standard video input and also in the

presence of Macrovision pulses. It provides composite sync,

vertical sync, burst/back porch timing, and horizontal

outputs. Fixed 70mV sync tip slicing provides sync edge

• Low supply current - 1.5mA typ.

• Single 3V to 5V supply

• Composite sync output

• Vertical output

detection when the video input level is between 0.5V

and

P-P

(sync tip amplitude 143mV to 572mV). A single

P-P

• Horizontal output

external resistor sets all internal timing to adjust for various

video standards. The composite sync output follows video in

sync pulses and a vertical sync pulse is output on the rising

edge of the first vertical serration following the vertical pre-

equalizing string. For non-standard vertical inputs, a default

vertical pulse is output when the vertical signal stays low for

longer than the vertical sync default delay time. The

horizontal output gives horizontal timing with pre/post

equalizing pulses.

• Burst/back porch output

• Macrovision compatible

• Available in 8-pin SO package

• Pb-free available

Applications

• Video amplifiers

• PCMCIA applications

• A/D drivers

The EL1883 is available in an 8-pin SO package and is

specified for operation over the full -40°C to +85°C

temperature range.

• Line drivers

Ordering Information

• Portable computers

• High speed communications

• RGB applications

• Broadcast equipment

• Active filtering

PART

NUMBER

PACKAGE

8-Pin SO

TAPE & REEL PKG. DWG. #

EL1883IS

7”

13”

MDP0027

EL1883IS-T7

EL1883IS-T13

EL1883ISZ

(See Note)

8-Pin SO

(Pb-free)

Demo Board

• A dedicated demo board is available

EL1883ISZ-T7

(See Note)

8-Pin SO

(Pb-free)

7”

MDP0027

Pinout

EL1883ISZ-

T13 (See Note)

8-Pin SO

(Pb-free)

13”

EL1883

(8-PIN SO)

TOP VIEW

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

VDD

COMPOSITE SYNC OUT

COMPOSITE VIDEO IN

VERTICAL SYNC OUT

GND

HORIZONTAL OUTPUT

RSET

BURST/BACK

PORCH OUTPUT

CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL1883

Absolute Maximum Ratings (T = 25°C)

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW

Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+0.5V

Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified

temperature and are pulsed tests, therefore: T = T = T

DC Electrical Specifications

= 3.3V, T = 25°C, R = 681kΩ, Unless Otherwise Specified.

SET

PARAMETER

DESCRIPTION

MIN

0.75

1.35

TYP

1.5

MAX

UNIT

, Quiescent

= 5V

Pin 2, I

Clamp Voltage

= -100µA

1.5

1.65

LOAD

Clamp Discharge Current

Clamp Charge Current

Pin 2 = 2V

Pin 2 = 1V

Pin 6

µA

-0.85

1.1

-0.65

1.22

0.24

3.2

-0.45

1.35

0.5

Pin Reference Voltage

SET

Output Low Voltage

Output High Voltage

= 1.6mA

= -40µA

= -1.6mA

2.5

3.0

Dynamic Characteristics

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Comp Sync Prop Delay, t

See Figure 13

Horizontal Sync Delay, t

Horizontal Sync Width

3.8

190

5.2

230

6.2

300

µs

Vertical Sync Width, t

Normal or Default Trigger, 50%-50%

See Figure 14

µs

Vertical Sync Default Delay, t

µs

VSD

Burst/Back Porch Delay, t

Burst/Back Porch Width, t

Input Dynamic Range

See Figure 13

120

2.5

0.5

200

3.5

300

4.5

See Figure 13

µs

Video Input Amplitude to Maintain Slice

P-P

Level Spec, V

= 5V

Slice Level

above V

SLICE

CLAMP

EL1883

Pin Descriptions

PIN NUMBER

PIN NAME

PIN FUNCTION

Composite Sync Out Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge

Composite Video In

Vertical Sync Out

GND

AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)

Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period

Supply ground

Burst/Back Porch

Output

Burst/back porch output; low during burst portion of composite video

RSET (Note)

An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for

NTSC signals

Horizontal Output

VDD 5V

Horizontal output; falling edge active

Positive supply (5V)

NOTE: R

SET

must be a 1% resistor

Typical Performance Curves

= 3V, V

= 5V, T = 25°C

T = 25°C

900

800

700

600

500

400

300

200

100

300

250

200

150

100

=5V

=3V

200

100

200

300

400

500

(kΩ)

600

700

800

FREQUENCY (kHz)

SET

FIGURE 1. R

SET

vs HORIZONTAL FREQUENCY

FIGURE 2. BURST/BACK PORCH DELAY vs R

SET

= 25°C

T = 25°C

4.5

=5V

=3V

3.5

=3V

=5V

2.5

1.5

0.5

100

200

300

400

500

600

700

800

100

300

500

(kΩ)

700

900

(kΩ)

SET

FIGURE 3. HORIZONTAL SYNC WIDTH vs R

FIGURE 4. BURST/BACK PORCH WIDTH vs R

SET

EL1883

Typical Performance Curves (Continued)

= 25°C

= 681kΩ

SET

300

250

200

150

100

300

250

200

150

100

=3V

=5V

=3V

100

200

300

400

500

600

700

800

-50

-30

-10

(kΩ)

SET

TEMPERATURE (°C)

FIGURE 5. VERTICAL SYNC WIDTH vs R

FIGURE 6. BURST/BACK PORCH DELAY vs TEMPERATURE

SET

= 681kΩ

SET

5.25

5.2

3.62

3.6

=3V

=5V

3.58

3.56

3.54

3.52

3.5

5.15

5.1

4.95

4.9

=5V

3.48

3.46

4.85

-50

-30

-10

-50

-30

-10

TEMPERATURE (°C)

FIGURE 7. HORIZONTAL SYNC WIDTH vs TEMPERATURE

FIGURE 8. BURST/BACK PORCH WIDTH vs TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

= 681kΩ

SET

230

229

228

227

226

225

224

223

222

221

220

1.8

1.6

1.4

1.136W

1.2

=3V

0.8

0.6

0.4

0.2

=5V

-50

-30

-10

75 85 100

125

150

TEMPERATURE (°C)

FIGURE 9. VERTICAL SYNC PULSE WIDTH vs TEMPERATURE

FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

EL1883

Typical Performance Curves (Continued)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

781mW

0.8

0.6

0.4

0.2

75 85 100

125

150

TEMPERATURE (°C)

FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE

SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1

SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3

SIGNAL 1d. BACK PORCH OUTPUT, PIN 5

SIGNAL 1e. HORIZONTAL SYNC OUTPUT, PIN 7

SEE FIG. 12, 13

SEE FIG. 15

FIGURE 12. TIMING DIAGRAM

NOTES:

b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.

c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.

d. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back

porch starts on the rising edge of the serration pulse (with propagation delay).

e. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.

EL1883

FIGURE 13. STANDARD VERTICAL TIMING

FIGURE 14. NON-STANDARD VERTICAL TIMING

EL1883

SLICE

70mV

HORIZONTAL SYNC, PIN 7

No pulses in next

75% of line time

BACK PORCH OUTPUT, PIN 5

FIGURE 15. NON-STANDARD VERTICAL TIMING

I/P SIGNAL

COMPOSITE

SYNC OUT (PIN 1)

HORIZONTAL

OUT (PIN 7)

HORIZONTAL

OUT (PIN 7)

VERTICAL OUT

(PIN 3)

VERTICAL OUT

(PIN 3)

FIGURE 16. EXAMPLE OF EL1883 WITH NTSC SIGNAL THAT

INCLUDES MACROVISION COPY PROTECTION

FIGURE 17. EXAMPLE OF EL1883 WITH 480p SIGNAL THAT

INCLUDES MACROVISION COPY PROTECTION

=681kΩ)

=310kΩ)

SET

EL1883

leading edge of the input H sync, with the same propagation

Applications Information

Video In

delay as composite sync. The half line pulses present in the

input signal during vertical blanking are removed with an

internal 2H line eliminator circuit. This is a circuit that inhibits

horizontal output pulses until 75% of the line time is reached,

then the horizontal output operation is enabled again. Any

signals present on the I/P signal after the true H sync will be

ignored, thus the horizontal output will not be affected by

MacroVision copy protection. When loss of sync, the

Horizontal Sync output is held high.

A simplified block diagram is shown following page.

An AC coupled video signal is input to Video In pin 2 via C1,

nominally 0.1µF. Clamp charge current will prevent the

signal on pin 2 from going any more negative than Sync Tip

Ref, about 1.5V. This charge current is nominally about 1mA.

A clamp discharge current of about 10µA is always

attempting to discharge C1 to Sync Tip Ref, thus charge is

lost between sync pulses that must be replaced during sync

pulses. The droop voltage that will occur can be calculated

from IT = CV, where V is the droop voltage, I is the discharge

current, T is the time between sync pulses (sync period -

sync tip width), and C is C1.

SET

An external R

resistor, connected from R

pin 6 to

SET

ground, produces a reference current that is used internally

as the timing reference for vertical sync width, vertical sync

default delay, burst gate delay and burst width. Decreasing

the value of R

increases the reference current, which in

An NTSC video signal has a horizontal frequency of

15.73kHz, and a sync tip width of 4.7µs. This gives a period

of 63.6µs and a time T = 58.9µs. The droop voltage will then

be V = 5.9mV. This is less than 2% of a nominal sync tip

amplitude of 286mV. The charge represented by this droop

is replaced in a time given by T = CV/I, where I = clamp

charge current = 1mA. Here T = 590ns, about 12% of the

sync pulse width of 4.7µs. It is important to choose C1 large

enough so that the droop voltage does not approach the

switching threshold of the internal comparator.

SET

turn decreases reference times and pulse widths. A higher

frequency video input necessitates a lower R

value.

SET

Chroma Filter

A chroma filter is suggested to increase the S/N ratio of the

incoming video signal. Use of the optional chroma filter is

shown in the figure below. It can be implemented very simply

and inexpensively with a series resistor of 620Ω and a

parallel capacitor of 500pF, which gives a single pole roll-off

frequency of about 500kHz. This sufficiently attenuates the

3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet

passes the approximately 15kHz sync signals without

appreciable attenuation. A chroma filter will increase the

propagation delay from the composite input to the outputs.

Composite Sync

The Composite Sync output is simply a reproduction of the

input signal with the active video removed. The sync tip of

the Composite video signal is clamped to 1.5V at pin 2 and

then slices at 70mV above the sync tip reference. The output

signal is buffered out to pin 1. When loss of sync, the

Composite Sync output is held low.

Burst

A low-going burst pulse follows each rising edge of sync,

and lasts approximately 3.5µs for an R

of 681kΩ. When

SET

loss of sync, the Back Porch output is held high.

Vertical Sync

A low-going Vertical Sync pulse is output during the start of

the vertical cycle of the incoming video signal. The vertical

cycle starts with a pre-equalizing phase of pulses with a duty

cycle of about 93%, followed by a vertical serration phase

that has a duty cycle of about 15%. Vertical Sync is clocked

out of the EL1883 on the first rising edge during the vertical

serration phase. In the absence of vertical serration pulses,

a vertical sync pulse will be forced out after the vertical sync

default delay time, approximately 60µS after the last falling

edge of the vertical equalizing phase for R

= 681kΩ.

SET

When loss of sync, the vertical output is held low.

Horizontal Sync

The Horizontal circuit senses the composite sync edges and

produces the true horizontal pulses of nominal width 5.2µs

with R

= 681kΩ. The leading edge is triggered from the

SET

EL1883

Simplified Block Diagram

CLAMP

SYNC TIP REF

1.5V

0.1µF

COMPOSITE

VIDEO IN

COMP.

COMPOSITE

SYNC

620Ω

SLICE

1.57V

0.1µF

510pF

GND

BURST/BACK

PORCH OUT

BURST

SET

SYNC

TIP

0.1µF

REF

GEN

SET

70mV

SLICE

VERTICAL

SYNC OUT

V SYNC

H SYNC

HORIZONTAL

SYNC OUT

NOTE: R

must be at 1% resistor.

SET

2 H

ELIMINATOR

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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