EL4584
of a long pendulum. Due to parasitic effects of PCB traces
and component variables, it will take some trial and error
experimentation to determine the best values to use for any
given situation. Use the component tables as a starting
point, but be aware that deviation from these values is not
out of the ordinary.
possible. VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO operating
point. Coast mode is intended to be used when noise or
signal degradation result in loss of horizontal sync for many
cycles. The phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal sync returns,
sync lock can be re-established quickly. However, if much
VCO drift has occurred, it may take as long to re-lock as
when restarting.
External Divide
DIV SEL (pin 8) controls the use of the internal divider. When
high, the internal divider is enabled and EXT DIV (pin 13)
outputs the CLK out divided by N. This is the signal to which
the horizontal sync input will lock. When divide select is low,
the internal divider output is disabled, and external divide
becomes an input from an external divider, so that a divisor
other than one of the 8 pre-programmed internal divisors can
be used.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any
DC current path from charge pump out will skew EXT DIV
relative to HSYNC in, tending to offset or add to the 110ns
internal delay, depending on which way the extra current is
flowing. This offset is called static phase error, and is always
present in any PLL system. If, when the part stabilizes in a
locked mode, lock detect is not low, adding or subtracting
Normal Mode
Normal mode is enabled by pulling COAST (pin 9) low
from the loop filter series resistor R will change this static
2
(below 1/3*V ). If H
and CLK ÷ N have any phase or
CC SYNC
phase error to allow LDET to go low while in lock. The goal is
to put the rising edge of EXT DIV in sync with the falling
frequency difference, an error signal is generated and sent
to the charge pump. The charge pump will either force
current into or out of the filter capacitor in an attempt to
modulate the VCO frequency. Modulation will continue until
the phase and frequency of CLK ÷ N exactly match the
edge of H
2
+ 110ns. (See timing diagrams.) Increasing
SYNC
R decreases phase error, while decreasing R increases
2
phase error. (Phase error is positive when EXT DIV lags
HSYNC.) The resistance needed will depend on VCO design
or VCXO module selection.
H
input. When the phase and frequency match (with
SYNC
some offset in phase that is a function of the VCO
characteristics), the error signal goes to zero, lock detect no
longer pulses high, and the charge pump enters a high
Applications Information
Choosing External Components
impedance state. The clock is now locked to the H
SYNC
1. To choose LC VCO components, first pick the desired
input. As long as phase and frequency differences remain
small, the PLL can adjust the VCO to remain locked and lock
detect remains low.
operating frequency. For our example we will use
14.31818MHz, with an H
SYNC
frequency of 15.734kHz.
2. Choose a reasonable inductor value (10–20µH works
Fast Lock Mode
well). We choose 15µH.
Fast Lock mode is enabled by either allowing coast to float,
3. Calculate C needed to produce F
T
.
OSC
or pulling it to mid supply (between 1/3 and 2/3*V ). In this
CC
1
F
= ----------------------
mode, lock is achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the
clock is either inhibited or reset to attempt a “fast” lock of the
signals.
OSC
2π LC
T
1
1
C
= -------------------- = --------------------------------------------------------------------- = 8.2pF
T
2
2
2
2
4π F L
4π (14.318e6) (15e – 6)
4. From the varactor data sheet find C @ 2.5V, the desired
V
Forcing the clock to be synchronized to the H
input this
SYNC
lock voltage. C = 23pF for our SMV1204-12, for
V
way allows a lock in approximately 2 H-cycles, but the clock
spacing will not be regular during this time. Once the near
lock condition is attained, charge pump output should be
very close to its lock-on value and placing the device into
normal mode should result in a normal lock very quickly.
example.
5. C should be about 10C , so we choose C = 220pF for
2
V
2
our example.
6. Calculate C . Since:
1
C C C
2 V
Fast Lock mode is intended to be used where H
1
SYNC
C
= ----------------------------------------------------------------------------
T
(C C ) + (C C ) + (C C )′
becomes irregular, until a stable signal is again obtained.
1
2
1
V
2 V
Coast Mode
then:
Coast mode is enabled by pulling COAST (pin 9) high
(above 2/3*V ). In coast mode the internal phase detector
C C C
T V
CC
2
C
= -------------------------------------------------------------------------
1
is disabled and filter out remains in high impedance mode to
keep filter out voltage and VCO frequency as constant a
(C C )–(C C ) – (C C )′
2
V
2
T
T V
FN7174.2
8
July 25, 2005
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