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EL5162, EL5163, EL5262, EL5263, EL5362

®

Data Sheet

January 4, 2008

FN7388.10

500MHz Low Power Current Feedback

Amplifiers with Enable

Features

• 500MHz to 3dB bandwidth

• 4000V/µs slew rate

The EL5162, EL5163, EL5262, EL5263, and EL5362 are

current feedback amplifiers with a bandwidth of 500MHz.

This makes these amplifiers ideal for today’s high speed

video and monitor applications.

• 1.5mA supply current

• Single and dual supply operation, from 5V to 12V supply

span

With a supply current of just 1.5mA and the ability to run

from a single supply voltage from 5V to 12V, these amplifiers

are also ideal for handheld, portable or battery-powered

equipment.

• Fast enable/disable (EL5162, EL5262 and EL5362 only)

• Available in SOT-23 packages

• Pb-free available (RoHS compliant)

The EL5162 also incorporates an enable and disable

function to reduce the supply current to 100µA typical per

amplifier. Allowing the CE pin to float or applying a low logic

level will enable the amplifier.

• High speed, 1.4GHz product available (EL5167 and

EL5167)

• High speed, 4mA, 630MHz product available (EL5164 and

EL5165)

The EL5162 is available in 6 Ld SOT-23 and 8 Ld SOIC

packages, the EL5163 in 5 Ld SOT-23 and SC-70 packages,

the EL5262 in the 10 Ld MSOP package, the EL5263 in 8 Ld

MSOP and SO packages, and the EL5362 in 16 Ld SOIC

(0.150”) and QSOP packages. All operate over the industrial

temperature range of -40°C to +85°C.

Applications

• Battery-powered equipment

• Handheld, portable devices

• Video amplifiers

• Cable drivers

• RGB amplifiers

• Test equipment

• Instrumentation

• Current to voltage converters

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL5162, EL5163, EL5262, EL5263, EL5362

Ordering Information

PART NUMBER

PART MARKING

5162IS

PACKAGE

PKG. DWG. #

MDP0027

EL5162IS

8 Ld SOIC (150 mil)

EL5162IS-T7*

5162IS

5162ISZ

j

MDP0027

MDP0038

P5.049

EL5162IS-T13*

EL5162ISZ (Note)

EL5162ISZ-T7* (Note)

EL5162ISZ-T13* (Note)

EL5162IW-T7*

8 Ld SOIC (150 mil) (Pb-free)

6 Ld SOT-23

EL5162IW-T7A*

j

6 Ld SOT-23

EL5162IWZ-T7* (Note)

EL5162IWZ-T7A* (Note)

EL5163IW-T7*

BAKA

d

6 Ld SOT-23 (Pb-free)

5 Ld SOT-23

EL5163IW-T7A*

d

5 Ld SOT-23

EL5163IWZ-T7* (Note)

EL5163IWZ-T7A* (Note)

EL5163IC-T7*

BALA

5 Ld SOT-23 (Pb-free)

5 Ld SC-70 (1.25mm)

BALA

E

EL5163IC-T7A*

E

5 Ld SC-70 (1.25mm)

P5.049

EL5163ICZ-T7* (Note)

EL5163ICZ-T7A* (Note)

EL5262IY

BDA

5 Ld SC-70 (1.25mm) (Pb-free)

10 Ld MSOP (3.0mm)

10 Ld MSOP (3.0mm) (Pb-free)

8 Ld SOIC (150 mil)

P5.049

BDA

P5.049

BLAAA

BBTAA

5263IS

5263ISZ

BMAAA

BBBJA

EL5362IS

MDP0043

MDP0027

MDP0043

MDP0027

EL5262IY-T7*

EL5262IY-T13*

EL5262IYZ (Note)

EL5262IYZ-T7* (Note)

EL5262IYZ-T13* (Note)

EL5263IS

EL5263IS-T7*

8 Ld SOIC (150 mil)

EL5263IS-T13*

8 Ld SOIC (150 mil)

EL5263ISZ (Note)

EL5263ISZ-T7* (Note)

EL5263ISZ-T13* (Note)

EL5263IY

8 Ld SOIC (150 mil) (Pb-free)

8 Ld MSOP (3.0mm)

EL5263IY-T7*

8 Ld MSOP (3.0mm)

EL5263IY-T13*

8 Ld MSOP (3.0mm)

EL5263IYZ (Note)

EL5263IYZ-T7* (Note)

EL5263IYZ-T13* (Note)

EL5362IS

8 Ld MSOP (3.0mm) (Pb-free)

16 Ld SOIC (150 mil)

EL5362IS-T7*

16 Ld SOIC (150 mil)

EL5362IS-T13*

16 Ld SOIC (150 mil)

FN7388.10

January 4, 2008

2

EL5162, EL5163, EL5262, EL5263, EL5362

Ordering Information (Continued)

PART NUMBER

PART MARKING

EL5362ISZ

5362IU

PACKAGE

16 Ld SOIC (150 mil) (Pb-free)

16 Ld QSOP (150 mil)

PKG. DWG. #

MDP0027

EL5362ISZ (Note)

EL5362ISZ-T7* (Note)

EL5362ISZ-T13* (Note)

EL5362IU

MDP0027

MDP0040

EL5362IU-T7*

5362IU

16 Ld QSOP (150 mil)

EL5362IU-T13*

5362IU

16 Ld QSOP (150 mil)

EL5362IUZ (Note)

EL5362IUZ-T7* (Note)

EL5362IUZ-T13* (Note)

5362IUZ

16 Ld QSOP (Pb-free)

5362IUZ

16 Ld QSOP (Pb-free)

5362IUZ

16 Ld QSOP (Pb-free)

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

FN7388.10

January 4, 2008

3

EL5162, EL5163, EL5262, EL5263, EL5362

Pinouts

EL5162

(8 LD SOIC)

TOP VIEW

EL5162

(6 LD SOT-23)

TOP VIEW

EL5163

(5 LD SOT-23, SC-70)

TOP VIEW

NC

IN-

1

2

3

4

8

7

6

5

CE

OUT

VS-

IN+

1

2

3

6

5

4

VS+

CE

OUT

VS-

IN+

1

2

3

5

VS+

OUT

NC

-

+

-

+

-

IN+

VS-

IN-

4

IN-

EL5262

(10 LD MSOP)

TOP VIEW

EL5263

(8 LD SOIC, MSOP)

EL5362

(16 LD SOIC, QSOP)

TOP VIEW

OUT

IN-

1

2

3

4

5

10 VS+

OUT1

IN-

1

2

3

4

8

7

6

5

VS+

OUT2

IN-

INA+

CEA

VS-

1

2

3

4

5

6

7

8

16 INA-

15 OUTA

14 VS+

-

+

9

8

7

6

OUT

IN-

-

+

-

+

IN+

VS-

CE

IN+

-

+

-

+

-

IN+

CE

VS-

IN+

CEB

INB+

NC

13 OUTB

12 INB-

11 NC

+

-

CEC

INC+

10 OUTC

9

INC-

FN7388.10

January 4, 2008

4

EL5162, EL5163, EL5262, EL5263, EL5362

Absolute Maximum Ratings (T = +25°C)

Thermal Information

A

Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . 13.2V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

S

Slewrate of V + to V -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs

S

Maximum Voltage between IN+ and IN-, disabled. . . . . . . . . . ±1.5V

Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA

Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . V - -0.5V to V + +0.5V

S

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

Electrical Specifications V + = +5V, V - = -5V, R = 750Ω for A = 1, R = 400Ω for A = 2, R = 150Ω, T = +25°C unless otherwise

S

F

V

F

V

L

A

specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCE

BW

-3dB Bandwidth

A

= +1, R = 500Ω, R = 598Ω

500

233

30

MHz

V/µs

V

L

F

A

= +2, R = 150Ω, R = 422Ω

L F

V

BW1

SR

0.1dB Bandwidth

Slew Rate

V

= -2.5V to +2.5V, A = +2, R = 100Ω

2000

2800

2500

4000

6000

O

V

L

(EL5262, EL5263, EL5362)

V

= -2.5V to +2.5V, A = +2, R = 100Ω

4000

V/µs

O

V

L

(EL5162, EL5163)

t

0.1% Settling Time

V

= -2.5V to +2.5V, A = +1

25

3

ns

nV/√Hz

pA/√Hz

%

S

OUT

V

e

Input Voltage Noise

IN- Input Current Noise

IN+ Input Current Noise

N

i -

10

N

i +

N

6.5

0.05

0.15

dG

dP

Differential Gain Error (Note 1)

Differential Phase Error (Note 1)

A = +2

V

A

= +2

°

V

DC PERFORMANCE

V

Offset Voltage

-5

1.5

6

+5

mV

OS

T V

Input Offset Voltage Temperature

Coefficient

Measured from T

MIN

to T

MAX

µV/°C

C

OS

R

Transimpedance

500

1000

kΩ

OL

INPUT CHARACTERISTICS

CMIR

Common Mode Input Range

Guaranteed by CMRR test

= ±3V

±3

50

-1

±3.3

62

V

dB

CMRR

-ICMR

Common Mode Rejection Ratio

- Input Current Common Mode Rejection

+ Input Current

V

75

+1

+8

+10

3

IN

0.22

0.5

2

µA/V

µA

+I

-8

IN

-I

- Input Current

-10

0.8

µA

IN

R

Input Resistance

1.6

1

MΩ

pF

IN

C

Input Capacitance

OUTPUT CHARACTERISTICS

V

Output Voltage Swing

R = 150Ω to GND

±3.35

±3.75

60

±3.6

±3.9

100

±3.75

±4.15

V

O

L

R = 1kΩ to GND

L

I

Output Current

R = 10Ω to GND

mA

OUT

L

FN7388.10

January 4, 2008

5

EL5162, EL5163, EL5262, EL5263, EL5362

Electrical Specifications V + = +5V, V - = -5V, R = 750Ω for A = 1, R = 400Ω for A = 2, R = 150Ω, T = +25°C unless otherwise

S

F

V

F

V

L

A

specified. (Continued)

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

I

Supply Current - Enabled, per Amplifier No load, V = 0V

IN

1.3

-25

0

1.5

-14

10

2.0

0

mA

µA

SON

Supply Current - Disabled, per Amplifier No load, V = 0V

IN

SOFF-

SOFF+

+25

µA

PSRR

-IPSR

Power Supply Rejection Ratio

DC, V = ±4.75V to ±5.25V

65

76

dB

S

- Input Current Power Supply Rejection DC, V = ±4.75V to ±5.25V

-0.5

0.1

+0.5

µA/V

S

ENABLE (EL5162, EL5262, EL5362 ONLY)

t

I

Enable Time

380

800

5

ns

µA

V

EN

Disable Time

DIS

CE Pin Input High Current

CE Pin Input Low Current

CE Input High Voltage for Power-down

CE Input Low Voltage for Power-down

CE = V +

1

25

+1

IHCE

ILCE

S

CE = (V +) -5V

-1

0

S

V

V + - 1

S

IHCE

ILCE

V + - 3

V

S

NOTE:

1. Standard NTSC test, AC signal amplitude = 286mV , f = 3.58MHz

P-P

FN7388.10

January 4, 2008

6

EL5162, EL5163, EL5262, EL5263, EL5362

Typical Performance Curves

+4

+3

+2

+1

0

+4

+3

+2

+1

0

V

R

= +5V

= -5V

= 375Ω

V

R

= +5V

= -5V

= 500Ω

= 598Ω

CC

EE

F

CC

EE

L

F

-1

-2

-3

-4

-5

-6

-1

-2

-3

-4

-5

-6

100k

1M

10M

100M

1G

100k

1M

10M

100M

1G

FREQENCY (Hz)

FREQUENCY (Hz)

FIGURE 1. FREQUENCY RESPONSE FOR A = +1

V

FIGURE 2. FREQUENCY RESPONSE FOR A = +4.6

V

+2

+1

0

+3

+2

+1

0

-1

-2

-3

-4

-1

-2

-3

-4

V

= +5V

= -5V

= +10

= 150Ω

= 375Ω

CC

EE

-5

-6

-7

-8

V

R

= +5V

= -5V

= 150Ω

= 422Ω

CC

EE

L

F

-5

-6

-7

A

V

R

L

F

100k

1M

10M

100M

1G

100k

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 3. FREQUENCY RESPONSE FOR A = +10

V

FIGURE 4. FREQUENCY RESPONSE FOR A = +2

V

+3

+2

+1

0

+5

A

R

= +1

= 150Ω

= 698Ω

V

L

F

+4

+3

+2

+1

0

±6V

-1

-2

-3

-4

-1

-2

-3

-4

-5

V

, V

=

±5V

±4V

CC EE

V

R

= +5V

= -5V

= 150Ω

= 422Ω

CC

EE

L

F

±3V

-5

-6

-7

±2.5V

1M

10M

100M

500M

100k

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 5. FREQUENCY RESPONSE FOR A = +4

V

FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS V , V

CC EE

FN7388.10

January 4, 2008

7

EL5162, EL5163, EL5262, EL5263, EL5362

Typical Performance Curves (Continued)

100

10

1

V

= +5V

= -5V

= +2

V

= +5V

= -5V

= +2

CC

EE

CC

EE

INPUT RISE TIME

1.028ns

A

V

R

= 150Ω

1V/DIV

L

OUTPUT RISE

TIME 2.218ns

2V/DIV

0.1

10k

100k

1M

10M

100M

4ns/DIV

FREQUENCY (Hz)

FIGURE 7. CLOSED LOOP OUTPUT IMPEDANCE

FIGURE 8. EL5262 OUTPUT RISE TIME

V

= +5V

= -5V

= +2

CC

EE

CH 1

A

V

INPUT FALL

TIME 1.036ns

1V/DIV

R

= 150Ω

L

OUTPUT FALL

TIME 2.21ns

2V/DIV

CH 2

CH1 = 5V

CH2 = 200mV

M = 100ns

4ns/DIV

100ns/DIV

FIGURE 9. EL5262 OUTPUT FALL TIME

FIGURE 10. TURN ON TIME

0

V

= +5V

= -5V

= +2

= 150Ω

CC

EE

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

CH1 = 5V

CH2 = 200mV

M = 100ns

A

V

R

L

CH1

CH2

100

1k

10k

100k

1M

10M

100M

100ns/DIV

FREQUENCY (Hz)

FIGURE 11. TURN OFF TIME

FIGURE 12. PSRR (V

)

CC

FN7388.10

January 4, 2008

8

EL5162, EL5163, EL5262, EL5263, EL5362

Typical Performance Curves (Continued)

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= +5V

= -5V

= +2

CC

EE

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

A

V

1.250W

R

= 150Ω

SO16 (0.150”)

L

θ

= +80°C/W

JA

909mW

SO8

= +110°C/W

θ

JA

100

1k

10k

100k

1M

10M

100M

0

25

50

75 85 100

125

150

FREQUENCY (Hz)

AMBIENT TEMPERATURE (°C)

FIGURE 13. PSRR (V

)

FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

EE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.4

0.50

435mW

0.45

1.2

1.0

0.8

0.6

0.4

0.2

0

0.40

893mW

0.35

SOT23-5/6

0.30

0.25

0.20

0.15

0.10

0.05

0

θ

= +230°C/W

JA

QSOP16

= +112°C/W

θ

JA

0

25

50

75 85 100

125

150

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.0

870mW

0.9

909mW

625mW

SO16 (0.15 0”)

= +110°C/W

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

θ

JA

MSOP8/10

0.7

θ

= +115°C/W

JA

0.6

0.5

0.4

0.3

0.2

0.1

0

SO8

= +160°C/W

θ

JA

0

25

50

75 85 100

125

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FN7388.10

January 4, 2008

9

EL5162, EL5163, EL5262, EL5263, EL5362

Typical Performance Curves (Continued)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

1.0

0.8

0.6

0.4

0.2

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

391mW

SOT23-5/6

633mW

θ

= +256°C/W

JA

QSOP16

θ

= +158°C/W

JA

0

25

50

75 85 100

125

150

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.6

0.5

0.4

0.3

0.2

0.1

0

486mW

MSOP8/10

= +206°C/W

θ

JA

0

25

50

75 85 100

125

AMBIENT TEMPERATURE (°C)

FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

FN7388.10

January 4, 2008

10

EL5162, EL5163, EL5262, EL5263, EL5362

SOT-23 Package Family

MDP0038

e1

D

SOT-23 PACKAGE FAMILY

A

MILLIMETERS

6

4

N

SYMBOL

SOT23-5

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

5

SOT23-6

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

6

TOLERANCE

MAX

A

A1

A2

b

±0.05

E1

E

±0.15

2

3

±0.05

0.15

2X

C

D

c

±0.06

1

2

3

0.20

2X

C

D

Basic

5

e

E

Basic

E1

e

Basic

0.20

C

A-B

D

M

B

b

NX

Basic

e1

L

Basic

±0.10

L1

N

Reference

Rev. F 2/07

0.15

2X

C

A-B

1

3

D

NOTES:

C

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

A2

SEATING

PLANE

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

A1

3. This dimension is measured at Datum Plane “H”.

0.10

NX

C

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).

(L1)

H

A

GAUGE

PLANE

0.25

c

+3°

-0°

L

0°

FN7388.10

January 4, 2008

11

EL5162, EL5163, EL5262, EL5263, EL5362

Small Outline Package Family (SO)

A

D

h X 45°

(N/2)+1

N

A

PIN #1

I.D. MARK

E1

E

c

SEE DETAIL “X”

1

(N/2)

B

L1

0.010 M

C A B

e

H

C

A2

A1

GAUGE

PLANE

SEATING

PLANE

0.010

L

4° ±4°

0.004 C

b

0.010 M

C

A

B

DETAIL X

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

SO24

(SOL-24)

SO28

(SOL-28)

SYMBOL

SO-8

0.068

0.006

0.057

0.017

0.009

0.193

0.236

0.154

0.050

0.025

0.041

0.013

8

SO-14

0.068

0.006

0.057

0.017

0.009

0.341

0.236

0.154

0.050

0.025

0.041

0.013

14

(SOL-20)

0.104

0.007

0.092

0.017

0.011

0.504

0.406

0.295

0.050

0.030

0.056

0.020

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.068

0.006

0.057

0.017

0.009

0.390

0.236

0.154

0.050

0.025

0.041

0.013

16

0.104

0.007

0.092

0.017

0.011

0.406

0.295

0.050

0.030

0.056

0.020

16

0.104

0.007

0.092

0.017

0.011

0.606

0.406

0.295

0.050

0.030

0.056

0.020

24

0.104

0.007

0.092

0.017

0.011

0.704

0.406

0.295

0.050

0.030

0.056

0.020

28

-

±0.003

±0.002

±0.003

±0.001

±0.004

±0.008

±0.004

Basic

-

c

-

D

1, 3

E

-

E1

e

2, 3

-

L

±0.009

Basic

-

L1

h

-

Reference

-

N

-

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

FN7388.10

January 4, 2008

12

EL5162, EL5163, EL5262, EL5263, EL5362

Small Outline Transistor Plastic Packages (SC70-5)

D

P5.049

VIEW C

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

e1

INCHES

MIN

MILLIMETERS

SYMBOL

MAX

0.043

0.004

0.039

0.012

0.010

0.009

0.085

0.094

0.053

MIN

0.80

0.00

0.80

0.15

0.08

1.85

1.80

1.15

MAX

1.10

0.10

1.00

0.30

0.25

0.22

0.20

2.15

2.40

1.35

NOTES

5

1

4

A

A1

A2

b

0.031

0.000

0.031

0.006

0.003

0.073

0.071

0.045

-

E

C

L

C

E1

L

2

3

b

b1

c

e

6

3

-

C

L

c1

D

0.20 (0.008) M

C

L

E

E1

e

3

-

SEATING

PLANE

0.0256 Ref

0.0512 Ref

0.010 0.018

0.65 Ref

1.30 Ref

0.26 0.46

A2

A1

A

e1

L

-

-C-

4

-

L1

L2

0.017 Ref.

0.420 Ref.

0.15 BSC

0.10 (0.004)

C

0.006 BSC

o

0

8

0

8

-

α

N

b

WITH

5

PLATING

b1

R

0.004

-

0.10

0.15

-

R1

0.010

0.25

c

c1

Rev. 3 7/07

NOTES:

BASE METAL

1. Dimensioning and tolerances per ASME Y14.5M-1994.

2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.

4X θ1

3. Dimensions D and E1 are exclusive of mold flash, protrusions,

or gate burrs.

R1

4. Footlength L measured at reference to gauge plane.

5. “N” is the number of terminal positions.

R

6. These Dimensions apply to the flat section of the lead between

0.08mm and 0.15mm from the lead tip.

GAUGE PLANE

SEATING

PLANE

7. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

L

C

α

L2

L1

4X θ1

VIEW C

0.4mm

0.75mm

2.1mm

0.65mm

TYPICAL RECOMMENDED LAND PATTERN

FN7388.10

January 4, 2008

13

EL5162, EL5163, EL5262, EL5263, EL5362

Mini SO Package Family (MSOP)

MDP0043

0.25 M C A B

A

MINI SO PACKAGE FAMILY

D

(N/2)+1

MILLIMETERS

N

SYMBOL

MSOP8

1.10

0.10

0.86

0.33

0.18

3.00

4.90

3.00

0.65

0.55

0.95

8

MSOP10

1.10

0.10

0.86

0.23

0.18

3.00

4.90

3.00

0.50

0.55

0.95

10

TOLERANCE

Max.

NOTES

A

A1

A2

b

-

±0.05

-

E

E1

PIN #1

I.D.

±0.09

-

+0.07/-0.08

±0.05

-

c

-

D

±0.10

1, 3

1

B

(N/2)

E

±0.15

-

E1

e

±0.10

2, 3

Basic

-

e

H

C

L

±0.15

-

SEATING

PLANE

L1

N

Basic

-

Reference

-

M

C A B

b

0.08

0.10 C

Rev. D 2/07

N LEADS

NOTES:

1. Plastic or metal protrusions of 0.15mm maximum per side are not

included.

L1

2. Plastic interlead protrusions of 0.25mm maximum per side are

not included.

A

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

SEE DETAIL "X"

A2

GAUGE

PLANE

0.25

L

DETAIL X

A1

3° ±3°

FN7388.10

January 4, 2008

14

EL5162, EL5163, EL5262, EL5263, EL5362

Quarter Size Outline Plastic Packages Family (QSOP)

A

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

D

(N/2)+1

N

INCHES

SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES

A

A1

A2

b

0.068

0.006

0.056

0.010

0.008

0.193

0.236

0.154

0.025

0.041

16

0.068

0.006

0.056

0.010

0.008

0.341

0.236

0.154

0.025

0.041

24

0.068

0.006

0.056

0.010

0.008

0.390

0.236

0.154

0.025

0.041

28

Max.

±0.002

±0.004

±0.002

±0.001

±0.004

±0.008

±0.004

Basic

-

PIN #1

I.D. MARK

E

E1

-

1

(N/2)

c

-

B

D

1, 3

0.010 C A B

E

-

e

E1

e

2, 3

H

-

C

SEATING

L

±0.009

Basic

-

PLANE

L1

N

-

0.007 C A B

b

0.004 C

Reference

-

Rev. F 2/07

L1

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not

included.

A

2. Plastic interlead protrusions of 0.010” maximum per side are not

included.

c

SEE DETAIL "X"

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

0.010

A2

GAUGE

PLANE

L

A1

4°±4°

DETAIL X

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7388.10

January 4, 2008

15

型号:	EL5263IYZ
Brand Name：	Intersil
生命周期：	Unknown
零件包装代码：	MSOP, SOIC
包装说明：	3 MM, ROHS COMPLIANT, MSOP-8
针数：	8, 8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	5.19
Is Samacsys：	N
放大器类型：	OPERATIONAL AMPLIFIER
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e3
长度：	3 mm
湿度敏感等级：	2
功能数量：	2
端子数量：	8
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Operational Amplifier
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3 mm
Base Number Matches：	1

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