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EL5325A

®

Data Sheet

May 8, 2006

FN7447.1

12-Channel TFT-LCD Reference Voltage

Generator with External Shutdown

Features

• 12-channel reference outputs

• Accuracy of ±1%

The EL5325A with external shutdown is designed to produce

the reference voltages required in TFT-LCD applications.

Each output is programmed to the required voltage with 10

bits of resolution. Reference pins determine the high and low

voltages of the output range, which are capable of swinging

to either supply rail. Programming of each output is

• Supply voltage of 5V to 16.5V

• Digital supply 3.3V to 5V

• Low supply current of 10mA

• Rail-to-rail capability

performed using the 3-wire, SPI compatible interface.

A number of EL5325A can be stacked for applications

requiring more than 12 outputs. The reference inputs can be

tied to the rails, enabling each part to output the full voltage

range, or alternatively, they can be connected to external

resistors to split the output range and enable finer

resolutions of the outputs.

• Internal thermal protection

• External shutdown

• Pb-free plus anneal available (RoHS compliant)

Applications

• TFT-LCD drive circuits

• Reference voltage generators

The EL5325A has 12 outputs and is available in a 28 Ld

TSSOP package. They are specified for operation over the

full -40°C to +85°C temperature range.

Pinout

EL5325A

(28 LD TSSOP/HTSSOP)

TOP VIEW

Ordering Information

PART

TAPE&

PKG.

NUMBER

MARKING REEL

PACKAGE

DWG. #

ENA

SDI

1

2

28 OUTA

EL5325AIREZ

(Note)

5325AIREZ

-

28 Ld HTSSOP MDP0048

(Pb-Free)

27

26

25

24

23

22

21

20

19

18

17

16

OUTB

OUTC

GND

EL5325AIREZ-T7 5325AIREZ

(Note)

7”

28 Ld HTSSOP MDP0048

(Pb-Free)

3

SCLK

SDO

4

EL5325AIREZ-T13 5325AIREZ

(Note)

13”

-

28 Ld HTSSOP MDP0048

(Pb-Free)

5

EXT_OSC

VS

OUTD

OUTE

OUTF

OUTG

OUTH

OUTI

EL5325AIRZ

(Note)

5325AIRZ

28 Ld TSSOP MDP0044

(Pb-Free)

6

EL5325AIRZ-T7

(Note)

5325AIRZ

7”

28 Ld TSSOP MDP0044

(Pb-Free)

7

SHDN

VSD

8

EL5325AIRZ-T13 5325AIRZ

(Note)

13”

28 Ld TSSOP MDP0044

(Pb-Free)

9

REFH

REFL

VS

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

10

11

12

13

GND

OUTJ

OUTK

CAP

NC 14

15 OUTL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

EL5325A

Absolute Maximum Ratings (T = 25°C)

A

Supply Voltage between V & GND . . . . . .4.5V (min) to 18V (max)

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

S

Supply Voltage between V

& GND . 3V (min) to V and 7V (max)

SD

S

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: T = T = T

J

C

A

Electrical Specifications

V

= 15V, V

= 5V, V

= 13V, V

= 2V, R = 1.5kΩ and C = 200pF to 0V, T = 25°C, unless

S

SD

REFH

REFL

L

A

otherwise specified.

PARAMETER

SUPPLY

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

I

Supply Current

No load

10.2

0.17

12.5

0.35

mA

S

Digital Supply Current

SD

ANALOG

V

Output Swing Low

Sinking 5mA (V

REFH

= 15V, V

REFL

= 0)

50

14.95

140

65

150

mV

V

OL

Output Swing High

Sourcing 5mA (V

= 15V, V

14.85

100

45

OH

REFH

REFL

I

Short Circuit Current

R

= 10Ω

L

mA

SC

PSRR

Power Supply Rejection Ratio

Program to Out Delay

Accuracy referred to the ideal value

Channel to Channel Mismatch

Droop Voltage

V + is moved from 14V to 16V

S

dB

t

4

ms

D

V

Code = 512

20

mV

AC

ΔV

2

mV

MIS

V

1

2

mV/ms

kΩ

DROOP

R

Input Resistance @ V

Load Regulation

Band Gap

, V

32

INH

REFH REFL

REG

I

= 5mA step

0.5

1.3

1.5

1.6

mV/mA

V

OUT

CAP

By pass with 0.1µF

1

DIGITAL

V

Logic 1 Input Voltage

V

= 5V

4

2

V

IH

SD

= 3.3V

F

Clock Frequency

Logic 0 Input Voltage

Setup Time

5

1

MHz

V

CLK

V

= 3.3V/5V

IL

SD

t

20

10

1

ns

S

Hold Time

ns

H

Load to Clock Time

Clock to Load Line

ns

LC

CE

DCO

ns

Clock to Out Delay Time

Input Resistance

Negative edge of SCLK

ns

R

S

GΩ

µs

SDIN

DIN

T

Minimum Pulse Width for EXT_OSC Signal

Duty Cycle for EXT_OSC Signal

Integral Nonlinearity Error

5

PULSE

Duty Cycle

INL

50

1.3

0.5

21

%

LSB

kHz

V

DNL

Differential Nonlinearity Error

Internal Refresh Oscillator Frequency

SHDN Voltage Input High

F_OSC

OSC_Select = 0

SHDN = 2V

V

2

IH_SHDN

I

SHDN Current Input High

100

µA

IH_SHDN

2

EL5325A

Pin Descriptions

EL5325A

PIN NAME

PIN TYPE

Logic Input

PIN FUNCTION

1

2

ENA

SDI

Chip select, low enables data input to logic

Serial data input

Logic Input

3

SCLK

SDO

Logic Input

Serial data clock

4

Logic Output

Serial data output

5

EXT_OSC

VS+

Logic Input/Output

Analog Power

Logic Input

External oscillator input or internal oscillator output

Positive supply voltage for analog circuits

Chip shutdown: float enables chip, high > 2V disables chip

Positive power supply for digital circuits (3.3V - 5V)

High reference voltage

6, 11

7

SHDN

VSD

8

Digital Power

9

REFH

REFL

GND

Analog Reference Input

Ground

10

12

13

14

17

19

20

21

22

23

24

26

27

28

15

16

18, 25

Low reference voltage

Ground

CAP

Analog Bypass Pin

Decoupling capacitor for internal reference generator, 0.1µF

Not connected

NC

OUTJ

OUTI

OUTH

OUTG

OUTF

OUTE

OUTD

OUTC

OUTB

OUTA

OUTL

OUTK

GND

Analog Output

Power

Channel J programmable output voltage

Channel I programmable output voltage

Channel H programmable output voltage

Channel G programmable output voltage

Channel F programmable output voltage

Channel E programmable output voltage

Channel D programmable output voltage

Channel C programmable output voltage

Channel B programmable output voltage

Channel A programmable output voltage

Channel L programmable output voltage

Channel K programmable output voltage

Ground

3

EL5325A

Typical Performance Curves

V =15V, V =5V, V

SD

=13V, V

REFH

=2V

REFL

REFH=13V, REFL=2V

S

1.5

1

0.3

0.2

0.1

0

0.5

0

-0.1

-0.2

-0.3

-0.5

-1

0

200

400

600

800

1000 1200

10

210

410

610

810

1010

CODE

INPUT CODE

FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE

FIGURE 2. INTEGRAL NONLINEARITY ERROR

V =V

M=400ns/DIV

=15V

S

REFH

V =V

M=400ns/DIV

=15V

S

REFH

5mA

0mA

5mA

5mA/DIV

C =1nF

L

C =4.7nF

L

R =20Ω

S

R =20Ω

S

5V

200mV/DIV

C =1nF

L

C =4.7nF

L

R =20Ω

S

R =20Ω

S

C =180pF

L

C =180pF

L

FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)

FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)

M=400µs/DIV

SCLK

5V

0V

SDA

5V

0V

10V

5V

OUTPUT

0V

OUTPUT

FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V

TO 8V)

FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V

TO 0V)

4

EL5325A

Typical Performance Curves (Continued)

M=400µs/DIV

SCLK

SDA

5V

0V

SDA

5V

0V

OUTPUT

200mV

0V

FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V

TO 200mV)

FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM

200mV TO 0V)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.4

0.9

833mW

1.333W

1.2

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

0.8

0.6

0.4

0.2

0

25

50

75 85 100

125

0

25

50

75 85 100

125

AMBIENT TEMPERATURE (°C)

FIGURE 9. POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 10. POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE

THERMAL CONDUCTIVITY TEST BOARD -

HTSSOP EXPOSED DIEPAD SOLDERED

TO PCB PER JESD51-5

JEDEC JESD51-3 LOW EFFECTIVE

THERMAL CONDUCTIVITY TEST BOARD

3.5

1

0.9

3

3.333W

909mW

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2.5

2

1.5

1

0.5

0

25

50

75 85 100

125

150

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 12. POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 11. POWER DISSIPATION vs AMBIENT

TEMPERATURE

5

EL5325A

allocated to the following functions (also refer to the Control

Bits Logic Table)

General Description

The EL5325A provides a versatile method of providing the

reference voltages that are used in setting the transfer

characteristics of LCD display panels. The V/T

• Bit 15 is always set to a zero

• Bit 14 controls the source of the clock, see the next

section for details

(Voltage/Transmission) curve of the LCD panel requires that

a correction is applied to make it linear; however, if the panel

is to be used in more than one application, the final curve

may differ for different applications. By using the EL5325A,

the V/T curve can be changed to optimize its characteristics

according to the required application of the display product.

Each of the eight reference voltage outputs can be set with a

10-bit resolution. These outputs can be driven to within

50mV of the power rails of the EL5325A. As all of the output

buffers are identical, it is also possible to use the EL5325A

for applications other than LCDs where multiple voltage

references are required that can be set to 10 bit accuracy.

• Bits 13 through 10 select the channel to be written to,

these are binary coded with channel A = 0, and channel

H = 7

• The 10-bit data is on bits 9 through 0. Some examples of

data words are shown in the table of Serial Programming

Examples

TABLE 1. CONTROL BITS LOGIC TABLE

BIT

B15

B14

B13

B12

B11

B10

B9

NAME

Test

Oscillator

A3

DESCRIPTION

Always 0

0 = Internal, 1 = External

Digital Interface

Channel Address

The EL5325A uses a simple 3-wire SPI compliant digital

interface to program the outputs. The EL5325A can support

the clock rate up to 5MHz.

A2

Channel Address

A1

Channel Address

Serial Interface

A0

Channel Address

Data

The EL5325A is programmed through a three-wire serial

interface. The start and stop conditions are defined by the

ENA signal. While the ENA is low, the data on the SDI (serial

data input) pin is shifted into the 16-bit shift register on the

positive edge of the SCLK (serial clock) signal. The MSB (bit

15) is loaded first and the LSB (bit 0) is loaded last (see

Table 1). After the full 16-bit data has been loaded, the ENA

is pulled high and the addressed output channel is updated.

The SCLK is disabled internally when the ENA is high. The

SCLK must be low before the ENA is pulled low.

D9

B8

D8

Data

B7

D7

Data

B6

D6

Data

B5

D5

Data

B4

D4

Data

B3

D3

Data

To facilitate the system designs that use multiple EL5325A

chips, a buffered serial output of the shift register (SDO pin)

is available. Data appears on the SDO pin at the 16th falling

SCLK edge after being applied to the SDI pin.

B2

D2

Data

B1

D1

Data

B0

D0

Data

To control the multiple EL5325A chips from a single three-

wire serial port, just connect the ENA pins and the SCLK

pins together, connect the SDO pin to the SDI pin on the

next chip. While the ENA is held low, the 16m-bit data is

loaded to the SDI input of the first chip. The first 16-bit data

will go to the last chip and the last 16-bit data will go to the

first chip. While the ENA is held high, all addressed outputs

will be updated simultaneously.

The Serial Timing Diagram and parameters table show the

timing requirements for three-wire signals.

The serial data has a minimum length of 16 bits, the MSB

(most significant bit) is the first bit in the signal. The bits are

6

EL5325A

Serial Timing Diagram

ENA

t

T

t

SE

HE

SE

r

f

HE

SCLK

SDI

t

HD

t

SD

w

B15

B14

B13

B12-B2

B1

B0

t

MSB

Load MSB first, LSB last

LSB

TABLE 2. SERIAL TIMING PARAMETERS

RECOMMENDED OPERATING RANGE

PARAMETER

DESCRIPTION

T

≥200ns

0.05 * T

≥10ns

Clock Period

t /t

r f

Clock Rise/Fall Time

ENA Hold Time

t

HE

t

≥10ns

ENA Setup Time

Data Hold Time

SE

HD

t

≥10ns

t

≥10ns

Data Setup Time

Clock Pulse Width

SD

t

0.50 * T

W

TABLE 3. SERIAL PROGRAMMING EXAMPLES

DATA

CONTROL CHANNEL ADDRESS

CONDITION

C1

0

C0

0

A3 A2 A1

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Internal Oscillator, Channel A, Value = 0

Internal Oscillator, Channel A, Value = 1023

Internal Oscillator, Channel A, Value = 512

0

1

0

1‘t Internal Oscillator, Channel C, Value = 513

0

1

Internal Oscillator, Channel H, Value = 31

External Oscillator, Channel H, Value = 31

0

1

7

EL5325A

Block Diagram

REFERENCE HIGH

OUTA

OUTB

OUTJ

OUTK

OUTL

EIGHT

CHANNEL

MEMORY

VOLTAGE

SOURCES

REFERENCE LOW

REFERENCE DECOUPLE

CLK

SDI

SDO

CONTROL IF

LOAD

FILTER

EXT_OSC

CLOCK OSCILLATOR

Analog Section

The EL5325A requires an internal clock or external clock to

refresh its outputs. The outputs are refreshed at the falling

OSC clock edges. The output refreshed switches open at the

rising edges of the OSC clock. The driving load shouldn’t be

changed at the rising edges of the OSC clock. Otherwise, it

will generate a voltage error at the outputs. This clock may be

input or output via the clock pin labeled OSC. The internal

clock is provided by an internal oscillator running at

TRANSFER FUNCTION

The transfer function is:

data

------------

V

= V

+

× (V

- V

REFL

)

OUT(IDEAL)

REFL

REFH

1024

where data is the decimal value of the 10-bit data binary

input code.

approximately 21kHz and can be output to the OSC pin. In a 2

chip system, if the driving loads are stable, one chip may be

programmed to use the internal oscillator; then the OSC pin

will output the clock from the internal oscillator. The second

chip may have the OSC pin connected to this clock source.

The output voltages from the EL5325A will be derived from

the reference voltages present at the V

and V

REFL

REFH

pins. The impedance between those two pins is about 32kΩ.

Care should be taken that the system design holds these two

reference voltages within the limits of the power rails of the

For transient load application, the external clock Mode

should be used to ensure all functions are synchronized

together. The positive edge of the external clock to the OSC

pin should be timed to avoid the transient load effect. The

Application Drawing shows the LCD H rate signal used, here

the positive clock edge is timed to avoid the transient load of

the column driver circuits.

EL5325A. GND < V

REFH

≤ V and GND ≤ V

REFL

≤ V .

REFH

S

In some LCD applications that require more than 12

channels, the system can be designed such that one

EL5325A will provide the Gamma correction voltages that

are more positive than the V potential. The second

COM

EL5325A can provide the Gamma correction voltage more

negative than the V potential. The Application Drawing

COM

After power on, the chip will start with the internal oscillator

mode. At this time, the OSC pin will be in a high impedance

condition to prevent contention. By setting B14 to high, the

shows a system connected in this way.

8

EL5325A

chip is on external clock mode. Setting B14 to low, the chip is

on internal clock mode.

when sinking.

Where:

CHANNEL OUTPUTS

• i = 1 to total 12

Each of the channel outputs has a rail-to-rail buffer. This

enables all channels to have the capability to drive to within

50mV of the power rails, (see Electrical Characteristics for

details).

• V = Supply voltage

S

• I = Quiescent current

S

• V

i = Output voltage of the i channel

OUT

When driving large capacitive loads, a series resistor should

be placed in series with the output. (Usually between 5Ω and

50Ω).

• I

i = Load current of the i channel

LOAD

By setting the two P

can solve for the R

package power dissipation curves provide a convenient way

to see if the device will overheat.

equations equal to each other, we

DMAX

s to avoid the device overheat. The

LOAD

Each of the channels is updated on a continuous cycle, the

time for the new data to appear at a specific output will

depend on the exact timing relationship of the incoming data

to this cycle.

The EL5325A has an internal thermal shutdown circuitry that

prevents overheating of the part. When the junction

temperature goes up to about 150°C, the part will be

disabled. When the junction temperature drops down to

about 120°C, the part will be enabled. With this feature, any

short circuit at the outputs will enable the thermal shutdown

circuitry to disable the part.

The best-case scenario is when the data has just been

captured and then passed on to the output stage immediately;

this can be as short as 48µs. In the worst-case scenario this

will be 576µs when the data has just missed the cycle.

When a large change in output voltage is required, the change

will occur in 2V steps, thus the requisite number of timing cycles

will be added to the overall update time. This means that a

large change of 16V can take between 4.6ms to 5.2ms

depending on the absolute timing relative to the update cycle.

POWER SUPPLY BYPASSING AND PRINTED CIRCUIT

BOARD LAYOUT

Good printed circuit board layout is necessary for optimum

performance. A low impedance and clean analog ground plane

should be used for the EL5325A. The traces from the two

ground pins to the ground plane must be very short. The

thermal pad of the EL5325A should be connected to the analog

ground plane. Lead length should be as short as possible and

all power supply pins must be well bypassed. A 0.1µF ceramic

capacitor must be place very close to the V , V ,

and CAP pins. A 4.7µF local bypass tantalum capacitor should

be placed to the V , V , and V pins.

POWER DISSIPATION AND THERMAL SHUTDOWN

With the 30mA maximum continues output drive capability

for each channel, it is possible to exceed the 125°C absolute

maximum junction temperature. Therefore, it is important to

calculate the maximum junction temperature for the

application to determine if load conditions need to be

modified for the part to remain in the safe operation.

, V

S

REFH REFL

S

REFH REFL

The maximum power dissipation allowed in a package is

determined according to:

APPLICATION USING THE EL5325A

In the first application drawing, the schematic shows the

interconnect of a pair of EL5325A chips connected to give

T

- T

AMAX

JMAX

P

= --------------------------------------------

DMAX

Θ

JA

12 gamma corrected voltages above the V

12 gamma corrected voltages below the V

voltage, and

voltage.

COM

where:

External Shutdown

• T

= Maximum junction temperature

= Maximum ambient temperature

JMAX

The EL5325A also has an external shutdown to enable and

disable the part. The SHDN pin should never be driven low.

Rather, to enable the part, the SHDN pin must be left open

(float). To disable, the SHDN pin must be driven HI (>2V).

WIth this feature, the EL5325A can be forced to shut down,

regardless of any other conditions. A simple open collector

driver is adequate to control the enable and disable function:

AMAX

• θ = Thermal resistance of the package

JA

• P

DMAX

= Maximum power dissipation in the package

The maximum power dissipation actually produced by the IC

is the total quiescent supply current times the total power

supply voltage and plus the power in the IC due to the loads.

V

SD

P

= V × I + Σ[(V - V

i) × I i]

LOAD

R

1

100K

DMAX

S

OUT

Q

PNP

1

EL5325A

SHDN

when sourcing, and:

R

100K

2

P

= V × I + Σ(V

i × I

i)

LOAD

SHDN

DMAX

S

OUT

9

EL5325A

Application Drawing

HIGH REFERENCE

VOLTAGE

COLUMN

(SOURCE)

DRIVER

+10V

REFH

OUTA

OUTB

OUTC

OUTD

OUTE

OUTF

0.1µF

+12V

VS

0.1µF

LCD PANEL

+5V

0.1µF

VSD

MICROCONTROLLER

SDI

SCK

ENA

SDO

LCD

TIMING

CONTROLLER

HORIZONTAL RATE

OSC

CAP

0.1µF

OUTK

OUTL

REFL

GND

EL5325A

MIDDLE REFERENCE

+5.5V

REFH

OSC

OUTA

OUTB

OUTC

OUTD

OUTE

OUTF

+12V

+5V

VS

0.1µF

VSD

0.1µF

SDI

SCK

ENA

CAP

0.1µF

LOW REFERENCE

VOLTAGE

+1V

REFL

0.1µF

OUTK

OUTL

GND

EL5325A

10

EL5325A

Package Outline Drawing (HTSSOP)

11

EL5325A

TSSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil

website at <http://www.intersil.com/design/packages/index.asp>

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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型号:	EL5325AIREZ
Brand Name：	Intersil
生命周期：	Obsolete
IHS 制造商：	INTERSIL CORP
零件包装代码：	TSSOP
包装说明：	HTSSOP, TSSOP28,.25
针数：	28
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.82
Is Samacsys：	N
模拟集成电路 - 其他类型：	THREE TERMINAL VOLTAGE REFERENCE
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3
长度：	9.7 mm
湿度敏感等级：	3
功能数量：	1
输出次数：	12
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电压：	13 V
最小输出电压：	2 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装等效代码：	TSSOP28,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5,15 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Other Analog ICs
最大供电电压 (Vsup)：	16.5 V
最小供电电压 (Vsup)：	5 V
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
微调/可调输出：	YES
宽度：	4.4 mm
Base Number Matches：	1

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