EL7562CUZ应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

EL7562

®

Data Sheet

May 1, 2006

FN7295.1

Monolithic 2Amp DC-DC Step-Down

Regulator

Features

• Integrated synchronous MOSFETs and current mode

controller

The EL7562 is an integrated, synchronous step-down

regulator with output voltage adjustable from 1.0V to 3.8V. It

is capable of delivering 2A continuous current at up to 95%

efficiency. The EL7562 operates at a constant frequency

pulse width modulation (PWM) mode, making external

synchronization possible. Patented on-chip resistorless

current sensing enables current mode control, which

provides cycle-by-cycle current limiting, over-current

protection, and excellent step load response. The EL7562 is

available in a fused-lead 16 Ld QSOP package. With proper

external components, the whole converter fits into a less

• 2A continuous output current

• Up to 95% efficiency

• 3.3V or 5V nominal input voltage

• Adjustable output from 1V to 3.8V

• Cycle-by-cycle current limit

• Precision reference

• ±0.5% load and line regulation

• Adjustable switching frequency to 1MHz

• Oscillator synchronization possible

• Internal soft-start

2

than 0.5 in area. The minimal external components and

small size make this EL7562 ideal for desktop and portable

applications.

The EL7562 is specified for operation over the 0°C to +70°C

temperature range.

• Over-temperature protection

• Under-voltage lockout

• 16 Ld QSOP package

Pinout

• Pb-free plus anneal available (RoHS compliant)

EL7562

(16 LD QSOP)

TOP VIEW

Applications

• DSP, CPU core and IO supplies

• Logic/Bus supplies

1

2

3

4

5

6

7

8

SGND PGND 16

• Portable equipment

C

4

3

C

5

0.1µF 270pF

• DC-DC converter modules

• GTL + Bus power supply

COSC

VDD

VREF 15

FB 14

R

0.1µF

R

2

3

39Ω

R

1

1kΩ

2.37kΩ

PGND VDRV 13

Ordering Information

PGND

VIN

LX 12

LX 11

VHI 10

V

O

PART

TAPE &

PKG.

DWG. #

C

2

1

(3.3V,

2A)

PART NUMBER MARKING REEL

PACKAGE

C

7

6

100µF 0.1µF

0.1µF

100µF

EL7562CU

7562CU

-

7”

13”

-

16 Ld QSOP MDP0040

VIN

V

EL7562CU-T7

IN

(4.5V- 5.5V)

EN

PGND 9

EL7562CU-T13 7562CU

EL7562CUZ

(Note)

7562CUZ

16 Ld QSOP MDP0040

(Pb-free)

EL7562CUZ-T7 7562CUZ

(Note)

7”

16 Ld QSOP MDP0040

(Pb-free)

Please refer to page 4 for 3.3V input Application Diagram

Manufactured under U.S. Patent No. 57,323,974

EL7562CUZ-T13 7562CUZ

(Note)

13”

16 Ld QSOP MDP0040

(Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings (T = 25°C)

A

Supply Voltage between V or V

IN

and GND . . . . . . . . . . . . +6.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Ambient Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C

DD

V

Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V +0.3V

LX

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, V

IN

+0.3V

DD

V

Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, V +6V

HI

LX

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

DC Electrical Specifications

V

= V = 5V, T = T = 25°C, C

= 270pF, unless otherwise specified.

DD

DESCRIPTION

Reference Accuracy

IN

A

J

OSC

PARAMETER

CONDITIONS

MIN

TYP

1.26

50

MAX

UNIT

V

1.24

1.28

REF

V

Reference Temperature Coefficient

Reference Load Regulation

Oscillator Ramp Amplitude

Oscillator Charge Current

ppm/°C

%

REFTC

0 < I

< 50µA

REF

-1

REFLOAD

RAMP

1.15

200

8

V

I

0.1V < V

< 1.25V

µA

mA

V

OSC_CHG

OSC_DIS

OSC

Oscillator Discharge Current

+V

V

+V

Supply Current

Standby Current

V

= 4V, F = 120kHz

OSC

2

6.5

1.5

2.7

3

VDD DRV

DD DRV

EN

EN = 0

1

VDD_OFF

DD

V

for Shutdown

for Startup

2.5

2.6

DD_OFF

DD_ON

OT

V

T

Over-temperature Threshold

Over-temperature Hysteresis

Internal FET Leakage Current

135

20

°C

HYS

I

EN = 0, L = 5V (low FET), L = 0V (high

20

µA

LEAK

X

FET)

I

Peak Current Limit

FET On Resistance

3

A

mΩ

mΩ/°C

V

LMAX

R

Wafer level test only

60

0.2

120

DSON

R

Tempco

DSONTC

FB

DSON

V

Output Initial Accuracy

Output Line Regulation

Output Load Regulation

Output Temperature Stability

Feedback Input Pull Up Current

EN Input High Level

I

= 0A

0.970

0.985

0.5

1.000

LOAD

V

= 5V, ΔV = 10%, I

= 0A

%

FB_LINE

FB_LOAD

FB_TC

IN

LOAD

0.1A < I

< 1A

0.5

%

LOAD

-40°C < T < 85°C, I

= 0.5A

LOAD

±1

%

A

I

V

= 0V

100

200

1

nA

V

FB

V

(Note)

4

EN_HI

EN Input Low Level

V

EN_LO

I

Enable Pull Up Current

V

= 0

-4

-2.5

µA

EN

NOTE: V

is typically 2/3 of V . For V

DD

= 3.3V, V

EN_HI

is 2.2V typical.

EN_HI

DD

2

Closed-Loop AC Electrical Specifications

V

= V = 5V, T = T = 25°C, C

IN

= 270pF, unless otherwise specified.

OSC

S

A

J

PARAMETER

DESCRIPTION

Oscillator Initial Accuracy

Minimum Oscillator Sync Width

Soft-start Slope

CONDITIONS

MIN

TYP

580

25

MAX

UNIT

kHz

ns

F

493

667

OSC

t

SYNC

M

0.5

15

V/ms

ns

SS

BRM

LEB

t

FET Break Before Make Delay

High Side FET Minimum On Time

Maximum Duty Cycle

150

95

ns

D

%

MAX

Pin Descriptions

NUMBER

PIN NAME

SGND

COSC

VDD

PGND

VIN

PIN FUNCTION

1

2

Control circuit negative supply

Oscillator timing capacitor; F

can be approximated by: F

(kHz) = 0.1843/C

OSC

, C in µF

OSC OSC

OSC

Control circuit positive supply

3

4

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Power supply input of the regulator; connected to the drain of the high-side NMOS power FET

Chip enable, active high; a 2µA internal pull-up current enables the device if the pin is left open

Ground return of the regulator

5

6

7

VIN

8

EN

9

PGND

VHI

10

11

12

13

14

Positive supply of the high-side driver

LX

Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage

Positive supply of the low-side driver and input voltage for the high-side boot strap

LX

VDRV

FB

Voltage feedback input; connected to an external resistor divider between V

and GND; a 125nA pull-up current

OUT

forces V

to V in the event that FB is floating

S

OUT

15

16

VREF

PGND

Bandgap reference bypass capacitor; typically 0.1µF to GND

Ground return of the regulator

3

Application Diagram for 3.3V Input

1

2

3

4

5

6

7

8

SGND

COSC

VDD

PGND

VIN

PGND 16

VREF 15

FB 14

C

4

3

C

5

0.1µF

270pF

0.1µF

R

3

D

2

39Ω

D

4

3

VDRV 13

LX 12

C

9

8

0.1µF

C

V

O

1

2

L

1

(2.5V, 2A)

100µF

0.1µF

LX 11

C

R

2

6

7

4.7µF

1.54kΩ

0.1µF

100µF

VIN

VHI 10

R

1

V

IN

(3V-3.6V)

1kΩ

EN

PGND 9

EL7562

(16 Ld QSOP)

4

Typical Performance Curves

Efficiency vs I

Power Loss vs I

O

IN

O

V

=5V

V

=5V

IN

100

95

90

85

80

75

70

65

60

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V

=2.5

V =3.3

O

V

=3.3

O

V

=1.8

O

V

=1.5

O

V

=2.5

=1.5

O

V

=1.2

O

V

=1.8

O

=1.2

1.5

O

F =500kH

S

L=Coilcraft DO3316P-

0.1

1

LOAD CURRENT I (A)

2

0

0.5

1

2

LOLAoaDdCCUuRrrReEnNt TI I(A()A)

O O

O

Efficiency vs I

Load Regulation

O

V

=3.3V

V

=3.3V

O

100

95

90

85

80

75

70

65

60

0.8

0.6

0.4

0.2

0

V

=4.5

IN

V

=5V

V =5.5

IN

V

=5.5

IN

V

=5V

IN

V

=4.5

IN

-0.2

-0.4

-0.6

0

0.5

1

1.5

2

0

0.5

1

1.5

2

LOAD CURRENT I (A)

O

Line Regulation

=3.3V

V

vs Temperature

REF

V

O

0.6

0.4

0.2

0

1.258

1.256

1.254

1.252

1.25

I

=0.1A

O

I

=1A

O

1.248

1.246

1.244

1.242

-0.2

-0.4

-0.6

I =2A

O

4.5

4.7

4.9

5.1

5.3

5.5

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

V

(V)

IN

5

Typical Performance Curves (Continued)

Oscillator Frequency vs Temperature

390

Input Current vs Temperature

(Enable connected to GND)

0.96

0.94

0.92

0.9

C

=390p

OSC

V

=5.5

IN

385

380

375

370

365

360

V

=5V

IN

V

=4.5

IN

0.88

0.86

0.84

0.82

0.8

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

Switching Frequency vs C

OSC

1400

1200

1000

800

600

400

200

0

200

400

C

600

(pF)

800

1000

OSC

6

Block Diagram

0.1µF

270pF

VREF

Voltage

COSC

Junction

Temperature

VDRV

Oscillator

Reference

Controller

Supply

VHI

VIN

39Ω

VDD

Power

0.1µF

4.7µH

5V

0.1µF

FET

PWM

Controlle

Drivers

V

OUT

Power

FET

2370Ω

1kΩ

100µF

PGND

EN

Current

Sense

SGND

FB

averages the logic level modulator output. In a step-down

(buck) converter, the feedback loop forces the time-

averaged output of the modulator to equal the desired output

voltage. Unlike pure voltage-mode control systems, current-

mode control utilizes dual feedback loops to provide both

output voltage and inductor current information to the

controller. The voltage loop minimizes DC and transient

errors in the output voltage by adjusting the PWM duty-cycle

in response to changes in line or load conditions. Since the

output voltage is equal to the time-averaged of the modulator

output, the relatively large LC time constant found in power

supply applications generally results in low bandwidth and

poor transient response. By directly monitoring changes in

inductor current via a series sense resistor the controller's

response time is not entirely limited by the output LC filter

and can react more quickly to changes in line and load

conditions. This feed-forward characteristic also simplifies

AC loop compensation since it adds a zero to the overall

loop response. Through proper selection of the current-

feedback to voltage-feedback ratio the overall loop response

will approach a one-pole system. The resulting system offers

several advantages over traditional voltage control systems,

including simpler loop compensation, pulse by pulse current

limiting, rapid response to line variation and good load step

response.

Applications Information

Circuit Description

General

The EL7562 is a fixed frequency, current mode controlled

DC-DC converter with integrated N-channel power

MOSFETs and a high precision reference. The device

incorporates all the active circuitry required to implement a

cost effective, user-programmable 2A synchronous step-

down regulator suitable for use in DSP core power supplies.

Theory of Operation

The EL7562 is composed of 5 major blocks:

1. PWM Controller

2. NMOS Power FETs and Drive Circuitry

3. Bandgap Reference

4. Oscillator

5. Thermal Shut-down

PWM Controller

The EL7562 regulates output voltage through the use of

current-mode controlled pulse width modulation. The three

main elements in a PWM controller are the feedback loop

and reference, a pulse width modulator whose duty cycle is

controlled by the feedback error signal, and a filter which

7

The heart of the controller is an input direct summing

comparator which sum voltage feedback, current feedback,

slope compensation ramp and power tracking signals

together. Slope compensation is required to prevent system

instability that occurs in current-mode topologies operating

at duty-cycles greater than 50% and is also used to define

the open-loop gain of the overall system. The slope

compensation is fixed internally and optimized for 500mA

inductor ripple current. The power tracking will not contribute

any input to the comparator steady-state operation. Current

feedback is measured by the patented sensing scheme that

senses the inductor current flowing through the high-side

switch whenever it is conducting. At the beginning of each

oscillator period the high-side NMOS switch is turned on.

The comparator inputs are gated off for a minimum period of

time of about 150ns (LEB) after the high-side switch is

turned on to allow the system to settle. The Leading Edge

Blanking (LEB) period prevents the detection of erroneous

voltages at the comparator inputs due to switching noise. If

the inductor current exceeds the maximum current limit

NMOS Power FETs and Drive Circuitry

The EL7562 integrates low on-resistance (60mΩ) NMOS

FETs to achieve high efficiency at 2A. In order to use an

NMOS switch for the high-side drive it is necessary to drive

the gate voltage above the source voltage (LX). This is

accomplished by bootstrapping the V pin above the LX

HI

voltage with an external capacitor C

and internal switch

VHI

and diode. When the low-side switch is turned on and the LX

voltage is close to GND potential, capacitor C is charged

VHI

through internal switch to V

, typically 5V. At the

DRV

beginning of the next cycle the high-side switch turns on and

the LX pins begin to rise from GND to V potential. As the

IN

LX pin rises the positive plate of capacitor C

follows and

VHI

eventually reaches a value of V

+V , typically 10V, for

DRV IN

V

=V =5V. This voltage is then level shifted and used to

DRV IN

drive the gate of the high-side FET, via the V pin. A value

HI

of 0.1µF for C

is recommended.

VHI

Reference

A 1.5% temperature compensated bandgap reference is

integrated in the EL7562. The external V capacitor acts

(I

) a secondary over-current comparator will terminate

the high-side switch on time. If I has not been reached,

LMAX

REF

as the dominant pole of the amplifier and can be increased

in size to maximize transient noise rejection. A value of

0.1µF is recommended.

LMAX

the feedback voltage FB derived from the regulator output

voltage V is then compared to the internal feedback

OUT

reference voltage. The resultant error voltage is summed

with the current feedback and slope compensation ramp.

The high-side switch remains on until all four comparator

inputs have summed to zero, at which time the high-side

switch is turned off and the low-side switch is turned on.

However, the maximum on-duty ratio of the high-side switch

is limited to 95%. In order to eliminate cross-conduction of

the high-side and low-side switches a 15ns break-before-

make delay is incorporated in the switch drive circuitry. The

output enable (EN) input allows the regulator output to be

disabled by an external logic control signal.

Oscillator

The system clock is generated by an internal relaxation

oscillator with a maximum duty-cycle of approximately 95%.

Operating frequency can be adjusted through the C

OSC

or can be driven by an external source. If the oscillator is

driven by an external source care must be taken in selecting

the ramp amplitude. Since C value is derived from the

SLOPE

ramp will change the

C

ramp, changes to C

OSC

compensation ramp which determine the open-loop

SLOPE

gain of the system.

When external synchronization is required, always choose

Output Voltage Setting

C

such that the free-running frequency is at least 20%

OSC

In general:

lower than that of sync source to accommodate component

and temperature variations. Figure 1 shows a typical

connection.

R

⎛

⎞

⎟

⎠

2

V

= 0.985 × 1 + ------

⎜

OUT

R

⎝

1

For V = 5V

IN

1

2

3

6

7

8

16

15

14

11

10

9

100p

BAT54

External

Oscillato

R

⎛

⎞

⎟

⎠

2

= 0.975 × 1 + ------

⎜

R

⎝

1

FOR V = 3.3V

IN

However, due to the relatively low open loop gain of the

system, gain errors will occur as the output voltage and loop-

gain is changed. This is shown in the performance curves. A

100nA pull-up current from FB to V

in the event that FB is floating.

forces V to GND

OUT

DD

EL7562

FIGURE 1. OSCILLATOR SYNCHRONIZATION

8

The demo board is a good example of layout based on these

principles. Please refer to the EL7562 Application Brief for

the layout.

Thermal Shut-down

An internal temperature sensor continuously monitors die

temperature. In the event that die temperature exceeds the

thermal trip-point, the system is in fault state and will be shut

down. The upper and low trip-points are set to 135°C and

115°C respectively.

Start-up Delay

A capacitor can be added to the EN pin to delay the

converter start-up (Figure 2) by utilizing the pull-up current.

The delay time is approximately:

t (ms) = 1200 × C(μF)

d

1

2

3

6

7

8

1

9

V

OU

V

IN

O

t

d

C

EL7562

TIME

FIGURE 2. START-UP DELAY

Layout Considerations

The layout is very important for the converter to function

properly. Power Ground ( ) and Signal Ground (- --)

should be separated to ensure that the high pulse current in

the Power Ground never interferes with the sensitive signals

connected to Signal Ground. They should only be connected

at one point (normally at the negative side of either the input

or output capacitor).

The trace connected to pin 14 (FB) is the most sensitive

trace. It needs to be as short as possible and in a “quiet”

place, preferably between PGND or SGND traces.

In addition, the bypass capacitor connected to the V

needs to be as close to the pin as possible.

DD

The heat of the chip is mainly dissipated through the PGND

pins. Maximizing the copper area around these pins is

preferable. In addition, a solid ground plane is always helpful

for the EMI performance.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

9

型号:	EL7562CUZ
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	ROHS COMPLIANT, QSOP-16
针数：	16
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.72
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.5 V
最小输入电压：	4.5 V
标称输入电压：	5 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3
长度：	4.9022 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	16
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	3 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.7272 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	1000 kHz
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.9116 mm
Base Number Matches：	1

电子百科

产品导航

产品型号EL7562CUZ的概述

产品型号EL7562CUZ的Datasheet PDF文件预览

EL7562CUZ相关产品

EL7562CUZ相关文章

IC37:专业IC行业平台