EN5311QI各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号EN5311QI的概述

芯片EN5311QI的概述 EN5311QI是一款高效的DC-DC降压转换器，主要用于将高输入电压转换为较低且稳定的输出电压。它被广泛应用于移动设备、工业控制、消费电子以及电源管理系统中。此芯片的设计目的是满足现代电子设备对高能效和小型化的需求，因此在高频操作、低静态电流和过流保护等方面表现出色。 EN5311QI是一个集成了开关电源管理功能的芯片，具有较高的输出电流能力，并支持多种输出电压配置。它的输入电压范围广泛，通常在4.5V至17V之间，这使其能够兼容多种电源供电场景。此外，EN5311QI配备了内置的MOSFET，减少了外部元器件的数量，从而实现了设计的紧凑性和成本的节约。芯片EN5311QI的详细参数以下是EN5311QI的一些详细参数： - 输入电压范围：4.5V至17V - 输出电压：可调节，范围从1.2V到10V - 输出电流：最大为3A - 开关频率：可达1MH...

产品型号EN5311QI的Datasheet PDF文件预览

EN5311QI

1A Synchronous Buck Regulator

With Integrated Inductor

RoHS Compliant

Halogen Free

Product Overview

Featuring Integrated Inductor Technology

The Ultra-Low-Profile EN5311QI is targeted to

applications where board area and profile are

critical. EN5311QI is a complete power

conversion solution requiring only two low cost

ceramic MLCC caps. Inductor, MOSFETS,

PWM, and compensation are integrated into a

tiny 5mm x 4mm x 1.1mm QFN package. The

EN5311QI is engineered to simplify design and

V_IN

UVLO

Thermal Limit

Current Limit

ENABLE

Soft Start

P-Drive

N-Drive

Logic

V_OUT

(-)

PWM

Comp

(+)

GND

to minimize layout constraints.

4 MHz

V_SENSE

Sawtooth

Generator

switching frequency and internal type III

compensation provides superior transient

Compensation

Network

response.

With a 1.1 mm profile, the

(-)

Switch

Error

Amp

V_FB

EN5311QI is ideal for space and height

constrained applications.

(+)

DAC

Voltage

Select

VREF

A 3-pin VID output voltage selector provides

seven pre-programmed output voltages along

with an option for external resistor divider.

Output voltage can be programmed on-the-fly

to provide fast, dynamic voltage scaling.

Package Boundry

VS0 VS1 VS2

Product Highlights

• Revolutionary Integrated Inductor

• 5mm x 4mm x1.1mm QFN package

• Very small total solution foot print*

• 4 MHz switching frequency

Typical Application Circuit

ENABLE

V_Sense

V_OUT

V_IN

V_in

V_out

V_FB

4.7μF

10μF

• Only two low cost MLCC caps required

• Designed for low noise/low EMI

• Very low ripple voltage; 5mV_p-pTypical

• High efficiency, up to 95%

V_S0

Voltage

Select

V_S1

V_S2

GND

• Wide 2.4V to 6.6V input range

• 1000mA continuous output current

• Less than 1 μA standby current.

• Excellent transient performance

• 3 Pin VID Output Voltage select

• External divider: 0.6V to V_IN-V_dropout

• 100% duty cycle capable

• Short circuit and over current protection

• UVLO and thermal protection

• RoHS compliant; MSL 3 260°C reflow

Figure 1. Typical application circuit.

Applications

• Area constrained applications

• Noise Sensitive Applications such as A/V

and RF

• LDO replacement for improved thermals

• Set top box/home gateway

• Smart phones, PDAs

• VoIP and Video phones

• Personal Media Players

*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.

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EN5311QI

Pin Description

ground. One or more of these pins may be

connected internally.

VSENSE (Pin 15):

Sense pin for output

voltage regulation. Connect V_SENSEto the

output voltage rail as close to the terminal of

the output filter capacitor as possible.

VFB (Pin 16): Feed back pin for external

divider option. When using the external divider

option (VS0=VS1=VS2= high) connect this pin

to the center of the external divider. Set the

divider such that V_FB= 0.603V.

VS0,VS1,VS2 (Pin 17,18,19): Output voltage

select. VS0=pin19, VS1=pin18, VS2=pin17.

Selects one of seven preset output voltages or

choose external divider by connecting pins to

logic high or low. Logic low is defined as V_LOW

≤ 0.4V. Logic high is defined as V_HIGH≥ 1.4V.

Any level between these two values is

indeterminate.

Figure 2. Pin description, top view.

VIN (Pin 1,2): Input voltage pin. Supplies

power to the IC.

Input GND: (Pin 3): Input power ground.

Connect this pin to the ground terminal of the

input

capacitor.

Refer

Layout

ENABLE (Pin 20): Output enable. Enable =

logic high, disable = logic low. Logic low is

defined as V_LOW≤ 0.2V. Logic high is defined

as V_HIGH≥ 1.4V. Any level between these two

values is indeterminate.

Recommendations for further details.

Output GND: (Pin 4): Power ground. The

output filter capacitor should be connected

between this pin and V_OUT. Refer to Layout

recommendations for further detail.

Bottom Thermal Pad: Device thermal pad to

remove heat from package. Connect to PCB

surface ground pad and PCB internal ground

plane (see layout recommendations).

VOUT (Pin 5,6,7): Regulated output voltage.

NC (Pin 8,9,10,11,12,13,14): These pins

should not be electrically connected to each

other or to any external signal, voltage, or

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EN5311QI

Functional Block Diagram

V_IN

UVLO

Thermal Limit

Current Limit

ENABLE

Soft Start

P-Drive

N-Drive

Logic

V_OUT

(-)

PWM

Comp

(+)

GND

V_SENSE

Sawtooth

Generator

Compensation

Network

(-)

Switch

Error

Amp

V_FB

(+)

DAC

Voltage

Select

VREF

Package Boundry

VS0 VS1

VS2

Figure 3. Functional block diagram.

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EN5311QI

Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond

recommended operating conditions is not implied. Stress beyond absolute maximum ratings may

cause permanent damage to the device. Exposure to absolute maximum rated conditions for

extended periods may affect device reliability.

PARAMETER

SYMBOL

MIN

-0.3

-65

MAX

7.0

V_IN+ 0.3

2.7

150

260

2000

UNITS

Input Supply Voltage

V_IN

°C

Voltages on: ENABLE, V_SENSE, V_S0-V_S2

Voltage on: V_FB

Storage Temperature Range

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A

ESD Rating (based on Human Body Model)

T_STG

Recommended Operating Conditions

PARAMETER

Input Voltage Range (VID)

SYMBOL

MIN

MAX

5.5

6.6

V_IN-0.6

1000

+85

UNITS

V_IN

V_OUT

I_OUT

T_A

2.4

0.6

-40

°C

Input Voltage Range (External Divider (VFB))¹

Output Voltage Range

Output Current

Operating Ambient Temperature

Operating Junction Temperature

T_J

+125

1. See Section “Application Information” for specific circuit requirements

Thermal Characteristics

PARAMETER

Thermal Resistance: Junction to Ambient (0 LFM)

Thermal Resistance: Junction to Case (0 LFM)

Thermal Shutdown

SYMBOL

θ_JA

TYP

+150

UNITS

°C/W

°C

θ_JC

T_J-TP

Thermal Shutdown Hysteresis

°C

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EN5311QI

Electrical Characteristics

NOTE: T_A= 25°C unless otherwise noted. Typical values are at V_IN= 3.6V, C_IN= 4.7μF, C_OUT=10uF.

NOTE: V_INmust be greater than V_OUT+ 0.6V.

SYMBOL

PARAMETER

Operating Input Voltage

TEST CONDITIONS

MIN

2.4

TYP

MAX

5.5

6.6

UNITS

V_IN

Using VID

Using External Divider (VFB)¹

V_INgoing low to high

Under Voltage Lockout

UVLO Hysteresis

V_UVLO

2.2

0.145

2.3

V_OUTInitial Accuracy (VID)

2.4V ≤ V_IN≤ 5.5V, I_LOAD= 100mA;

T_A= 25C

2.4V ≤ V_IN≤ 5.5V, I_LOAD= 0 - 1A,

T_A= -40°C to +85°C

2.4V ≤ V_IN≤ 6.6V, I_LOAD= 100mA

TA = 25C; VSO=VS1=VS2=1

2.4V ≤ V_IN≤ 6.6V, I_LOAD= 0 - 1A,

T_A= -40°C to +85°C;

V_OUT

V_FB

-2.0

-3.0

+2.0

+3.0

V_OUTVariation for all

Causes (VID)

Feedback Pin Voltage

0.591

0.603

0.615

Feedback Pin Voltage

V_FB

0.585

0.621

2.1

VSO=VS1=VS2=1

Feedback Pin Input Current

Dynamic Voltage Slew

Rate^†

I_FB

V_slew

1.24

1.65

V/mS

Output Current

Shut-Down Current

Quiescent Current

I_OUT

I_SD

1000

μA

Enable = Low

No switching

0.75

800

2.4V ≤ V_IN≤ 6.6V,

0.6V ≤ V_OUT≤ V_IN– 0.6V

Pin = Low

PFET OCP Threshold

I_LIM

1.4

0.0

1.4

0.4

V_IN

VS0-VS1 Thresholds

V_TH

I_VSX

Pin = High

VS0-VS2 Pin Input Current

Enable Voltage Threshold

Logic Low

Logic High

V_IN= 3.6V

0.0

1.4

0.2

V_IN

Enable Pin Input Current

Operating Frequency

PFET On Resistance

NFET On Resistance

Typical inductor DCR

Soft-Start Operation

V_OUTSoft Start Slew Rate^†

Soft Start Rise Time

I_EN

F_OSC

R_DS(ON)

340

270

.110

μA

MHz

mΩ

VID Mode ²

VFB mode ²

1.24

0.80

1.65

1.10

2.1

1.40

V/mS

ΔV_SS

ΔT_SS

1. See Section “Application Information” for specific circuit requirements

2. Measured from when V_IN≥ V_UVLO& ENABLE pin crosses its logic High threshold

† Parameter guaranteed by design.

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EN5311QI

Typical Performance Characteristics

Efficiency Vs. Load Current (Vin = 3.3V)

Efficiency Vs. Load Current (Vin = 5.0V)

100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Load Current (A)

Top to Bottom: V_OUT= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V

Load Current (A)

Top to Bottom: V_OUT= 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V

Start up Waveform

V_out

1V/Div

Enable

1V/Div

V_IN= 5.0V

V_OUT= 3.3V

400μs/Div

Transient Response

V_out

50mV/Div

V_out

50mV/Div

I_Load

500mA/Div

I_Load

500mA/Div

V_IN= 3.3V

20μs/Div

V_IN= 5.0V

_OUT= 3.3V

I_load= 100mA to 800mA

20μs/Div

V_OUT= 1.8V

_load= 100mA to 800mA

Output Ripple: V_IN= 5.0 V

Output Ripple: V_IN= 3.3 V

V_OUT= 1.2V, I_LOAD= 1A, C_OUT= 1 x 10µF 0805

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03799

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EN5311QI

Detailed Description

Functional Overview

Protection features include under-voltage lock-

out (UVLO), over-current protection (OCP),

short circuit protection, and thermal overload

protection.

The EN5311QI is a complete DCDC converter

solution requiring only two low cost MLCC

capacitors.

MOSFET switches, PWM

controller, Gate-drive, compensation, and

inductor are integrated into the tiny 5mm x

4mm x 1.1mm package to provide the smallest

footprint possible while maintaining high

efficiency, low ripple, and high performance.

The converter uses voltage mode control to

provide the simplest implementation and high

noise immunity. The device operates at a high

switching frequency. The high switching

frequency allows for a wide control loop

Integrated Inductor

Enpirion has introduced the world’s first

product family featuring integrated inductors.

The use of an internal inductor localizes the

noises associated with the output loop

currents. The inherent shielding and compact

construction of the integrated inductor reduces

the radiated noise that couples into the traces

of the circuit board. Further, the package

layout is optimized to reduce the electrical path

length for the AC ripple currents that are a

major source of radiated emissions from DCDC

bandwidth

providing

excellent

transient

performance. The high switching frequency

enables the use of very small components

making possible this unprecedented level of

integration.

converters.

The

integrated

inductor

significantly reduces parasitic effects that can

harm loop stability, and makes layout very

simple.

Enpirion’s

proprietary

power

MOSFET

technology provides very low switching loss at

frequencies of 4 MHz and higher, allowing for

the use of very small internal components, and

very wide control loop bandwidth. Unique

magnetic design allows for integration of the

inductor into the very low profile 1.1mm

package. Integration of the inductor virtually

eliminates the design/layout issues normally

Soft Start

Internal soft start circuits limit in-rush current

when the device starts up from a power down

condition or when the “ENABLE” pin is

asserted “high”. Digital control circuitry limits

the V_OUTramp rate to levels that are safe for

the Power MOSFETS and the integrated

inductor.

associated

with

switch-mode

DCDC

converters. All of this enables much easier

and faster integration into various applications

to meet demanding EMI requirements.

The EN5311QI operates in a constant slew

rate when the output voltage is programmed

with an internal VID code. The EN5311QI,

when in external resistor divider mode, has a

constant start up time. Please refer to the

Electrical Characteristics table for soft-start

slew rates and soft-start time

Output voltage is chosen from seven preset

values via a three pin VID voltage select

scheme. An external divider option enables

the selection of any voltage in the 0.6V to V_IN-

0.6V range. This reduces the number of

components that must be qualified and

reduces inventory burden. The VID pins can

be toggled on the fly to implement glitch free

dynamic voltage scaling.

Excess bulk capacitance on the output of the

device can cause an over-current condition at

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03799

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EN5311QI

During initial power up an under voltage

lockout circuit will hold-off the switching

circuitry until the input voltage reaches a

sufficient level to insure proper operation. If

the voltage drops below the UVLO threshold

the lockout circuitry will again disable the

switching. Hysteresis is included to prevent

chattering between states.

startup. Assuming no-load at startup, the

maximum total capacitance on the output,

including the output filter capacitor, bulk and

decoupling capacitance, at the load, is given

as:

In VID Mode:

C_{OUT_TOTAL_MAX}= C_{OUT_Filter}+ C_{OUT_BULK}= 700uF

Enable

In external divider mode:

C_{OUT_TOTAL_MAX}= 1.22x10^-3/V_OUTFarads

The ENABLE pin provides a means to shut

down the converter or enable normal

operation. A logic low will disable the converter

and cause it to shut down. A logic high will

enable the converter into normal operation. In

shutdown mode, the device quiescent current

will be less than 1 uA.

The nominal value for C_OUTis 10uF. See the

applications section for more details.

Over Current/Short Circuit Protection

The current limit function is achieved by

sensing the current flowing through a sense P-

MOSFET which is compared to a reference

current. When this level is exceeded the P-

FET is turned off and the N-FET is turned on,

pulling V_OUTlow. This condition is maintained

for a period of 1mS and then a normal soft start

is initiated. If the over current condition still

persists, this cycle will repeat in a “hick-up”

mode.

NOTE: This pin must not be left floating.

Thermal Shutdown

When excessive power is dissipated in the

chip, the junction temperature rises. Once the

junction temperature exceeds the thermal

shutdown temperature the thermal shutdown

circuit turns off the converter output voltage

thus allowing the device to cool. When the

junction temperature decreases by 15C°, the

device will go through the normal startup

process.

Under Voltage Lockout

Application Information

optimum compensation, independent of the

output voltage selected.

Output Voltage Select

To provide the highest degree of flexibility in

choosing output voltage, the EN5311QI uses a

3 pin VID, or Voltage ID, output voltage select

arrangement. This allows the designer to

choose one of seven preset voltages, or to use

an external voltage divider. Internally, the

output of the VID multiplexer sets the value for

the voltage reference DAC, which in turn is

connected to the non-inverting input of the

error amplifier. This allows the use of a single

feedback divider with constant loop gain and

Table 1 shows the various VS0-VS2 pin logic

states and the associated output voltage

levels. A logic “1” indicates a connection to V_IN

or to a “high” logic voltage level. A logic “0”

indicates a connection to ground or to a “low”

logic voltage level. These pins can be either

hardwired to V_INor GND or alternatively can be

driven by standard logic levels. Logic low is

defined as V_LOW≤ 0.4V. Logic high is defined

as V_HIGH≥ 1.4V. Any level between these two

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EN5311QI

1.2x10⁵

values is indeterminate. These pins must not

be left floating.

R_b

V_OUT− 0.603

The External Voltage Divider pin, V_FB,may be

left floating for all VID settings other than the

VS0=VS1=VS2= ”1”.

V_OUTcan be programmed over the range of

0.6V to V_IN– 0.6V (0.6 is the nominal full load

dropout voltage including margin).

Table 1. VID voltage select settings.

ENABLE

V_Sense

V_OUT

V_IN

V_in

V_out

VS2

VS1

VS0

V_OUT

4.7uF

10μF

27pF

3.3V

V_FB

2.5V

1.8V

1.5V

1.25V

1.2V

V_S0

V_S1

V_S2

GND

0.8V

User

Selectable

Figure 5. External Divider (V_IN> 5.5V).

For applications where V_IN> 5.5V, the V_SENSE

connection is not necessary, but the addition of

C_A= 27pF is required.

External Voltage Divider

As described above, the external voltage

divider option is chosen by connecting the

VS0, VS1, and VS2 pins to V_INor logic “high”.

The EN5311QI uses a separate feedback pin,

VFB, when using the external divider.

Dynamically Adjustable Output

The EN5311QI is designed to allow for

dynamic switching between the predefined VID

voltage levels. The inter-voltage slew rate is

optimized to prevent excess undershoot or

overshoot as the output voltage levels

transition. The slew rate is identical to the soft-

start slew rate of 1.65V/mS.

For applications with V_IN≤ 5.5V, VSENSE must

be connected to VOUT as indicated in Figure 4.

Figure 5 indicates the required connections for

V_IN> 5.5V.

ENABLE

V_Sense

Dynamic transitioning between internal VID

settings and the external divider is not allowed.

V_OUT

V_IN

V_in

V_out

4.7uF

10μF

V_FB

V_S0

V_S1

V_S2

Input and Output Capacitors

GND

The input capacitance requirement is 4.7uF.

Enpirion recommends that a low ESR MLCC

capacitor be used. The input capacitor must

use a X5R or X7R or equivalent dielectric

Figure 4. External Divider (V_IN≤ 5.5V).

The output voltage is selected by the following

formula:

formulation.

Y5V or equivalent dielectric

formulations lose capacitance with frequency,

bias, and with temperature, and are not

suitable for switch-mode DC-DC converter

input and output filter applications.

V_OUT= 0.603V

(

)

R_amust be chosen as 200KΩ to maintain loop

gain. Then R_bis given as:

www.enpirion.com

03799

11/24/2009

Rev:B

EN5311QI

Excess total capacitance on the output (Output

Filter + Bulk) can cause an over-current

condition at startup. Refer to the section on

Soft-Start for the maximum total capacitance

on the output.

The output capacitance requirement is a

minimum of 10uF. The control loop is

designed to be stable with up to 60uF of total

output capacitance next to the output pins of

the device without requiring modification to the

compensation network. V_OUThas to be sensed

at the last output filter capacitor next to the

device. Capacitance above the 10uF minimum

should be added if the transient performance is

The output capacitor must use a X5R or X7R

or equivalent dielectric formulation. Y5V or

equivalent

dielectric

formulations

lose

capacitance with frequency, bias, and

temperature and are not suitable for switch-

mode DC-DC converter input and output filter

applications.

not sufficient using the 10uF.

Enpirion

recommends a low ESR MLCC type capacitor

be used.

Additional bulk capacitance for decoupling and

bypass can be placed at the load as long as

there is sufficient separation between the V_OUT

Sense point and the bulk capacitance. The

separation provides an inductance that isolates

the control loop from the bulk capacitance.

Power-Up Sequencing

During power-up, ENABLE should not be

asserted before VIN. Tying these pins together

meets these requirements.

Cin

Manufacturer

Cout

Manufacturer

Part #

Value

WVDC Case Size

Part #

Value

WVDC Case Size

Murata

GRM219R61A475KE19D

GRM319R61A475KA01D

GRM219R60J475KE01D

GRM31MR60J475KA01L

4.7uF

10V

0805

1206

0805

1206

Murata

GRM219R60J106KE19D

GRM319R60J106KE01D

10uF

6.3V

0805

1206

Panasonic

Taiyo Yuden

ECJ-2FB0J106K

ECJ-3YB0J106K

10uF

6.3V

0805

1206

Panasonic

ECJ-2FB1A475K

ECJ-3YB1A475K

ECJ-2FB0J475K

ECJ-3YB0J475K

4.7uF

10V

6.3V

0805

1206

0805

1206

JMK212BJ106KD-T

JMK316BJ106KF-T

10uF

6.3V

0805

1206

Taiyo Yuden

LMK212BJ475KG-T

LMK316BJ475KD-T

JMK212BJ475KD-T

4.7uF

10V

6.3V

0805

1206

0805

1. For V_IN≤ 5.5V

LAYOUT CONSIDERATIONS*

*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.

Recommendation 1: Input and output filter capacitors should be placed on the same side of the

PCB, and as close to the EN5311QI package as possible. They should be connected to the device

with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor

pads to the respective nodes. The +V and GND traces between the capacitors and the EN5311QI

should be as close to each other as possible so that the gap between the two nodes is minimized,

even under the capacitors.

Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the

Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground

pad for the input and output filter capacitors should be isolated ground islands and should be

connected to system ground as indicated in recommendation 3 and recommendation 5.

www.enpirion.com

03799

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EN5311QI

Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect

ground terminals of the Input capacitor and the output capacitor to the system ground plane. This

provides a low inductance path for the high-frequency AC currents; thereby reducing ripple and

suppressing EMI (see Fig. 6, Fig. 7, and Fig. 8).

Recommendation 4: The large thermal pad underneath the component must be connected to the

system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill

size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for

heat dissipation from the converter.

Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be

the first layer immediately below the surface layer (PCB layer 2). This ground plane should be

continuous and un-interrupted below the converter and the input and output capacitors that carry

large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an

uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the

EN5311QI and its input and output capacitors. The vias that connect the input and output capacitor

grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as

well.

Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or

control lines underneath the converter package.

Recommendation 7: The VOUT sense point should be just after the last output filter capacitor next

to the device. Keep the sense trace short in order to avoid noise coupling into the node.

Recommendation 8: Keep R_a, C_a, and R_bclose to the VFB pin (see Figures 4 and 5). The VFB pin is

a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible,

connect R_bdirectly to the GND pin instead of going through the GND plane.

Figure 6 shows an example schematic for the EN5311QI using the internal voltage select. In this

example, the device is set to a VOUT of 1.5V (VS2=0, VS1=1, VS0=1).

Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The

resistor values are chosen to give an output voltage of 2.6V.

VS2

VS1

Rb=60K

Ra=200K

V_OUT

VS1

VS0

ENABLE

V_OUT

V_IN

4.7uF

10μF

4.7uF

10μF

(see layout recommendation 3)

Figure 6. Example application, Vout=1.5V.

Figure 7. Example Application, external divider, Vout = 2.6V.

Figure 8 shows an example board layout. The left side of the figure demonstrates construction of the

PCB top layer. Note the placement of the vias from the input and output filter capacitor grounds, and

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EN5311QI

the thermal pad, to the PCB ground on layer 2 (1^stlayer below PCB surface). The right side of the

figure shows the layout with the components populated. Note the placement of the vias per

recommendation 3.

Thermal Vias to Ground Plane

Package

Outline

C_IN

C_OUT

Vias to Ground Plane

Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter

capacitor local grounds, and thermal pad, to PCB system ground.

Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom of Package

Enpirion has developed a break-through in package technology that utilizes the lead frame as part of

the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced

electrical lead resistance, and in overall foot print. However, it does require some special

considerations.

As part of the package assembly process, lead frame construction requires that for mechanical

support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal

passives are attached. This results in several small pads being exposed on the bottom of the

package.

Only the large thermal pad and the perimeter pin pads are to be mechanically or electrically

connected to the PC board. The PCB top layer under the EN5311QI should be clear of any metal

except for the large thermal pad. The “grayed-out” area in Figure 9 represents the area that should

be clear of any metal (traces, vias, or planes), on the top layer of the PCB.

NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the

perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC

MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest

adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.

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EN5311QI

Thermal Pad.

Connect to

Ground plane

Figure 9. Exposed metal and mechanical dimensions of the package. Gray area represents bottom metal no-

connect and area that should be clear of any traces, planes, or vias, on the top layer of the PCB.

0.25

0.20

JEDEC minimum separation = 0.20

Figure 10. Exposed pad clearances; the Enpirion lead frame package complies with JEDEC requirements.

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EN5311QI

Figure 11. Recommended solder mask opening.

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EN5311QI

Figure 12. Package mechanical dimensions.

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EN5311QI

Ordering Information

Part Number

EN5311QI

Temp Range

-40°C to +85°C

Package

QFN20

Tape & Reel

EN5311QI-E

Evaluation Board

Contact Information

Enpirion, Inc.

Perryville III

53 Frontage Road, Suite 210

Hampton, NJ 08827

USA

Phone: +1 908-894-6000

Fax: +1 908-894-6090

www.enpirion.com

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is

believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may

result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment

used in hazardous environment without the express written authority from Enpirion.

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03799

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EN5311QI相关文章

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EN5311QI产品参数

型号:	EN5311QI
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
包装说明：	HQCCN, LCC20,.17X.21,25
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	3.77
Samacsys Confidence：	4
Samacsys Status：	Released
Samacsys PartID：	1386683
Samacsys Pin Count：	21
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Other
Samacsys Footprint Name：	EN5311QI-3
Samacsys Released Date：	2019-09-10 15:52:31
Is Samacsys：	N
其他特性：	OUTPUT VOLTAGE RANGE FROM 0.6 V TO 6 V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	6.6 V
最小输入电压：	2.4 V
标称输入电压：	3.6 V
JESD-30 代码：	R-XQCC-N20
JESD-609代码：	e3
长度：	5 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1 A
封装主体材料：	UNSPECIFIED
封装代码：	HQCCN
封装等效代码：	LCC20,.17X.21,25
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, HEAT SINK/SLUG
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.15 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	4000 kHz
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	NO LEAD
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	10
宽度：	4 mm
Base Number Matches：	1

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