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产品型号EN5394QI的概述

芯片EN5394QI的概述 EN5394QI是一款广泛应用于电源管理和电压调节的高效能芯片，属于一系列集成电路（IC）中的一种。这款芯片主要用于为电子设备提供稳定的电源，尤其是在对电压精度和效率要求较高的场合。EN5394QI集成了多种功能，例如电源转换、过压保护和低功耗设计，适合在移动设备、工业应用及消费电子产品中使用。芯片EN5394QI的详细参数 EN5394QI在电源管理上表现出色，拥有如下关键参数： - 输入电压范围：芯片可以在3.0V到20V的输入电压范围内工作，能够适应多种电源情况。 - 输出电压范围：支持调节输出电压，一般在1.0V到15V之间，具体需要根据应用进行配置。 - 最大输出电流：EN5394QI可以提供高达1A的输出电流，适合驱动中等功率的设备。 - 效率：在典型负载条件下，其转换效率可达到90%以上，显示出优异的电源管理能力。 - 静态功耗：静态功耗低至...

产品型号EN5394QI的Datasheet PDF文件预览

EN5394QI

Feature Rich 9A Voltage Mode

Synchronous Buck PWM DC-DC Converter

with Integrated Inductor

RoHS Compliant - Halogen Free

Typical Application Circuit

Description

The EN5394QI is a Power Supply on a Chip

(PwrSoC) DC to DC converter with integrated

inductor, PWM controller, MOSFETS, and

compensation providing the smallest possible

solution size in a 68 pin QFN module. The

switching frequency can be synchronized to an

external clock or other EN5394QIs with the

added capability of phasing multiple EN5394QIs

as desired. Other features include precision

ENABLE threshold, pre-bias monotonic start-up,

margining, and parallel operation.

V_IN

PVIN

VOUT

V_OUT

2x47μF

47μF

AVIN

ENABLE

PGND

VFB

OCP_ADJ

15nF

PGND

AGND

Figure 1: Typical Application Schematic

EN5394QI is specifically designed to meet the

precise voltage and fast transient requirements

of present and future high-performance

applications such as set-top boxes/HD DVRs,

LAN/SAN adapter cards, audio/video equipment,

optical networking, multi-function printers, test

and measurement, embedded computing,

Features

• Integrated Inductor, MOSFETS, Controller in

a 8 x 11 x 1.85mm package

• Wide input voltage range of 2.375V to 6.6V.

• > 30W continuous output power.

• High efficiency, up to 93%.

storage,

and

servers.

Advanced

circuit

techniques, ultra high switching frequency, and

very advanced, high-density, integrated circuit

and proprietary inductor technology deliver high-

quality, ultra compact, non-isolated DC-DC

conversion. Operating this converter requires

very few external components.

• Output voltage margining

• Monotonic output voltage ramp during start-

up with pre-biased loads.

• Precision Enable pin for accurate sequencing

of power converters and Power OK signal.

• Programmable soft-start time.

• Soft Shutdown.

The Enpirion integrated inductor solution

significantly helps to reduce noise. The complete

power converter solution enhances productivity

by offering greatly simplified board design, layout

and manufacturing requirements.

• 4 MHz operating frequency with ability to

synchronize to an external system clock or

other EN5394’s.

• Programmable phase delays between

synchronized units to allow reduction of

input ripple.

• Master/slave configuration for paralleling

multiple EN5394’s for greater power output.

• Under Voltage Lockout, Over-current, Short

Circuit, and Thermal Protection

All Enpirion products are RoHS compliant and

lead-free manufacturing environment compatible.

• RoHS compliant, MSL level 3, 260C reflow.

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EN5394QI

Applications

• Point of load regulation for low-power

processors, network processors, DSPs,

FPGAs, and ASICs

• Applications requiring monotonic start-up with

pre-bias

• Low voltage, distributed power architectures

with 2.5V, 3.3V or 5V, 6V rails

• Ripple voltage sensitive applications

• Noise sensitive applications

• Computing, broadband, networking,

LAN/WAN, optical, test & measurement

• A/V, high density cards, storage, DSL, STB,

DVR, DTV, Industrial PC

• Beat frequency sensitive applications

Ordering Information

Temp Rating

Part Number

EN5394QI-T

EN5394QI-E

(°C)

-40 to +85

Package

68-pin QFN T&R

QFN Evaluation Board

Pin Configuration

Figure 2: Pinout Diagram (Top View). All perimeter pins must be soldered to PCB.

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EN5394QI

Pin Descriptions

1-4,

NAME

FUNCTION

Input/Output power ground. Connect these pins to the ground electrode of the input

27-33,

64-68

PGND

and output filter capacitors. See VOUT and PVIN descriptions for more details.

Regulated converter output. Connect to the load, and place output filter capacitor(s)

between these pins and PGND pins 1-4 and 64-68.

5-13

VOUT

NO CONNECT: These pins must be soldered to PCB but not be electrically connected

to each other or to any external signal, voltage, or ground. These pins may be

connected internally. Failure to follow this guideline may result in device damage.

NO CONNECT: These pins are internally connected to the common switching node of

the internal MOSFETs. They must be soldered to PCB but not be electrically

connected to any external signal, ground, or voltage. Failure to follow this guideline

may result in device damage.

14-24,

44-47

25-26

NC(SW)

Input power supply. Connect to input power supply, place input filter capacitor(s)

between these pins and PGND pins 27-33.

34-43

PVIN

Clock Output. Depending on the mode, either a clock signal or the PWM signal is

output on this pin. These signals are delayed by a time that is related to the resistor

connected between S_DELAY and AGND. Leave this pin floating if not needed.

Clock Input. Depending on the mode, this pin accepts either an input clock to

synchronize the internal switching frequency or the S_OUT signal from another

EN5394QI. Leave this pin floating if it is not used.

S_OUT

S_IN

This is a Ternary Input. Floating the pin disables parallel operation. A low level

configures the device as Master and a High level configures the device as a slave.

This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support

monotonic start-up under a pre-biased load. There is a 150kΩ pull-down on this pin.

This is the Device Enable pin. A high level enables the device while a low level

disables the device.

Input power supply for the controller. Needs to be connected to V_INat a quiet point.

Power OK is an open drain transistor for power system state indication. POK is a

logic high when VOUT is with -10% to +20% of VOUT nominal. Being an open drain

output allows several devices to be wired to logically AND the function. Size pull-up

resistor to limit current to 4mA when POK is low.

M/S

EN_PB

ENABLE

AVIN

POK

AGND

VFB

Ground return for the controller. Needs to be connected to a quiet ground.

External Feedback input. The feedback loop is closed through this pin. A voltage

divider at V_OUTis used to set the output voltage. The mid-point of the divider is

connected to VFB. The control loop regulates to make the VFB node voltage 0.6V.

Optional Error Amplifier output. Allows for customization of the control loop.

EAOUT

OCP_ADJ This pin should be pulled to GND for proper operation of the OCP circuit.

A soft-start capacitor is connected between this pin to AGND. The value of the

capacitor controls the soft-start interval and startup time.

A resistor is connected between this pin and AGND. The value of the resistor controls

the delay in S_OUT. This pin can be left floating if the S_OUT function is not used.

S_DELAY

These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float

MAR1,

MAR2

condition. 7 of the 9 states are used to modulate the output voltage by 0%, ±2.5%,

±5% or ±10%. The 8th state is used to by-pass the delay in S_OUT. See Functional

Description section.

61-62

VSENSE This pin senses VOUT when the device is placed in the Back-feed (or Pre-bias) mode.

Device thermal pads to be connected to the system gnd plane. See Layout

Recommendations section.

69, 70

PGND

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EN5394QI

Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond

recommended operating conditions is not implied. Stress beyond absolute maximum ratings may

cause permanent damage to the device. Exposure to absolute maximum rated conditions for

extended periods may affect device reliability.

PARAMETER

SYMBOL

MIN

-0.5

-65

MAX

7.0

V_IN+ 0.3

2.7

UNITS

Voltages on PVIN, AVIN, VOUT

V_IN

Voltages on VSENSE, ENABLE, EN_PB, POK,

Voltages on VFB, EAOUT, SS, S_IN, S_OUT, OCP_ADJ

Voltages on MAR1, MAR2, M/S

3.6

150

260

Storage Temperature Range

T_STG

T_{J-ABS MAX}

°C

Maximum Operating Junction Temperature

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A

ESD Rating (based on Human Body Model)

2000

Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Voltage Range

V_IN

V_OUT

I_LOAD

T_A

2.375

0.60

6.6

°C

†

Output Voltage Range

V_IN– V_DO

Output Current

Operating Ambient Temperature

Operating Junction Temperature

-40

+85

+125

T_J

^†V_{DO (}drop-out voltage) is defined as (I_LOADx Dropout Resistance). Please see Electrical Characteristics table.

Thermal Characteristics

PARAMETER

Thermal Resistance: Junction to Ambient (0 LFM)^††

Thermal Resistance: Junction to Case

Thermal Shutdown Trip Point

SYMBOL

θ_JA

TYP

+150

UNITS

°C/W

°C

θ_JC

T_SD

T_SDH

Thermal Shutdown Trip Point Hysteresis

°C

^††Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.

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EN5394QI

Electrical Characteristics

NOTE: V_IN=5.5V over operating temperature range unless otherwise noted.

Typical values are at T_A= 25°C.

PARAMETER

Input Voltage

SYMBOL

V_IN

COMMENTS

MIN

2.375

TYP

MAX UNITS

6.6

Under Voltage Lock out

threshold

V_UVLOR

V_UVLOF

V_INIncreasing

V_INDecreasing

2.2

2.1

Shut-Down Supply

Current

I_S

ENABLE=0V

250

μA

2.375V ≤ VIN ≤ 6.6V,

Feedback Pin Voltage

V_FB

I_FB

0.588

-5

0.600

0.612

_LOAD= 1A; T_A= 25°C

Feedback Pin Input Leakage

Current¹

Line Regulation

Load Regulation

Temperature Regulation

2.375V ≤ V_IN≤ 6.6V

0A ≤ ILOAD ≤ 6A

ΔV_{OUT_TEMP}-40°C ≤ TEMP ≤ 85°C

Measured from when V_IN≥ V_UVLOR

0.035

−0.04

0.001

%/V

%/A

%/°C

ΔV_{OUT_LINE}

ΔV_{OUT_LOAD}

C_SSx

T_RISE

& ENABLE pin crosses logic high

threshold. (4.7nF ≤ C_SS≤ 100nF)

4.7nF ≤ C_SS≤ 100nF

V_OUTRise Time

65kΩ

Rise Time Accuracy¹

Output Dropout

Voltage¹

-25

+25

ΔT_RISE

mΩ

V_DO

R_DO

V_INMIN– V_OUTat Full Load

Input to Output Resistance

360

720

Resistance¹

Maximum Continuous

Output Current²

Current Limit Threshold

ENABLE pin:

I_{OUT_MAX_CONT}

I_OCP

OCP_ADJ pulled low

2.375V ≤ V_IN≤ 6.6V

Disable Threshold

Enable Threshold

V_DISABLE

V_ENABLE

ENABLE pin logic low

1.0

1.30

ENABLE pin logic high

Time for device to re-enable after

a falling edge on ENABLE pin

1.10

t_ENLO

ENABLE Lock-out time

ENABLE Pin Input

Current

I_ENABLE

F_SWITCH

F_{PLL_LOCK}

V_IN= 5.5V

μA

Switching Frequency

External S_IN Clock

Frequency Lock Range

S_IN Threshold – Low

S_IN Threshold – High

S_OUT Threshold – Low

S_OUT Threshold – High

S_IN Duty Cycle for

External Synchronization¹

S_IN Duty Cycle for

Parallel Operation¹

Free Running frequency

Frequency Range of S_IN

Input Clock

S_IN Clock low level

S_IN Clock high level

S_OUT Clock low level

S_OUT Clock high level

MHz

3.6

1.8

4.4

V_{S_IN_LO}

V_{S_IN_HI}

V_{S_OUT_LO}

V_{S_OUT_HI}

0.8

2.5

0.5

1.8

SY_{DC_SYNC}M/S Pin Float or Low

SY_{DC_PWM}M/S Pin High

Delay in ns / kΩ

Phase Delay vs. S_Delay

Resistor value

Φ_DEL

Delay in phase angle / kΩ -

@ 4MHz switching frequency

Phase delay programmable via

resistor connected from S_Delay

to AGND.

Phase Delay between

S_IN and S_OUT¹

150

Φ_DEL

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EN5394QI

Phase Delay between

S_IN and S_OUT¹

Delay By-Pass Mode

(MAR1 floating, MAR2 high)

Φ_DEL

Phase Delay Accuracy¹

-20

Allowable Pre-Bias as a fraction

of programmed output voltage

(subject to a minimum of 300mV)

Allowable non monotonicity

Pre-Bias Level

V_PB

Non-Monotonicity

V_{PB_NM}

POK_LT

120

115

POK Lower Threshold as

V_OUTrising

V_OUTfalling

V_OUTrising

V_OUTfalling

a percent of V_OUT

POK Upper Threshold as

POK_UT

a percent of V_OUT

POK Falling Edge

µs

Deglitch Delay⁴

POK Output Low Voltage

POK Output High Voltage

Ternary Pin Logic Low⁵

V_POKL

V_POKH

V_T-Low

With 4mA current sink into POK

2.375V ≤ V_IN≤ 6.6V

Tie pin to GND

0.4

V_IN

see Input

Current

below

Pull up to V_INthrough an external

resistor R_EXT– see Figure 5.

Ternary Pin Logic High⁵

V_T-High

V_IN= 2.375V, R_EXT= 3.32kΩ

V_IN= 3.3V, R_EXT= 15kΩ

V_IN= 5.0V, R_EXT= 24.9kΩ

V_IN= 6.6V, R_EXT= 49.9kΩ

100

Ternary Pin Input Current

(see Figure 5)⁵

I_TERN

μA

Binary Input Logic Low

Threshold⁶

V_B-Low

V_B-High

0.8

Binary Input Logic High

1.8

Threshold⁶

NOTES:

1. Parameter guaranteed by design.

2. Maximum output current may need to be de-rated, based on operating condition, to meet T_Jrequirements.

3. POK threshold when V_OUTis rising is nominally 92%. This threshold is 90% when V_OUTis falling. After crossing the

90% level, there is a 256 clock cycle (~50us) delay before POK is de-asserted. The 90%, 92%, 115%, and 120%

levels are nominal values. Expect these thresholds to vary by ±3%.

4. On the falling edge of VOUT below 90% of programmed value, POK response is delayed for the duration of the

deglitch delay time. Any VOUT glitch shorter than the deglitch time is ignored.

5. M/S, MAR1, and MAR2 are ternary. Ternary pins have three logic levels: high, float, and low. These pins are only

meant to be strapped to V_INthrough an external resistor, strapped to GND, or left floating. Their state cannot be

changed while the device is on.

6. Binary input pins are EN_PB and OCP_ADJ.

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03738

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Rev:B

EN5394QI

Typical Performance Characteristics

V_IN= 3.3V

V_IN= 5V

Load (Amps)

Efficiency V_IN= 3.3V

V_OUT(From top to bottom) = 2.5, 1.8, 1.2, 1.0V

Efficiency V_IN= 5.0V

V_OUT(From top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0V

20 MHz BW limit

500 MHz BW

Output Ripple: V_IN= 3.3V, V_OUT= 1.2V, Iout = 9A

C_IN= 2 x 22μF/1206, C_OUT= 2 x 47μF/1206

20 MHz BW limit

500 MHz BW

Output Ripple: V_IN= 5.0V, V_OUT= 1.2V, Iout = 9A

C_IN= 2 x 22μF/1206, C_OUT= 2 x 47μF/1206

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EN5394QI

Load Transient: V_IN= 5.0V, V_OUT= 1.2V

Ch.1: V_OUT, Ch.4: I_LOAD0↔9A (slew rate ≥ 10A/µS)

C_IN≈ 50μF, C_OUT≈ 100μF

Load Transient: V_IN= 3.3V, V_OUT= 1.2V

Ch.1: V_OUT, Ch.4: I_LOAD0↔9A (slew rate ≥ 10A/µS)

C_IN≈ 50μF, C_OUT≈ 100μF

R_A= 150kΩ, C_A= 33pF (see Figure 4)

R_A= 100kΩ, C_A= 56pF (see Figure 4)

Power Up/Down at No Load: V_IN/V_OUT= 5.0V/1.2V,

15nF soft-start capacitor,

Power Up/Down into 0.2Ω load: V_IN/V_OUT= 5.0V/1.2V,

15nF soft-start capacitor,

Ch.1: ENABLE, Ch.2: V_OUT, Ch.3; POK

Delay vs. S_Delay Resistance

180

160

140

120

100

S_Delar R (kohm)

ENABLE Lockout Operation

Ch.1: ENABLE, Ch2: V_OUT

Delay vs. S_Delay Resistance

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EN5394QI

Block Diagram

Figure 3: System block diagram.

Functional Description

type III, voltage-mode, and the device uses a

low-noise PWM topology. Up to 9A of continuous

output current can be drawn from this converter.

The 4MHz operating frequency enables the use

of small-size input and output capacitors.

Synchronous Buck Converter

The EN5394QI is a synchronous, programmable

power supply with integrated power MOSFET

switches and integrated inductor. The nominal

input voltage range is 2.375-6.6V. The output

voltage is programmed using an external resistor

divider network. The feedback control loop is a

The power supply has the following protection

features:

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EN5394QI

• Over-current protection with hiccup mode.

• Short Circuit protection.

• Thermal shutdown with hysteresis.

• Under-voltage lockout circuit to disable the

converter output when the input voltage is

less than approximately 2.2V

Master / Slave Parallel Operation

Multiple EN5394QI devices may be connected in

parallel in a Master/Slave configuration to handle

load currents greater than device maximum

rating. The device is set in Master mode by

pulling the ternary M/S pin low or in Slave mode

by pulling M/S pin high to V_INthrough an external

resistor. When this pin is in Float state, parallel

operation is not possible. In master mode, the

internal PWM signal is output on the S_OUT pin.

This PWM signal from the Master can be fed to

one or more Slave devices at its S_IN input. The

Slave device acts like an extension of the power

FETs in the Master. As a practical matter,

Enable Operation

The ENABLE pin provides a means to start

normal operation or to shut down the device. A

logic high will enable the converter into normal

operation. When the ENABLE pin is asserted

(high) the device will undergo a normal soft start.

A logic low will disable the converter. A logic low

will power down the device in a controlled

manner and the device is subsequently shut

down. The device will remain shut-down for the

duration of the ENABLE lockout time (see

Electrical Characteristics Table). If the ENABLE

signal is re-asserted during this time, the device

will power up with a normal soft-start at the end

of the ENABLE lockout time.

paralleling more than 4 devices may be very

difficult from the view point of maintaining very

low impedance in V_INand V_OUTlines.

The table below summarizes the different

configurations for the S_IN and S_OUT pins

depending on the condition of the M/S pin:

When M/S

pin is:

High (Slave) Low (Master) Float

The Enable threshold is a precision Analog

voltage rather than a digital logic threshold.

Precision threshold along with choice of soft-start

capacitor helps to accurately sequence multiple

power supplies in a system.

S_IN input S_OUT from External Sync input if

should be: Master

needed (NC for internal

clock)

S_OUT is

equal to

Same duty

cycle as

Same duty

cycle as

S_IN or

internal

(subject to S_IN

S_DELAY):

internal PWM clock

Frequency Synchronization

The switching frequency of the DC/DC converter

can be phase-locked to an external clock source

to move unwanted beat frequencies out of band.

To avail this feature, the ternary input M/S pin

should be floating or pulled low. The internal

switching clock of the DC/DC converter can then

be phase locked to a clock signal applied to S_IN

pin. An activity detector recognizes the presence

of an external clock signal and automatically

phase-locks the internal oscillator to this external

clock. Phase-lock will occur as long as the input

clock frequency is within ±10% of the free

running frequency (see Electrical Characteristics

table). When no clock signal is present, the

device reverts to the free running frequency of

the internal oscillator. The external clock input

may be swept between 3.6 MHz and 4.4 MHz at

repetition rates of up to 10 kHz in order to reduce

EMI frequency components.

Please contact Enpirion Applications support for

more information on Master / Slave operation.

Phase Delay

In all cases, S_OUT can be delayed with respect

to internal switching clock or the clock applied to

S_IN. Multiple EN5394QI devices on a system

board may be daisy chained to reduce or

eliminate input ripple as well as avoiding beat

frequency components. The EN5394QIs can all

be phase locked by feeding S_OUT of one

device into S_IN of the next device in a daisy

chain. All the switchers now run at a common

frequency. The delay is controlled by the value of

a resistor connected between S_DELAY and

AGND pins. The magnitude of this delay as a

function of S_DELAY resistor is shown in the

Electrical Characteristics table. See Figures 6

and 7 for an example of using phase delay.

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EN5394QI

During a soft-start cycle, when the soft-start

capacitor voltage reaches 0.60V, the output has

reached its programmed regulation range. Note

that the soft-start current source will continue to

charge the SS capacitor beyond 0.6V. During

normal operation, the soft-start capacitor will

charge to a final value of ~1.5V.

Margining

Using MAR1 and MAR2 pins, the nominal output

voltage can be increased / decreased by 2.5, 5

or 10% for system compliance, reliability or other

tests. The POK threshold voltages scale with the

margined output voltages. The following table

provides the possible combinations:

Soft-Shutdown Operation

MAR1

Float

Low

High

Low

High

Low

High

Float

MAR2

Float

Low

Output Modulation

When the Enable signal is de-asserted, the soft-

start capacitor is discharged in a controlled

manner. Thus the output voltage ramps down

gradually. The internal circuits are kept active for

the duration of soft-shutdown, thereafter they are

deactivated.

-2.5%

+2.5%

-5%

+5%

Low

High

Float

High

Low

-10%

+10%

0%, Delay Bypass

Reserved

Pre-Bias Operation

When EN_PB is asserted, the device will support

a monotonic output voltage ramp if the output

capacitor is charged to a pre-bias level.

Note: Low means tie to GND. High means tie to V_IN

as shown in Figure 5.

Proprietary circuit ensures the output voltage

ramps monotonically from pre-bias voltage to the

programmed output voltage. Monotonic start-up

is guaranteed by design for pre-bias voltages

between 20% and 85% of the programmed

output voltage. This feature is not supported

when ENABLE is tied to V_IN.

As shown above, when MAR1 is floating, and

MAR2 is high, the device enters the delay

bypass mode. In this mode, the delay from the

internal clock or S_IN to S_OUT is almost

eliminated (see Electrical Characteristics table).

Soft-Start Operation

The SS pin in conjunction with a small external

capacitor between this pin and AGND provides

the soft start function to limit the in-rush current

during start-up. During start-up of the converter

the reference voltage to the error amplifier is

gradually increased to its final level as an internal

current source of typically 10uA charges the soft

start capacitor. The typical soft-start time for the

output to reach regulation voltage, from when

AVIN > V_UVLOand ENABLE crosses its logic high

threshold, is given by:

POK Operation

The POK signal indicates if the output voltage is

within a specified range. The POK signal is

asserted when the rising output voltage crosses

92% (nominal) of the programmed output

voltage. POK is de-asserted ~50us (256 clock

cycles) after the falling output voltage crosses

90% (nominal) of the programmed voltage. POK

is also de-asserted if the output voltage exceeds

120% of the programmed output. If the feedback

loop is broken, POK will remain de-asserted

(output < 92% of programmed value), and the

output voltage will equal the input voltage. If

however, there is a short across the PFET, and

the feedback is in place, POK will be de-asserted

as an over voltage condition. The power NFET is

also turned on, resulting in a large input supply

current. This in turn is expected to trip the OCP

of the EN5394QI input power supply.

T_SS= (C_SS* 65KΩ) ± 25%

where the soft-start time T_SSis in seconds and

the soft-start capacitance C_SSis in Farads.

Typically, around 15nF is recommended. The

soft-start capacitor should be between 4.7nF and

100nF. A proper choice of SS capacitance can

be used advantageously for power supply

sequencing using the precision Enable threshold.

POK is an open drain output. It requires an

external pull up. Multiple EN5394QI’s POK pins

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03738

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Rev:B

EN5394QI

may be connected to a single pull up. The open device has cycle-by-cycle current limiting. Tie

drain NFET is designed to sink up to 4mA. The OCP_ADJ pin to GND for proper OCP operation.

pull-up resistor value should be chosen

Thermal Overload Protection

accordingly for when POK is logic low.

Thermal shutdown will disable operation when

the Junction temperature exceeds approximately

150ºC. Once the junction temperature drops by

approximately 20ºC, the converter will re-start

with a normal soft-start.

Input Under-Voltage Lock-Out (UVLO)

When the input voltage is below a required

voltage level (V_UVLO) for normal operation, the

converter switching is inhibited. The lock-out

threshold has hysteresis to prevent chatter.

UVLO is implemented to ensure that operation

does not begin before there is adequate voltage

to properly bias all internal circuitry.

Compensation

The EN5394 uses of a type III compensation

network. Most of this network is integrated.

However a phase lead capacitor is required in

parallel with upper resistor of the external divider

Over-Current Protection (OCP)

The current limit and short-circuit protection is network (see Figure 4). This network results in a

achieved by sensing the current flowing through wide loop bandwidth and excellent load transient

a sense P-FET. When the sensed current performance. It is optimized for approximately

exceeds the current limit, both NFET and PFET 100μF of output filter capacitance at the voltage

switches are turned off. If the over-current sensing point. Additional decoupling capacitance

condition is removed, the over-current protection may be placed beyond the voltage sensing point

circuit will re-enable the PWM operation. If the outside the control loop. Voltage-mode operation

over-current condition persists, the circuit will provides high noise immunity at light load.

continue to protect the device.

Further, voltage-mode control provides superior

impedance matching to ICs processed in sub

90nm technologies.

The OCP trip point is nominally set to 150% of

maximum rated load. In the event the OCP circuit

trips, the device enters a hiccup mode. The In exceptional cases modifications to the

device is disabled for ~10msec and restarted compensation may be required. The EN5394QI

with a normal soft-start. This cycle can continue provides the capability to modify the control loop

indefinitely as long as the over current condition response to allow for customization for specific

persists. During soft-start at power up or fault applications. For more information, contact

recovery, the hiccup mode is disabled and the Enpirion Applications Engineering support.

Application Information

Output Voltage Programming

R_A= 30,000×Vin (value in Ω)

The EN5394 output voltage is determined by the

5.6×10⁻⁶

voltage presented at the VFB pin. This voltage is

set by way of a resistor divider between V_OUTand

AGND with the midpoint going to VFB. A phase

lead capacitor C_Ais also required for stabilizing

C_A=

(C_A/R_Ain F/Ω)

R_A

Round C_Adown to closest

standard value lower than

calculated value.

the loop. Figure

shows the required

components and the equations to calculate their

values. Please note the equations below are

written to optimize the control loop as a function

of input voltage.

is 0.6V

V_FB× R_A

⎛

⎞

⎜

⎟

R_B=

(V_OUT−V ) nominal

⎝

⎠

Figure 4: Output voltage resistor divider and phase-

lead capacitor calculation. The equations need to be

followed in the order written above.

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03738

8/21/2009

Rev:B

EN5394QI

Z = ESR + ESL.

Input Capacitor Selection

Placing multiple capacitors in parallel reduces

the impedance and hence will result in lower

ripple voltage.

The EN5394QI requires between 30-40uF of

input capacitance. Low ESR ceramic capacitors

are required with X5R or X7R dielectric

formulation. Y5V or equivalent dielectric

formulations must not be used as these lose

capacitance with frequency, temperature and

bias voltage.

+... +

Z_TotalZ₁Z₂

Z_n

Typical ripple versus capacitor arrangement is

given below:

In some applications, lower value ceramic

capacitors may be needed in parallel with the

larger capacitors in order to provide high

frequency decoupling.

Typical Output Ripple (mVp-p)

Output Capacitor

(as measured on EN5394QI

Configuration

Evaluation Board)^†

Recommended Input Capacitors

2x47uF

20mV

12mV

2x47uF + 1x10uF

Description

MFG

Murata

P/N

^†20 MHz bandwidth limit

10uF, 10V, 10%

GRM31CR71A106KA01L

X7R, 1206

Taiyo Yuden LMK316B7106KL-T

Murata GRM31CR61A226ME19L

Taiyo Yuden LMK316BJ226ML-T

Murata GRM31CR60J476ME19L

Taiyo Yuden JMK212BJ476ML-T

(3-4 capacitors needed)

22uF, 10V, 20%

X5R, 1206

(2 capacitors needed)

47uF, 6.3V, 20%

X5R, 1206

Ternary Pin Inputs

The three ternary pins MAR1, MAR2, and M/S

have three possible states. In the Low state, the

pins are to be tied to GND. In the floating state,

nothing is to be connected to the pins. In the

High state, they are to be tied to V_INthrough an

external resistor R_EXTin order to limit the input

current to the pin (see Figure 5). The Electrical

Characteristics table lists, as a function of V_IN,

some recommended values for R_EXT, and the

resulting input currents.

(1 capacitor needed)

Output Capacitor Selection

The EN5394 has been optimized for use with

about 100µF of output filter capacitance.

Additional capacitance may be placed beyond

the voltage sensing point outside the control

loop. For the output filter, low ESR X5R or X7R

ceramic capacitors are required. Y5V or

equivalent dielectric formulations must not be

used as these lose capacitance with frequency,

temperature and bias voltage.

Frequency Sync & Phase Delay

The EN5394 can be synchronized to an external

clock source or to another EN5394 in order to

eliminate unwanted beat frequencies.

Furthermore, two or more synchronized

EN5394’s can have a programmable phase

delay with respect to each other to minimize input

voltage ripple and noise. An example of

synchronizing three EN5394’s with approximately

equal phase delay between them is shown in

Figures 6 and 7. The lowest allowable value for

the S_DELAY resistor is 10kΩ.

Recommended Output Capacitors

Description

47uF, 6.3V, 20%

X5R, 1206

(2 capacitors needed)

10uF, 6.3V, 10%

X5R, 0805

MFG

Murata

P/N

GRM31CR60J476ME19L

Taiyo Yuden

Murata

JMK212BJ476ML-T

GRM21BR60J106KE19L

(Optional 1 capacitor in

parallel with 2x47uF)

Taiyo Yuden

JMK212BJ106KG-T

Output ripple voltage is primarily determined by

the aggregate output capacitor impedance. At Power-Up Sequencing

the 4MHz switching frequency, the capacitor

During power-up, ENABLE should not be

impedance, denoted as Z, is comprised mainly of

effective series resistance, ESR, and effective

series inductance, ESL:

asserted before PVIN, and PVIN should not be

asserted before AVIN. Tying all three pins

together meets these requirements.

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03738

8/21/2009

Rev:B

EN5394QI

2.5V

100k

To Gates

Rext

250

VIN

100k

Vf ~ 2V

Figure 5: Equivalent circuit of a ternary pin

(MAR1, MAR2, or M/S) input buffer. To get a

logic High on a ternary input, pull the pin to V_IN

through an external resistor R_EXT. See Electrical

Characteristics table for some recommended

R_EXTvalues as a function of V_INand the resulting

input currents.

AGND

IC Package

VIN

X1_1

X1_2

EXT_CLK

S_IN

S_OUT

S_IN

S_OUT

VOUT

S_IN

S_OUT

VOUT

OUT1

OUT2

OUT3

VOUT

VFB

EN5364

GND

Figure 6: Example of synchronizing multiple EN5394QIs in a daisy chain with phase delay.

V_DRAIN- 1

Delay ~ 140°

V_DRAIN- 2

V_DRAIN- 3

Delay ~ 120°

Figure 7: Example of a possible way to synchronize and use delays advantageously to minimize input ripple.

R1 ~ 39kΩ, R2 ~ 33kΩ. (Refer to Figure 6 for R1 and R2.) R3 does not matter in this case.

www.enpirion.com

03738

8/21/2009

Rev:B

EN5394QI

Layout Recommendations

− RA and RB are voltage

programming resistors.

− CA is used for loop

compensation.

− CSS is the soft-start

capacitor.

− AGND via is also a test point.

− Test point added for EAOUT.

− CIN can also be 2x22µF for

improved noise/EMI.

Figure 8: Critical Components and Layer 1 Copper for Minimum Footprint

Figure 8 above shows critical components and

layer 1 traces of the recommended EN5394

layout for minimum footprint with ENABLE tied

to V_IN. Alternate ENABLE configurations, and

other small signal pins need to be connected

and routed according to specific customer

application. Please see the Gerber files on the

Enpirion website www.enpirion.com for exact

dimensions and other layers.

thermal pads underneath the component must

be connected to the system ground plane

through as many vias as possible. The drill

diameter of the vias should be 0.33mm, and

the vias must have at least 1 oz. copper plating

on the inside wall, making the finished hole

size around 0.20-0.26mm. Do not use thermal

reliefs or spokes to connect the vias to the

ground plane. This connection provides the

path for heat dissipation from the converter.

Please see figures: 8, 11, and 12.

Recommendation 1: Input and output filter

capacitors should be placed on the same side

of the PCB, and as close to the EN5394QI

package as possible. They should be

connected to the device with very short and

wide traces. Do not use thermal reliefs or

spokes when connecting the capacitor pads to

the respective nodes. The +V and GND traces

between the capacitors and the EN5394QI

should be as close to each other as possible

so that the gap between the two nodes is

minimized, even under the capacitors.

Recommendation 4: Multiple small vias (the

same size as the thermal vias discussed in

recommendation 3) should be used to connect

ground terminal of the input capacitor and

output capacitors to the system ground plane.

It is preferred to put these vias along the edge

of the GND copper closest to the +V copper.

These vias connect the input/output filter

capacitors to the GND plane, and help reduce

parasitic inductances in the input and output

current loops.

Recommendation 2: The system ground

plane referred to in recommendations 2 and 3

should be the first layer immediately below the

surface layer. This ground plane should be

continuous and un-interrupted below the

converter and the input/output capacitors.

Recommendation 5: AVIN is the power supply

for the small-signal control circuits. It should be

connected to the input voltage at a quiet point.

In Figure 8 this connection is made at the input

capacitor.

Recommendation 3: The large and small

Recommendation 6: The layer 1 metal under

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03738

8/21/2009

Rev:B

EN5394QI

the device must not be more than shown in

Figure 8. See the section regarding exposed

metal on bottom of package. As with any

switch-mode DC/DC converter, try not to run

sensitive signal or control lines underneath the

converter package on other layers.

capacitor. Keep the sense trace short in order

to avoid noise coupling into the node.

Recommendation 8: Keep R_A, C_A, and R_B

close to the VFB pin (see Figures 4 and 8).

The VFB pin is a high-impedance, sensitive

node. Keep the trace to this pin as short as

possible. Whenever possible, connect R_B

directly to the AGND pin instead of going

through the GND plane.

Recommendation 7: The V_OUTsense point

should be just after the last output filter

Thermal Considerations

The Enpirion EN5394QI DC-DC converter is

packaged in an 11 x 8 x 1.85mm 68-pin QFN

package. The QFN package is constructed

with copper lead frames that have exposed

thermal pads. The recommended maximum

junction temperature for continuous operation

is 125°C. Continuous operation above 125°C

will reduce long-term reliability. The device has

a thermal overload protection circuit designed

to shut it off at an approximate junction

temperature value of 150°C.

follows:

T_J= T_C+ (P_D)(θ_JC)

The device case temperature, T_C, is the

temperature at the center of the larger exposed

thermal pad at the bottom of the package.

The device junction-to-ambient and junction-to-

case thermal resistances, θ_JAand θ_JC, are

shown in the Thermal Characteristics table.

The θ_JCis a function of the device and the 68-

pin QFN package design. The θ_JAis a function

of θ_JCand the user’s system design

The silicon is mounted on a copper thermal

pad that is exposed at the bottom of the

package. There is an additional thermal pad in

the corner of the package which provides

another path for heat flow out from the

package. The thermal resistance from the

silicon to the exposed thermal pads is very low.

In order to take advantage of this low

resistance, the exposed thermal pads on the

package should be soldered directly on to a

copper ground pad on layer 1 of the PCB. The

PCB then acts as a heat sink. In order for the

PCB to be an effective heat sink, the device

thermal pads should be coupled to copper

ground planes using multiple vias (refer to

Layout Recommendations section).

parameters

that

include

the

thermal

effectiveness of the customer PCB and airflow.

The θ_JAvalue shown in the Thermal

Characteristics table is for free convection with

the device heat sunk (through the thermal

pads) to a copper plated four-layer PC board

with a full ground and a full power plane

following JEDEC EIJ/JESD 51 Standards. The

θ_JAcan be reduced with the use of forced air

convection. Because of the strong dependence

on the thermal effectiveness of the PCB and

the system design, the actual θ_JAvalue will be

a function of the specific application.

When operating on a board with the θ_JAof the

thermal characteristics table, some thermal

derating is needed to operate all the way up to

maximum output current.

The junction temperature, T_J, is calculated from

the ambient temperature, T_A, the device power

dissipation, P_D, and the device junction-to-

ambient thermal resistance, θ_JAin °C/W:

Figures 9 and 10 show, for a given input

voltage, the maximum output current curves as

a function of ambient temperature and output

voltage. These curves in figures have been

plotted assuming a maximum 125 °C limitation

on the junction temperature at a specific θ_JAfor

the PCB.

T_J= T_A+ (P_D)(θ_JA)

The junction temperature, T_J, can also be

expressed in terms of the device case

temperature, T_C, and the device junction-to-

case thermal resistance, θ_JCin °C/W, as

www.enpirion.com

03738

8/21/2009

Rev:B

EN5394QI

Current Derating Curves, EN5394QI, Vin = 5V

8x11mm QFN, Tjmax = 125°C, Θ-ja = 16°C/W, No Airflow

Current Derating Curves, EN5394QI, Vin = 3.3V

8x11mm QFN, Tjmax = 125°C, Θ-ja = 16°C/W, No Airflow

55.0

65.0

75.0

85.0

55.0

65.0

Ambient Temp, °C

Vout = 1.8V

75.0

85.0

Ambient Temp, °C

Vout = 1.0V

Vout = 1.8V

Vout = 2.5V

Vout=3.3V

Vout = 1.0V

Vout = 2.5V

Figure 10: Maximum I_OUTCurves at V_IN= 5.0V

Figure 9: Maximum I_OUTCurves at V_IN= 3.3V

Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom of Package

Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance,

and in overall foot print. However, they do require some special considerations.

In the assembly process lead frame construction requires that, for mechanical support, some of the

lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.

This results in several small pads being exposed on the package bottom, as shown in Figure 11.

Only the two thermal pads and the perimeter pads are to be mechanically or electrically connected to

the PC board. The PCB top layer under the EN5394QI should be clear of any metal (copper pours,

traces, or vias) except for the two thermal pads. The “grayed-out” area in Figure 11 represents the

area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the

grayed-out area runs the risk of undesirable shorted connections even if it is covered by soldermask.

One exposed pad in the grayed-out area can have V_INmetal under it as noted in Figure 11.

Figure 12 demonstrates the recommended PCB footprint for the EN5394QI. Figure 13 shows the

package dimensions.

V_INcopper covered by

soldermask acceptable

under this exposed pad.

Figure 11: Lead-Frame exposed metal. Grey

area highlights exposed metal that is not to

be mechanically or electrically connected to

the PCB.

www.enpirion.com

03738

8/21/2009

Rev:B

EN5394QI

PCB Footprint and Package Dimensions

Figure 12: Recommended footprint for PCB layout.

Figure 13. Package dimensions.

www.enpirion.com

03738

8/21/2009

Rev:B

EN5394QI

Contact Information

Enpirion, Inc.

Perryville III

53 Frontage Road, Suite 210

Hampton, NJ 08827

USA

Phone: +1-908-894-6000

Fax: +1-908-894-6090

www.enpirion.com

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is

believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may

result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment

used in hazardous environment without the express written authority from Enpirion.

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03738

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Rev:B

EN5394QI相关文章

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EN5394QI产品参数

型号:	EN5394QI
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	ALTERA CORP
包装说明：	HQCCN,
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.73
其他特性：	OPERATES IN ADJUSTABLE MODE FROM 0.6V TO 5.88V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	6.6 V
最小输入电压：	2.375 V
标称输入电压：	5.5 V
JESD-30 代码：	R-XQCC-N70
JESD-609代码：	e3
长度：	11 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	70
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED
封装代码：	HQCCN
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, HEAT SINK/SLUG
峰值回流温度（摄氏度）：	260
座面最大高度：	1.9 mm
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	4400 kHz
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	10
宽度：	8 mm
Base Number Matches：	1

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