EN6360QI各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

EN6360QI

8A Synchronous Highly Integrated DC-DC

PowerSoC

Description

Features

• High Efficiency (Up to 96%)

The EN6360QI is a Power System on a Chip

(PowerSoC) DC to DC converter with an integrated

• Excellent Ripple and EMI Performance

• Up to 8A Continuous Operating Current

• Input Voltage Range (2.5V to 6.6V)

inductor,

PWM

controller,

MOSFETs

and

compensation to provide the smallest solution size in

an 8x11x3mm 68 pin QFN module. It offers high

efficiency, excellent line and load regulation over

temperature and up to the full 8A load range. The

EN6360QI is specifically designed to meet the

precise voltage and fast transient requirements of

high-performance, low-power processor, DSP, FPGA,

memory boards and system level applications in

distributed power architecture. The EN6360QI

features switching frequency synchronization with an

external clock or other EN6360QIs for parallel

operation. Other features include precision enable

threshold, pre-bias monotonic start-up, and

programmable soft-start. The device’s advanced

circuit techniques, ultra high switching frequency, and

proprietary integrated inductor technology deliver

high-quality, ultra compact, non-isolated DC-DC

conversion.

• Frequency Synchronization (Clock or Primary)

• 2% V_OUTAccuracy (Over Line/Load/Temperature)

• Optimized Total Solution Size (190mm²)

• Precision Enable Threshold for Sequencing

• Programmable Soft-Start

• Master/Slave Configuration for Parallel Operation

• Thermal Shutdown, Over-Current, Short Circuit,

and Under-Voltage Protection

• RoHS Compliant, MSL Level 3, 260°C Reflow

Applications

• Point of Load Regulation for Low-Power, ASICs

Multi-Core and Communication Processors, DSPs,

FPGAs and Distributed Power Architectures

The Enpirion integrated inductor solution significantly

helps to reduce noise. The complete power converter

solution enhances productivity by offering greatly

simplified board design, layout and manufacturing

requirements. All Enpirion products are RoHS

• Blade Servers, RAID Storage and LAN/SAN

Adapter Cards, Wireless Base Stations, Industrial

Automation, Test and Measurement, Embedded

Computing, and Printers

compliant and lead-free manufacturing environment • High Efficiency 12V Intermediate Bus Architectures

compatible.

• Beat Frequency/Noise Sensitive Applications

Efficiency vs. Output Current

V_OUT

V_IN

100

90

80

70

60

50

40

30

20

10

0

PVIN

VOUT

VFB

R_A

C_A

ENABLE

2x

F

1206

EN6360QI

2x

22 F

1206

Actual Solution Size

190mm²

AVIN

SS

R₁

CONDITIONS

V_IN= 5.0V

15nF

PGND

VOUT = 3.3V

VOUT = 1.2V

PGND

R_B

FQADJ

AGND

R_FQADJ

0

1

2

3

4

5

6

7

8

OUTPUT CURRENT(A)

Figure 1. Simplified Applications Circuit

Figure 2. Highest Efficiency in Smallest Solution Size

www.enpirion.com

06489

April 16, 2012

Rev: C

EN6360QI

Ordering Information

Part Number

EN6360QI

EN6360QI-E

Package Markings

EN6360QI

Temp Rating (°C)

-40 to +85

Package Description

68-pin (8mm x 11mm x 3mm) QFN T&R

QFN Evaluation Board

Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm

Pin Assignments (Top View)

48

S_IN

BGND

VDDB

NC

1

2

NC

KEEP OUT

47

46

45

3

4

69

PGND

44 NC

43

5

6

PVIN

KEEP OUT

42

41

40

39

38

37

36

35

PVIN

7

8

9

10

11

12

13

14

Figure 3: Pin Out Diagram (Top View)

NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.

However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.

NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically

connected to the PCB. Refer to Figure 11 for details.

NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.

Pin Description

NAME

FUNCTION

1-15, 25,

44-45,

59, 64-68

NO CONNECT: These pins must be soldered to PCB but not electrically connected to each

other or to any external signal, voltage, or ground. These pins may be connected internally.

Failure to follow this guideline may result in device damage.

NC

Regulated converter output. Connect to the load and place output filter capacitor(s) between

these pins and PGND pins 28 to 31.

16-24

VOUT

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

NAME

FUNCTION

NO CONNECT: These pins are internally connected to the common switching node of the

26-27,

62-63

NC(SW) internal MOSFETs. They must be soldered to PCB but not be electrically connected to any

external signal, ground, or voltage. Failure to follow this guideline may result in device damage.

Input and output power ground. Connect these pins to the ground electrode of the input and

28-34

35-43

PGND

output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for

more details.

Input power supply. Connect to input power supply and place input filter capacitor(s) between

these pins and PGND pins 32 to 34.

PVIN

Internal regulated voltage used for the internal control circuitry. Decouple with an optional

0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is

limited.

46

47

VDDB

BGND

Ground for VDDB. Refer to pin 46 description.

Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will

accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S

pin will make this device a Master and the switching frequency will be phase locked to an

external clock. Leave this pin floating if it is not used.

48

S_IN

Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal

switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of

another EN6360QI device for parallel operation. Leave this pin floating if it is not used.

POK is a logic level high when VOUT is within -10% to +20% of the programmed output

voltage (0.9V_{OUT_NOM}≤ V_OUT≤ 1.2V_{OUT_NOM}). This pin has an internal pull-up resistor to AVIN

with a nominal value of 120kΩ.

49

50

51

S_OUT

POK

Device enable pin. A high level or floating this pin enables the device while a low level disables

ENABLE the device. A voltage ramp from another power converter may be applied for precision enable.

Refer to Power Up Sequencing

Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)

52

53

AVIN

at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is

sequencing.

The quiet ground for the control circuits. Connect to the ground plane with a via right next to the

pin.

AGND

Ternary (three states) input pin. Floating this pin disables parallel operation. A low level

configures the device as Master and a high level configures the device as a Slave. A R_EXT

resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional

Description section for R_EXTvalues. Also refer to S_IN and S_OUT pin descriptions.

This is the external feedback input pin. A resistor divider connects from the output to AGND.

The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (C_A) and

resistor (R1) are required parallel to the upper feedback resistor (R_A). The output voltage

regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB

floating.

54

55

M/S

VFB

56

57

EAOUT

SS

Error amplifier output. Allows for customization of the control loop. May be left floating.

A soft-start capacitor is connected between this pin and AGND. The value of the capacitor

controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.

This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect

VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.

Frequency adjust pin. This pin must have a resistor to AGND which sets the free running

frequency of the internal oscillator.

58

60

VSENSE

FQADJ

Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up

under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is

pulled high internally. Enable pre-bias feature is not available for parallel operations.

Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-

sinking purposes. Refer to Layout Recommendation section.

61

69

EN_PB

PGND

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating

conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability.

PARAMETER

SYMBOL

MIN

-0.3

MAX

7.0

UNITS

Voltages on : PVIN, AVIN, VOUT

V

Voltages on: EN, POK, M/S

V_IN+0.3

Voltages on: VFB, EXTREF, EAOUT, SS, S_IN, S_OUT, FQADJ

Storage Temperature Range

-0.3

-65

2.5

150

260

2000

500

V

°C

V

T_STG

Maximum Operating Junction Temperature

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A

ESD Rating (based on Human Body Model)

ESD Rating (based on CDM)

T_{J-ABS Max}

V

Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Voltage Range

V_IN

2.5

6.6

V

Output Voltage Range (Note 1)

Output Current

V_OUT

I_OUT

T_A

0.60

V_IN– V_DO

8

V

A

Operating Ambient Temperature

Operating Junction Temperature

-40

+85

°C

T_J

+125

Thermal Characteristics

PARAMETER

SYMBOL

θ_JA

TYP

UNITS

Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)

15

1.0

150

20

°C/W

Thermal Resistance: Junction to Case (0 LFM)

Thermal Shutdown

°C/W

°C

θ_JC

T_SD

Thermal Shutdown Hysteresis

T_SDH

°C

Note 1: V_DO(dropout voltage) is defined as (I_LOADx Dropout Resistance). Please refer to Electrical Characteristics Table.

Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for

high thermal conductivity boards.

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Electrical Characteristics

NOTE: V_IN=6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.

Typical values are at T_A= 25°C.

PARAMETER

Operating Input

Voltage

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V_IN

2.5

6.6

V

Internal Voltage Reference at:

V_IN= 5V, ILOAD = 0, T_A= 25°C

VFB Pin Voltage

V_VFB

0.594

0.588

-0.2

0.600

0.606

0.612

0.2

V

VFB Pin Voltage

2.5V ≤ V_IN≤ 6.6V

0A ≤ I_LOAD≤ 8A

V_VFB

(Line, Load and

Temperature)

VFB Pin Input Leakage

Current

I_VFB

VFB Pin Input Leakage Current

µA

mA

V

Shut-Down Supply

Current

Power Supply Current with

ENABLE=0

I_S

1.5

2.2

2.1

Under Voltage Lock-

out – V_INRising

Voltage Above Which UVLO is Not

Asserted

V_UVLOR

V_UVLOF

Under Voltage Lock-

out – V_INFalling

Voltage Below Which UVLO is

Asserted

V

Drop Out Voltage

V

_INMIN– V_OUTat Full Load

400

50

800

100

8

mV

mΩ

A

V_DO

R_DO

Drop Out Resistance

Input to Output Resistance

Continuous Output

Current

I_{OUT_SRC}

0

Over Current Trip

Level

I_OCP

F_SW

Sourcing Current

16

A

Switching Frequency

0.9

1.2

1.5

MHz

R_FADJ= 4.42 kΩ, V_IN= 5V

External SYNC Clock

Frequency Lock

Range

SYNC Clock Input Frequency

Range

F_{PLL_LOCK}

0.9*F_sw

F_sw

1.1*F_sw

MHz

S_IN Clock Amplitude

– Low

V_{S_IN_LO}

SYNC Clock Logic Low

SYNC Clock Logic High

M/S Pin Float or Low

M/S Pin High

0

0.8

2.5

80

V

S_IN Clock Amplitude

– High

V_{S_IN_HI}

1.8

20

10

S_IN Clock Duty Cycle

(PLL)

DC_{S_INPLL}

DC_{S_INPWM}

%

S_IN Clock Duty Cycle

(PWM)

90

Allowable Pre-bias as a Fraction of

Programmed Output Voltage for

Monotonic start up. Minimum Pre-

bias Voltage = 300mV.

Pre-Bias Level

V_PB

20

75

%

Allowable Non-monotonicity Under

Pre-bias Startup

Non-Monotonicity

V_{PB_NM}

100

mV

%

Range of Output Voltage as a

Fraction of Programmed Value

When P_OKis Asserted. (Note 3)

V_OUTRange for P_OK

High

=

90

120

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

UNITS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

Falling Edge Deglitch Delay After

Output Crossing 90% level.

F_SW=1.2 MHz

P_OKDeglitch Delay

213

µs

V_POKLogic Low level

V_POKLogic high level

With 4mA Current Sink into P_OKPin

0.4

V

V_IN

94

POK Internal pull-up

resistor

kΩ

With 2 to 4 Converters in Parallel,

the Difference Between Nominal

and Actual Current Levels.

Current Balance

+/-10

%

∆I_OUT

∆V_IN<50mV; R_TRACE< 10 mΩ,

I_load= # Converter * I_MAX

t_RISE[ms] = C_SS[nF] x 0.065;

10nF ≤ C_SS≤ 30nF;

(Note 5 and Note 6)

∆T_RISE

V_OUTRise Time

Accuracy

-25

+25

%

(Note 4)

ENABLE Logic High

ENABLE Logic Low

ENABLE Pin Current

V_{ENABLE_HIGH}2.5V ≤ V_IN≤ 6.6V;

1.2

0

V_IN

0.8

V

V_{ENABLE_LOW}

I_EN

VIN = 6.6V

50

µA

M/S Ternary Pin Logic

Low

V_T-LOW

Tie M/S Pin to GND

0

0.7

1.4

V

M/S Ternary Pin Logic

Float

V_T-FLOAT

V_T-HIGH

M/S Pin is Open

1.1

1.8

M/S Ternary Pin Logic

Hi (Note 7)

Pull Up to VIN through an external

resistor R_EXT. Refer to Figure 7.

2.5V ≤ V_IN≤ 4V, R_EXT= 15k

4V < V_IN≤ 6.6V, R_EXT= 51k

117

88

Ternary Pin Input

Current

I_TERN

µA

Binary Pin Logic Low

Threshold

V_B-LOW

V_B-HIGH

ENABLE, S_IN

0.8

V

Binary Pin Logic High

Threshold

1.8

2.0

S_OUT Low Level

S_OUT High Level

V_{S_OUT_LOW}

V_{S_OUT_HIGH}

0.4

V

Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing

the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels

are nominal values. Expect these thresholds to vary by 3%.

Note 4: Parameter not production tested but is guaranteed by design.

Note 5: Rise time calculation begins when AVIN > V_UVLOand ENABLE = HIGH.

Note 6: V_OUTRise Time Accuracy does not include soft-start capacitor tolerance..

Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to

VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.

Enpirion Confidential

www.enpirion.com, Page 6

06489

April 16, 2012

Rev: C

EN6360QI

Typical Performance Curves

Efficiency vs. Output Current

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

VOUT = 2.5V

VOUT = 3.3V

VOUT = 2.5V

VOUT = 1.8V

VOUT = 1.2V

VOUT = 1.0V

50

VOUT = 1.8V

40

30

20

10

0

VOUT = 1.2V

VOUT = 1.0V

CONDITIONS

V_IN= 3.3V

CONDITIONS

V_IN= 5.0V

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

OUTPUT CURRENT(A)

Output Voltage vs. Output Current

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

VOUT = 1.8V

VOUT = 1.0V

CONDITIONS

V_IN= 3.3V

CONDITIONS

V_IN= 3.3V

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

OUTPUT CURRENT(A)

Output Voltage vs. Output Current

3.320

3.315

3.310

3.305

3.300

3.295

3.290

3.285

3.280

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

VOUT = 3.3V

VOUT = 1.8V

CONDITIONS

V_IN= 5.0V

CONDITIONS

V_IN= 5.0V

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

OUTPUT CURRENT(A)

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Typical Performance Curves (Continued)

Output Voltage vs. Input Voltage

Output Voltage vs. Output Current

1.820

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

VOUT = 1.0V

CONDITIONS

Load = 0A

CONDITIONS

V_IN= 5.0V

2.4

3

3.6

4.2

4.8

5.4

6

6.6

0

1

2

3

4

5

6

7

8

6.6

85

INPUTVOLTAGE (V)

OUTPUT CURRENT(A)

Output Voltage vs. Input Voltage

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

CONDITIONS

Load = 4A

CONDITIONS

Load = 8A

2.4

3

3.6

4.2

4.8

5.4

6

2.4

3

3.6

4.2

4.8

5.4

6

6.6

INPUTVOLTAGE (V)

Output Voltage vs. Temperature

1.802

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

1.802

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

LOAD = 0A

LOAD = 2A

LOAD = 4A

LOAD = 6A

LOAD = 8A

LOAD = 0A

LOAD = 2A

LOAD = 4A

LOAD = 6A

LOAD = 8A

CONDITIONS

V_IN= 6.6V

V_{OUT_NOM}=1.8V

CONDITIONS

V_IN= 5V

V_{OUT_NOM}=1.8V

-40

-15

10

35

60

-40

-15

10

35

60

85

AMBIENT TEMPERATURE ( C)

Enpirion Confidential

www.enpirion.com, Page 8

06489

April 16, 2012

Rev: C

EN6360QI

Typical Performance Curves (Continued)

Output Voltage vs. Temperature

1.802

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

1.802

LOAD = 0A

LOAD = 2A

LOAD = 4A

LOAD = 6A

LOAD = 8A

LOAD = 0A

LOAD = 2A

LOAD = 4A

LOAD = 6A

LOAD = 8A

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

CONDITIONS

V_IN= 3.6V

V_{OUT_NOM}=1.8V

CONDITIONS

V_IN= 2.5V

V_{OUT_NOM}=1.8V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

AMBIENT TEMPERATURE ( C)

No Thermal Derating

10

9

8

7

6

5

4

3

2

1

10

9

8

7

6

5

4

3

COCNonDdITitIiOonNsS

V_IV_{N I}=_N=5.05V.0V

V_OV_UOTU=_T3=.3V.3V

COCNonDdITitIiOonNsS

V_IV_{N I}=_N=5.05V.0V

V_OV_UOTU=_T1=.03V.3V

2

1

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

AMBIENT TEMPERATURE( C)

EMI Performance (Vertical Scan)

EMI Performance (Horizontal Scan)

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

CONDITIONS

V_IN= 5.0V

V_{OUT_NOM}=1.5V

LOAD = 0.2Ω

CONDITIONS

V_IN= 5.0V

V_{OUT_NOM}= 1.5V

LOAD = 0.2Ω

CISPR 22 Class B 3m

30

300

30

300

FREQUENCY (MHz)

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Typical Parallel Performance Curves

Parallel Efficiency

vs. Output Current

Parallel Efficiency

vs. Output Current

100

90

80

70

60

50

40

30

20

10

0

90

80

70

VOUT = 3.3V

VOUT = 2.5V

VOUT = 1.8V

60

50

40

30

20

10

0

VOUT = 2.5V

VOUT = 1.8V

VOUT = 1.2V

VOUT = 1.0V

CONDITIONS

V_IN= 3.3V

2x EN6360QI

CONDITIONS

V_IN= 5.0V

2x EN6360QI

VOUT = 1.2V

VOUT = 1.0V

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

OUTPUT CURRENT(A)

Parallel Current Share Mis-Match

Parallel Current Share Breakdown

5

10

9

8

7

6

5

4

3

2

1

0

4

3

Mis-match (%) = (I_Master - I_Slave ) / I_Average x 100

Master Device

Slave Device

2

1

0

-1

-2

-3

-4

-5

CONDITIONS

EN6360QI

V_IN= 5V

CONDITIONS

EN6360QI

_IN= 5V

V_OUT= 3.3V

V

V_OUT= 3.3V

2

4

6

8

10

12

14

2

4

6

8

10

12

14

OUTPUT CURRENT(A)

TOTAL OUTPUT CURRENT(A)

Parallel Output Voltage

vs. Output Current

Parallel Output Voltage

vs. Output Current

3.4

3.38

3.36

3.34

3.32

3.3

1.1

1.08

1.06

1.04

1.02

1

VOUT = 1.0V

VOUT = 3.3V

3.28

3.26

3.24

3.22

3.2

0.98

0.96

0.94

0.92

0.9

CONDITIONS

V_IN= 5.0V

2x EN6360QI

CONDITIONS

V_IN= 3.3V

2x EN6360QI

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

OUTPUT CURRENT(A)

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April 16, 2012

Rev: C

EN6360QI

Typical Performance Characteristics

Output Ripple at 20MHz Bandwidth

Output Ripple at 500MHz Bandwidth

CONDITIONS

VIN = 5V

CONDITIONS

VIN = 5V

VOUT = 1V

IOUT = 8A

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

VOUT = 1V

IOUT = 8A

CIN = 2 x 22µF (1206)

VOUT

(AC Coupled)

VOUT

(AC Coupled)

COUT = 2 x 47 µF (1206)

Output Ripple at 20MHz Bandwidth

Output Ripple at 500MHz Bandwidth

CONDITIONS

VIN = 5V

CONDITIONS

VIN = 5V

VOUT = 2.4V

IOUT = 8A

CIN = 2 x 22µF (1206)

VOUT

(AC Coupled)

IOUT = 8A

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

VOUT

(AC Coupled)

COUT = 2 x 47 µF (1206)

Enable Power Up/Down

ENABLE

CONDITIONS

VIN = 5V

CONDITIONS

VIN = 5V

VOUT = 2.4V

IOUT = 8A

Css = 15nF

VOUT

VOUT = 1.0V

IOUT = 8A

Css = 15nF

VOUT

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

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EN6360QI

Typical Performance Characteristics (Continued)

Load Transient from 0 to 8A

Enable/Disable withPOK

CONDITIONS

VIN = 6.2V

ENABLE

VOUT = 1.5V

CIN = 2 x 22µF (1206)

COUT = 2 x 47µF (1206)

VOUT

POK

VOUT

(AC Coupled)

CONDITIONS

VIN = 5V, VOUT = 1.0V

LOAD = 5A, Css = 15nF

LOAD

Parallel Operation Current Sharing

Parallel Operation SW Waveforms

MASTER VSW

TOTALLOAD =18A

SLAVE 2 VSW

SLAVE 1 VSW

MASTER LOAD =6A

SLAVE 2 LOAD = 6A

CONDITIONS

COMBINEDLOAD(18A)

CONDITIONS

VIN= 5V

SLAVE 1 LOAD = 6A

VIN = 5V

VOUT = 1.8V

LOAD = 18A

VOUT = 1.8V

LOAD= 18A

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Rev: C

EN6360QI

Functional Block Diagram

Figure 4: Functional Block Diagram

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06489

April 16, 2012

Rev: C

EN6360QI

Functional Description

capacitor between this pin and AGND provides a

soft-start function to limit in-rush current during

device power-up. When the part is initially powered

up, the output voltage is gradually ramped to its

final value. The gradual output ramp is achieved by

increasing the reference voltage to the error

amplifier. A constant current flowing into the soft-

start capacitor provides the reference voltage ramp.

When the voltage on the soft-start capacitor

reaches 0.60V, the output has reached its

programmed voltage. Once the output voltage has

reached nominal voltage the soft-start capacitor will

continue to charge to 1.5V (Typical). The output

rise time can be controlled by the choice of soft-

start capacitor value.

The EN6360QI is a synchronous, programmable

buck power supply with integrated power MOSFET

switches and integrated inductor. The switching

supply uses voltage mode control and a low noise

PWM topology. This provides superior impedance

matching to ICs processed in sub 90nm process

technologies. The nominal input voltage range is

2.5 - 6.6 volts. The output voltage is programmed

using an external resistor divider network. The

feedback control loop incorporates a type IV

voltage mode control design. Type IV voltage mode

control maximizes control loop bandwidth and

maintains excellent phase margin to improve

transient performance. The EN6360QI is designed

to support up to 8A continuous output current

operation. The operating switching frequency is

between 0.9MHz and 1.5MHz and enables the use

of small-size input and output capacitors.

The rise time is defined as the time from when the

ENABLE signal crosses the threshold and the input

voltage crosses the upper UVLO threshold to the

time when the output voltage reaches 95% of the

programmed value. The rise time (t_RISE) is given by

the following equation:

The power supply has the following features:

•

Precision Enable Threshold

Soft-Start

t_RISE[ms] = C_ss[nF] x 0.065

Pre-bias Start-Up

The rise time (t_RISE) is in milliseconds and the soft-

start capacitor (C_SS) is in nano-Farads. The soft-

start capacitor should be between 10nF and 100nF.

Resistor Programmable Switching Frequency

Phase-Lock Frequency Synchronization

Parallel Operation

Pre-Bias Start-up

The EN6360QI supports startup into a pre-biased

load. A proprietary circuit ensures the output

voltage rises up from the pre-bias value to the

programmed output voltage. Start-up is guaranteed

to be monotonic for pre-bias voltages in the range

of 20% to 75% of the programmed output voltage

with a minimum pre-bias voltage of 300mV. Outside

of the 20% to 75% range, the output voltage rise

will not be monotonic. The Pre-Bias feature is

automatically engaged with an internal pull-up

resistor. For this feature to work properly, V_INmust

be ramped up prior to ENABLE turning on the

device. Tie VSENSE to VOUT if Pre-Bias is used.

Tie EN_PB to ground and leave VSENSE floating

to disable the Pre-Bias feature. Pre-Bias is

supported for external clock synchronization, but

not supported for parallel operations.

Power OK

Over-Current/Short Circuit Protection

Thermal Shutdown with Hysteresis

Under-Voltage Lockout

Precision Enable

The ENABLE threshold is a precision analog

voltage rather than a digital logic threshold. A

precision voltage reference and a comparator

circuit are kept powered up even when ENABLE is

de-asserted. The narrow voltage gap between

ENABLE Logic Low and ENABLE Logic High

allows the device to turn on at a precise enable

voltage level. With the enable threshold pinpointed,

a proper choice of soft-start capacitor helps to

accurately sequence multiple power supplies in a

system as desired. There is an ENABLE lockout

time of 2ms that prevents the device from re-

enabling immediately after it is disabled.

Resistor Programmable Frequency

The operation of the EN6360QI can be optimized

by a proper choice of the R_FQADJresistor. The

frequency can be tuned to optimize dynamic

performance and efficiency. Refer to Table 1 for

recommended R_FQADJvalues.

Soft-Start

The SS pin in conjunction with a small external

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06489

April 16, 2012

Rev: C

EN6360QI

together with the Master by connecting the S_OUT

of the Master to the S_IN of all other Slave devices.

Refer to Figure 5 for details.

Table 1: Recommended R_FQADJ(kΩ)

Careful attention is needed in the layout for parallel

operation. The VIN, VOUT and GND of the

paralleled devices should have low impedance

connections between each other. Maximize the

amount of copper used to connect these pins and

use as many vias as possible when using multiple

layers. Place the Master device between all other

Slaves and closest to the point of load.

V_OUT

0.8V 1.2V 1.5V 1.8V 2.5V 3.3V

3.57 3.57 4.99 5.49 5.49 NA

V_IN

3.3V 10%

5.0V 10%

6.0V 10%

3.57 3.57 4.99 5.49 5.49 4.99

3.57 3.57 4.99 5.49 5.49 5.49

Phase-Lock Operation:

The EN6360QI can be phase-locked to an external

clock signal to synchronize its switching frequency.

The M/S pin can be left floating or pulled to ground

to allow the device to synchronize with an external

clock signal using the S_IN pin. When a clock

signal is present at S_IN, an activity detector

recognizes the presence of the clock signal and the

internal oscillator phase locks to the external clock.

The external clock could be the system clock or the

output of another EN6360QI. The phase locked

clock is then output at S_OUT. Refer to Table 2 for

recommended clock frequencies.

Table 2: Recommended Clock fsw (MHz) 10%

V_OUT

0.8V 1.2V 1.5V 1.8V 2.5V 3.3V

V_IN

1.15 1.15 1.30 1.35 1.35

NA

3.3V 10%

5.0V 10%

6.0V 10%

1.15 1.15 1.30 1.35 1.35 1.30

1.15 1.15 1.30 1.35 1.35 1.35

Master / Slave (Parallel) Operation and

Frequency Synchronization

Multiple EN6360QI devices may be connected in a

Master/Slave configuration to handle larger load

currents. The device is placed in Master mode by

pulling the M/S pin low or in Slave mode by pulling

M/S pin high. When the M/S pin is in float state,

parallel operation is not possible. In Master

mode, a version of the internal switching PWM

signal is output on the S_OUT pin. This PWM

signal from the Master is fed to the Slave device at

its S_IN pin. The Slave device acts like an

extension of the power FETs in the Master and

inherits the PWM frequency and duty cycle. The

inductor in the Slave prevents crow-bar currents

from Master to Slave due to timing delays. The

Master device’s switching clock may be phase-

locked to an external clock source or another

EN6360QI to move the entire parallel operation

frequency away from sensitive frequencies. The

feedback network for the Slave device may be left

open. Additional Slave devices may be paralleled

Figure 5: Master/Slave Parallel Operation Diagram

POK Operation

The POK signals that the output voltage is within

the specified range. The POK signal is asserted

high when the rising output voltage crosses 92%

(nominal) of the programmed output voltage. If the

output voltage falls outside the range of 90% to

120%, POK remains asserted for the de-glitch time

(213µs at 1.2MHz). After the de-glitch time, POK is

de-asserted. POK is also de-asserted if the output

voltage exceeds 120% of the programmed output

voltage.

Over Current Protection

The current limit function is achieved by sensing

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

the current flowing through a sense P-FET. When

the sensed current exceeds the current limit, both

power FETs are turned off for the rest of the

switching cycle. If the over-current condition is

removed, the over-current protection circuit will re-

enable PWM operation. If the over-current condition

persists, the circuit will continue to protect the load.

The OCP trip point is nominally set as specified in

the Electrical Characteristics table. In the event the

OCP circuit trips consistently in normal operation,

the device enters a hiccup mode. The device is

disabled for 27µs and restarted with a normal soft-

start. This cycle can continue indefinitely as long as

the over current condition persists.

Thermal Overload Protection

Temperature sensing circuits in the controller will

disable operation when the junction temperature

exceeds approximately 150ºC. Once the junction

temperature drops by approx 20ºC, the converter

will re-start with a normal soft-start.

Input Under-Voltage Lock-Out

When the input voltage is below a required voltage

level (V_UVHI) for normal operation, the converter

switching is inhibited. The lock-out threshold has

hysteresis to prevent chatter. Thus when the device

is operating normally, the input voltage has to fall

below the lower threshold (V_UVLO) for the device to

stop switching.

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Application Information

Calculate the external feedback and compensation

network values with the equations below.

Output Voltage Programming and loop

Compensation

The EN6360QI output voltage is programmed using

a simple resistor divider network. A phase lead

capacitor plus a resistor are required for stabilizing

the loop. Figure 6 shows the required components

and the equations to calculate their values.

R_A[Ω] = 48,400 x V_IN[V]

*Round R_Aup to closest standard value

R_B[Ω] = (V_FBx R_A) / (V_OUT– V_FB) [V]

V_FB= 0.6V nominal

*Round R_Bto closest standard value

The EN6360QI output voltage is determined by the

voltage presented at the VFB pin. This voltage is

set by way of a resistor divider between VOUT and

AGND with the midpoint going to VFB.

C_A[F] = 3.83 x 10^-6/ R_A[Ω]

*Round C_Adown to closest standard value

The EN6360QI uses a type IV compensation

network. Most of this network is integrated.

However, a phase lead capacitor and a resistor are

required in parallel with upper resistor of the

external feedback network (Refer to Figure 6). Total

compensation is optimized for use with two 47µF

output capacitance and will result in a wide loop

bandwidth and excellent load transient performance

for most applications. Additional capacitance may

be placed beyond the voltage sensing point outside

the control loop. Voltage mode operation provides

high noise immunity at light load. Furthermore,

voltage mode control provides superior impedance

matching to ICs processed in sub 90nm

technologies.

R1 = 15kΩ

The feedback resistor network should be sensed at

the last output capacitor close to the device. Keep

the trace to VFB pin as short as possible.

Whenever possible, connect R_Bdirectly to the

AGND pin instead of going through the GND plane.

Input Capacitor Selection

The EN6360QI has been optimized for use with two

1206 22µF input capacitors. Low ESR ceramic

capacitors are required with X5R or X7R dielectric

formulation.

Y5V

or

equivalent

dielectric

formulations must not be used as these lose

capacitance with frequency, temperature and bias

voltage.

In some cases modifications to the compensation

or output capacitance may be required to optimize

device performance such as transient response,

ripple, or hold-up time. The EN6360QI provides the

capability to modify the control loop response to

allow for customization for such applications. For

more information, contact Enpirion Applications

Engineering support.

In some applications, lower value ceramic

capacitors may be needed in parallel with the larger

capacitors in order to provide high frequency

decoupling. The capacitors shown in the table

below are typical input capacitors. Other capacitors

with similar characteristics may also be used.

Table 3: Recommended Input Capacitors

Description

MFG

P/N

22µF, 10V, 20%

X5R, 1206

(2 capacitors needed)

Murata

GRM31CR61A226ME19L

Taiyo Yuden

LMK316BJ226ML-T

Output Capacitor Selection

The EN6360QI has been optimized for use with two

1206 47µF output capacitors. Low ESR, X5R or

X7R ceramic capacitors are recommended as the

primary choice. Y5V or equivalent dielectric

formulations must not be used as these lose

capacitance with frequency, temperature and bias

voltage.

The

capacitors

shown

in

the

Figure 6: External Feedback/Compensation Network

Recommended Output Capacitors table are typical

output capacitors. Other capacitors with similar

characteristics may also be used. Additional bulk

The feedback and compensation network values

depend on the input voltage and output voltage.

Enpirion Confidential

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Rev: C

EN6360QI

Table 5: Recommended R_EXTResistor

capacitance from 100µF to 1000µF may be placed

beyond the voltage sensing point outside the

control loop. This additional capacitance should

have a minimum ESR of 6mΩ to ensure stable

operation. Most tantalum capacitors will have more

than 6mΩ of ESR and may be used without special

care. Adding distance in layout may help increase

the ESR between the feedback sense point and the

bulk capacitors.

V_IN(V)

I_MAX(µA)

R_EXT(kΩ)

2.5 – 4.0

4.0 – 6.6

117

88

15

51

Table 4: Recommended Output Capacitors

Description

47µF, 10V, 20%

X5R, 1206

MFG

P/N

Taiyo Yuden

LMK316BJ476ML-T

(2 capacitors needed)

47µF, 6.3V, 20%

X5R, 1206

(2 capacitors needed)

10µF, 6.3V, 10%

X7R, 0805

Murata

Taiyo Yuden

Murata

GRM31CR60J476ME19L

JMK316BJ476ML-T

GRM21BR70J106KE76L

(Optional 1 capacitor in

parallel with 2x47µF)

Taiyo Yuden

JMK212B7106KG-T

Output ripple voltage is primarily determined by the

aggregate output capacitor impedance. Placing

multiple capacitors in parallel reduces the

impedance and hence will result in lower ripple

voltage.

Figure 7: Selection of R_EXTto Connect M/S pin to V_IN

Table 6: M/S (Master/Slave) Pin States

1

=

+

Z_TotalZ₁Z₂

+...+

M/S Pin

Function

Z_n

M/S pin is pulled to ground directly. This is

the Master mode. Switching PWM phase

will lock onto S_IN external clock if a signal

is available. S_OUT outputs a version of

the internal switching PWM signal.

Low

Table 5: Typical Ripple Voltages

(0V to 0.7V)

Output Capacitor

Configuration

Typical Output Ripple (mVp-p)

M/S pin is left floating. Parallel operation is

not feasible. Switching PWM phase will

lock onto S_IN external clock if a signal is

available. S_OUT outputs a version of the

internal switching PWM signal.

2 x 47 µF

<10mV

Float

^†20 MHz bandwidth limit measured on Evaluation Board

(1.1V to 1.4V)

M/S - Ternary Pin

M/S pin is pulled to VIN with R_EXT. This is

the Slave mode. The S_IN signal of the

Slave should connect to the S_OUT of the

Master device. This signal synchronizes

the switching frequency and duty cycle of

the Master to the Slave device.

M/S is a ternary pin. This pin can assume 3 states

– A low state (0V to 0.7V), a high state (1.8V to

VIN) and a float state (1.1V to 1.4V). Device

operation is controlled by the state of the pin. The

pins may be pulled to ground or left floating without

any special care. When pulling high to VIN, a series

resistor is recommended. The resistor value may

be optimized to reduce the current drawn by the

pin. The resistance should not be too high as in that

case the pin may not recognize the high state. The

recommend resistance (R_EXT) value is given in the

following table.

High

(>1.8V)

Power-Up Sequencing

During power-up, ENABLE should not be asserted

before PVIN, and PVIN should not be asserted

before AVIN. Tying all three pins together meets

these requirements.

Technical Suport

Contact Enpirion Applications for additional support

of

regarding

(techsupport@enpirion.com).

the

use

this

product

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Thermal Considerations

Thermal considerations are important power supply

design facts that cannot be avoided in the real

world. Whenever there are power losses in a

system, the heat that is generated by the power

dissipation needs to be accounted for. The Enpirion

PowerSoC helps alleviate some of those concerns.

For V_IN= 5V, V_OUT= 3.3V at 8A, η ≈ 94%

η = P_OUT/ P_IN= 94% = 0.94

P_IN= P_OUT/ η

P_IN≈ 26.4W / 0.94 ≈ 28.085W

The power dissipation (P_D) is the power loss in the

system and can be calculated by subtracting the

output power from the input power.

The Enpirion EN6360QI DC-DC converter is

packaged in an 8x11x3mm 68-pin QFN package.

The QFN package is constructed with copper lead

frames that have exposed thermal pads. The

exposed thermal pad on the package should be

soldered directly on to a copper ground pad on the

printed circuit board (PCB) to act as a heat sink.

The recommended maximum junction temperature

for continuous operation is 125°C. Continuous

operation above 125°C may reduce long-term

reliability. The device has a thermal overload

protection circuit designed to turn off the device at

an approximate junction temperature value of

150°C.

P_D= P_IN– P_OUT

≈ 28.085W – 26.4W ≈ 1.685W

With the power dissipation known, the temperature

rise in the device may be estimated based on the

theta JA value (θ_JA). The θ_JAparameter estimates

how much the temperature will rise in the device for

every watt of power dissipation. The EN6360QI has

a θ_JAvalue of 15 ºC/W without airflow.

Determine the change in temperature (∆T) based

on P_Dand θ_JA.

∆T = P_Dx θ_JA

The EN6360QI is guaranteed to support the full 8A

output current up to 85°C ambient temperature.

The following example and calculations illustrate

the thermal performance of the EN6360QI.

∆T ≈ 1.685W x 15°C/W = 25.28°C ≈ 25.3°C

The junction temperature (T_J) of the device is

approximately the ambient temperature (T_A) plus

the change in temperature. We assume the initial

ambient temperature to be 25°C.

Example:

V_IN= 5V

T_J= T_A+ ∆T

V_OUT= 3.3V

T_J≈ 25°C + 25.3°C ≈ 50.3°C

I_OUT= 8A

With 1.685W dissipated into the device, the T_Jwill

be 50.3°C.

First calculate the output power.

P_OUT= 3.3V x 8A = 26.4W

The maximum operating junction temperature

(T_JMAX) of the device is 125°C, so the device can

operate at a higher ambient temperature. The

maximum ambient temperature (T_AMAX) allowed can

be calculated.

Next, determine the input power based on the

efficiency (η) shown in Figure 8.

Efficiency vs. Output Current

100

90

T_AMAX= T_JMAX– P_Dx θ_JA

94%

80

≈ 125°C – 25.3°C ≈ 99.7°C

70

60

50

40

30

The ambient temperature can actually rise by

another 74.7°C, bringing it to 99.7°C before the

device will reach T_JMAX. This indicates that the

EN6360QI can support the full 8A output current

range up to approximately 99.7°C ambient

temperature given the input and output voltage

conditions. This allows the EN6360QI to guarantee

full 8A output current capability at 85°C with room

for margin. Note that the efficiency will be slightly

lower at higher temperatures and this estimate will

be slightly lower.

CONDITIONS

V_IN= 5.0V

20

10

0

VOUT = 3.3V

0

1

2

3

4

5

6

7

8

OUTPUT CURRENT(A)

Figure 8: Efficiency vs. Output Current

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EN6360QI

Engineering Schematic

Figure 9: Engineering Schematic with Engineering Notes

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06489

April 16, 2012

Rev: C

EN6360QI

Layout Recommendation

Recommendation 4: The thermal pad underneath

the component must be connected to the system

ground plane through as many vias as possible.

The drill diameter of the vias should be 0.33mm,

and the vias must have at least 1 oz. copper plating

on the inside wall, making the finished hole size

around 0.20-0.26mm. Do not use thermal reliefs or

spokes to connect the vias to the ground plane.

This connection provides the path for heat

dissipation from the converter.

Recommendation 5: Multiple small vias (the same

size as the thermal vias discussed in

recommendation 4) should be used to connect

ground terminal of the input capacitor and output

capacitors to the system ground plane. It is

preferred to put these vias along the edge of the

GND copper closest to the +V copper. These vias

connect the input/output filter capacitors to the

GND plane, and help reduce parasitic inductances

in the input and output current loops.

Recommendation 6: AVIN is the power supply for

the small-signal control circuits. It should be

connected to the input voltage at a quiet point. In

Figure 10 this connection is made at the input

capacitor.

Figure 10: Top Layout with Critical Components Only

(Top View). See Figure 9 for corresponding schematic.

This layout only shows the critical components and

top layer traces for minimum footprint in single-

supply mode with ENABLE tied to AVIN. Alternate

circuit configurations & other low-power pins need

to be connected and routed according to customer

application. Please see the Gerber files at

www.enpirion.com for details on all layers.

Recommendation 7: The layer 1 metal under the

device must not be more than shown in Figure 10.

Refer to the section regarding Exposed Metal on

Bottom of Package. As with any switch-mode

DC/DC converter, try not to run sensitive signal or

control lines underneath the converter package on

other layers.

Recommendation 1: Input and output filter

capacitors should be placed on the same side of

the PCB, and as close to the EN6360QI package

as possible. They should be connected to the

device with very short and wide traces. Do not use

thermal reliefs or spokes when connecting the

capacitor pads to the respective nodes. The +V and

GND traces between the capacitors and the

EN6360QI should be as close to each other as

possible so that the gap between the two nodes is

minimized, even under the capacitors.

Recommendation 8: The V_OUTsense point should

be just after the last output filter capacitor. Keep the

sense trace short in order to avoid noise coupling

into the node.

Recommendation 9: Keep R_A, C_A, R_B, and R₁

close to the VFB pin (Refer to Figure 10). The VFB

pin is a high-impedance, sensitive node. Keep the

trace to this pin as short as possible. Whenever

possible, connect R_Bdirectly to the AGND pin

instead of going through the GND plane.

Recommendation 2: The PGND connections for

the input and output capacitors on layer 1 need to

have a slit between them in order to provide some

separation between input and output current loops.

Recommendation 10: Follow all the layout

recommendations as close as possible to optimize

performance. Enpirion provides schematic and

layout reviews for all customer designs. Please

contact local Sales Representatives for references

to Enpirion Applications Engineering support.

Recommendation 3: The system ground plane

should be the first layer immediately below the

surface layer. This ground plane should be

continuous and un-interrupted below the converter

and the input/output capacitors.

Enpirion Confidential

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06489

April 16, 2012

Rev: C

EN6360QI

Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom of Package

Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in

overall foot print. However, they do require some special considerations.

In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame

cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several

small pads being exposed on the bottom of the package, as shown in Figure 11.

Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.

The PCB top layer under the EN6360QI should be clear of any metal (copper pours, traces, or vias) except for

the thermal pad. The “shaded-out” area in Figure 11 represents the area that should be clear of any metal on

the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted

connections even if it is covered by soldermask.

The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from

causing bridging between adjacent pins or other exposed metal under the package. Please consult the

Enpirion Manufacturing Application Note for more details and recommendations.

Figure 11: Lead-Frame exposed metal (Bottom View)

Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.

Enpirion Confidential

www.enpirion.com, Page 22

06489

April 16, 2012

Rev: C

EN6360QI

Recommended PCB Footprint

Figure 12: EN6360QI PCB Footprint (Top View)

Enpirion Confidential

www.enpirion.com, Page 23

06489

April 16, 2012

Rev: C

EN6360QI

Package and Mechanical

Figure 13: EN6360QI Package Dimensions (Bottom View)

Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm

Contact Information

Enpirion, Inc.

Perryville III Corporate Park

53 Frontage Road - Suite 210

Hampton, NJ 08827 USA

Phone: 1.908.894.6000

Fax: 1.908.894.6090

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is

believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may

result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment

used in hazardous environment without the express written authority from Enpirion

Enpirion Confidential

www.enpirion.com, Page 24

06489

April 16, 2012

Rev: C

型号:	EN71NS128B0-7DCWP
生命周期：	Transferred
IHS 制造商：	EON SILICON SOLUTION INC
包装说明：	VFBGA,
Reach Compliance Code：	unknown
HTS代码：	8542.32.00.51
风险等级：	5.8
JESD-30 代码：	R-PBGA-B56
长度：	7.7 mm
内存密度：	134217728 bit
内存集成电路类型：	FLASH
内存宽度：	16
功能数量：	1
端子数量：	56
字数：	8388608 words
字数代码：	8000000
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-25 °C
组织：	8MX16
封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL
编程电压：	1.8 V
座面最大高度：	1 mm
最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子形式：	BALL
端子节距：	0.5 mm
端子位置：	BOTTOM
宽度：	6.2 mm
Base Number Matches：	1

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