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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • EP3SL110F780C3N
  • 数量-
  • 厂家-
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  • 批号-
  • -
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    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • EP3SL110F780C3N图
  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N 三甲现货
  • 数量1300 
  • 厂家ALTERA 
  • 封装FBGA 
  • 批号24+ 
  • 原装认证,现货供应!实力商家
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  • 0755-88608316 QQ:2853107358QQ:2853107357
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N 三甲现货
  • 数量1630 
  • 厂家ALTERA 
  • 封装FBGA 
  • 批号24+ 
  • 渠道商,提供原厂COC,可开原型号发票
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  • 0755-88608527 QQ:3003819484QQ:3003818780
  • EP3SL110F780C3N图
  • 集好芯城

     该会员已使用本站13年以上
  • EP3SL110F780C3N 现货库存
  • 数量2213 
  • 厂家ALTERA(阿尔特拉) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
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  • 0755-83239307 QQ:3008092965QQ:3008092965
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N 现货库存
  • 数量560 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
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  • 755-83950019 QQ:800888908
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N 现货库存
  • 数量1860 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 专业ALTERA,假一罚万!
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  • EP3SL110F780C3N图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • EP3SL110F780C3N 现货库存
  • 数量3200 
  • 厂家ALTERA代理主营品牌 
  • 封装780FBGA 
  • 批号22+ 
  • ALTERA代理旗下专业分销!原装正品!
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  • 86-755-83616256 QQ:2355507162QQ:2355507165
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N 现货库存
  • 数量1860 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 专业ALTERA,假一罚万!
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
  • 0755-83950895 QQ:3003818780QQ:3003819484
  • EP3SL110F780C3N图
  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N 现货库存
  • 数量2660 
  • 厂家ALTERA 
  • 封装直销 
  • 批号24+ 
  • ALTERA现场可编程门阵列 (FPGA) ,中国地区销售
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  • 0755-88608316 QQ:2853107358QQ:2853107357
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N 现货库存
  • 数量2860 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 专业ALTERA,假一罚万!
  • QQ:3003819484QQ:3003819484 复制
    QQ:3003818780QQ:3003818780 复制
  • 0755-88608527 QQ:3003819484QQ:3003818780
  • EP3SL110F780C3N图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N 现货库存
  • 数量71 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • EP3SL110F780C3N图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N 现货库存
  • 数量71 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • EP3SL110F780C3N图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N
  • 数量13880 
  • 厂家Altera 
  • 封装780FBGA 
  • 批号21+ 
  • 公司只售原装 支持实单
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • EP3SL110F780C3N图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N
  • 数量85000 
  • 厂家Altera 
  • 封装BGA 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 0755-23605827 QQ:2881495753
  • EP3SL110F780C3N图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • EP3SL110F780C3N
  • 数量2213 
  • 厂家ALTERA(阿尔特拉) 
  • 封装 
  • 批号24+ 
  • 原装原厂现货
  • QQ:562765057QQ:562765057 复制
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  • 0755-84509636 QQ:562765057QQ:370820820
  • EP3SL110F780C3N图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N
  • 数量5600 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号23+ 
  • 100%深圳原装现货库存
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  • 18929336553 QQ:2276916927QQ:1977615742
  • EP3SL110F780C3N图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • EP3SL110F780C3N
  • 数量4500 
  • 厂家ALTERA 
  • 封装780FBGA 
  • 批号25+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • EP3SL110F780C3N图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N
  • 数量6800 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应
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  • 0755-82865294 QQ:198857245
  • EP3SL110F780C3N图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N
  • 数量71 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • EP3SL110F780C3N图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • EP3SL110F780C3N
  • 数量12736 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号23+ 
  • 全新原装正品现货特价
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • EP3SL110F780C3N图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • EP3SL110F780C3N
  • 数量3145 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • EP3SL110F780C3N图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • EP3SL110F780C3N
  • 数量30000 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • EP3SL110F780C3N图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N
  • 数量7098 
  • 厂家ALTERA/阿尔特拉 
  • 封装FPBGA780 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • EP3SL110F780C3N图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • EP3SL110F780C3N
  • 数量55874 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • EP3SL110F780C3N图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • EP3SL110F780C3N
  • 数量6500 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • EP3SL110F780C3N图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N
  • 数量10000 
  • 厂家ALTERA 
  • 封装780FBGA 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • EP3SL110F780C3N图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • EP3SL110F780C3N
  • 数量8800 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • EP3SL110F780C3N图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • EP3SL110F780C3N
  • 数量865000 
  • 厂家Altera 
  • 封装BGA 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • EP3SL110F780C3N图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • EP3SL110F780C3N
  • 数量12245 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
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  • 0755-83952260 QQ:2885659458QQ:2885657384
  • EP3SL110F780C3N图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • EP3SL110F780C3N
  • 数量24537 
  • 厂家ALTERA 
  • 封装FBGA780 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • EP3SL110F780C3N图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • EP3SL110F780C3N
  • 数量12500 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号23+ 
  • 全新原装现货,假一赔十
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • EP3SL110F780C3N图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • EP3SL110F780C3N
  • 数量253 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
  • QQ:800888908QQ:800888908 复制
  • 755-83950019 QQ:800888908
  • EP3SL110F780C3N图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • EP3SL110F780C3N
  • 数量325 
  • 厂家ALTERA原装 
  • 封装BGA 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507162QQ:2355507162 复制
    QQ:2355507165QQ:2355507165 复制
  • 86-755-83616256 QQ:2355507162QQ:2355507165
  • EP3SL110F780C3N图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • EP3SL110F780C3N
  • 数量28620 
  • 厂家Intel 
  • 封装780-BBGA 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • EP3SL110F780C3N图
  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • EP3SL110F780C3N
  • 数量45000 
  • 厂家ALTERA(阿尔特拉) 
  • 封装 
  • 批号1年内 
  • 原厂渠道 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
  • EP3SL110F780C3N图
  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • EP3SL110F780C3N
  • 数量4600 
  • 厂家ALTERA 
  • 封装原厂 
  • 批号24+ 
  • 中华地区销售
  • QQ:2853107358QQ:2853107358 复制
    QQ:2853107357QQ:2853107357 复制
  • 0755-88608316 QQ:2853107358QQ:2853107357
  • EP3SL110F780C3N图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • EP3SL110F780C3N
  • 数量32222 
  • 厂家INTEL/英特尔 
  • 封装FPBGA780 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • EP3SL110F780C3N图
  • 深圳市励创源科技有限公司

     该会员已使用本站2年以上
  • EP3SL110F780C3N
  • 数量35600 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号21+ 
  • 诚信经营,原装现货,假一赔十,欢迎咨询15323859243
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  • EP3SL110F780C3N图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • EP3SL110F780C3N
  • 数量2800 
  • 厂家ALTERA/阿尔特拉 
  • 封装BGA 
  • 批号20+ 
  • 绝对全新原装现货,欢迎来电查询
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
  • EP3SL110F780C3N图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • EP3SL110F780C3N
  • 数量71 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • EP3SL110F780C3N图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • EP3SL110F780C3N
  • 数量50000 
  • 厂家ALTERA 
  • 封装BGA 
  • 批号21+ 
  • 原装现货
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788

产品型号EP3SL110F780C3N的概述

芯片EP3SL110F780C3N的概述 EP3SL110F780C3N是由英特尔公司(Intel Corporation)设计和生产的一款阵列可编程逻辑器件(FPGA),属于其Stratix III系列。这款芯片专为满足高性能、高速数据处理应用而设计,广泛应用于通信、数据中心、工业自动化及军事等领域。其灵活的配置能力和强大的处理能力使其成为多种应用场合中极为理想的选择。 芯片EP3SL110F780C3N的详细参数 EP3SL110F780C3N FPGA在设计上具备丰富的参数,满足复杂应用的需求。该器件主要参数如下: 1. 逻辑单元: EP3SL110具有约110,000个可编程逻辑单元(LE),能够支持复杂的逻辑运算和功能实现。 2. 查找表(LUT): 每个逻辑单元配备的4输入查找表,可以实现灵活的逻辑函数构建。 3. 嵌入式存储器: 支持最多4.5Mb的嵌入式RAM,为数据存...

产品型号EP3SL110F780I4的Datasheet PDF文件预览

1. Stratix III Device Family Overview  
SIII51001-1.8  
The Stratix® III family provides one of the most architecturally advanced,  
high-performance, low-power FPGAs in the marketplace.  
Stratix III FPGAs lower power consumption through Altera’s innovative  
Programmable Power Technology, which provides the ability to turn on the  
performance where needed and turn down the power consumption for blocks not in  
use. Selectable Core Voltage and the latest in silicon process optimizations are also  
employed to deliver the industry’s lowest power, high-performance FPGAs.  
Specifically designed for ease of use and rapid system integration, the Stratix III  
FPGA family offers two variants optimized to meet different application needs:  
The Stratix III L family provides balanced logic, memory, and multiplier ratios for  
mainstream applications.  
The Stratix III E family is memory- and multiplier-rich for data-centric  
applications.  
Modular I/O banks with a common bank structure for vertical migration lend  
efficiency and flexibility to the high-speed I/O. Package and die enhancements with  
dynamic on-chip termination, output delay, and current strength control provide  
best-in-class signal integrity.  
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a  
programmable alternative to custom ASICs and programmable processors for  
high-performance logic, digital signal processing (DSP), and embedded designs.  
Stratix III devices include optional configuration bit stream security through volatile  
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where  
ultra-high reliability is required, Stratix III devices include automatic error detection  
circuitry to detect data corruption by soft errors in the configuration random-access  
memory (CRAM) and user memory cells.  
Features Summary  
Stratix III devices offer the following features:  
48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 1–1)  
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM  
block sizes to implement true dual-port memory and FIFO buffers  
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,  
and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and  
finite impulse response (FIR) filters  
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for  
robust signal integrity  
Programmable Power Technology, which minimizes power while maximizing  
device performance  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
1–2  
Chapter 1: Stratix III Device Family Overview  
Features Summary  
Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),  
enables selection of lowest power or highest performance operation  
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device  
Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,  
clock switchover, programmable bandwidth, clock synthesis, and dynamic phase  
shifting  
Memory interface support with dedicated DQS logic on all I/O banks  
Support for high-speed external memory interfaces including DDR, DDR2,  
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular  
I/O banks  
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide  
range of industry I/O standards  
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O  
banks  
High-speed differential I/O support with serializer/deserializer (SERDES) and  
dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance  
Support for high-speed networking and communications bus standards including  
SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI  
The only high-density, high-performance FPGA with support for 256-bit AES  
volatile and non-volatile security key to protect designs  
Robust on-chip hot socketing and power sequencing support  
Integrated cyclical redundancy check (CRC) for configuration memory error  
detection with critical error determination for high availability systems support  
Built-in error correction coding (ECC) circuitry to detect and correct data errors in  
M144K TriMatrix memory blocks  
®
Nios II embedded processor support  
®
®
Support for multiple intellectual property megafunctions from Altera MegaCore  
functions and Altera Megafunction Partners Program (AMPP )  
SM  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
Chapter 1: Stratix III Device Family Overview  
1–3  
Features Summary  
Table 1–1 lists the Stratix III FPGA family features.  
Table 1–1. FPGA Family Features for Stratix III Devices  
MLAB  
RAM  
Kbits  
(1)  
Total  
Embedded  
RAM Kbits  
Total  
RAM  
18×18-bit  
Device/  
Feature  
M9K  
M144K MLAB  
PLLs  
(3)  
ALMs  
LEs  
Multipliers  
Blocks Blocks Blocks  
Kbits(2) (FIR Mode)  
EP3SL50  
EP3SL70  
19K  
27K  
47.5K  
67.5K  
108  
150  
275  
355  
468  
6
950  
1,836  
2,214  
4,203  
5,499  
9,396  
16,272  
5,328  
6,183  
8,055  
14,688  
297  
422  
2,133  
2,636  
4,875  
6,390  
10,646  
18,381  
5,625  
6,683  
8,727  
16,282  
216  
288  
288  
384  
576  
576  
384  
672  
896  
768  
4
4
6
1,350  
2,150  
2,850  
4,000  
6,750  
950  
Stratix III  
Logic  
Family  
EP3SL110 43K 107.5K  
EP3SL150 57K 142.5K  
12  
16  
36  
48  
12  
12  
16  
48  
672  
8
891  
8
EP3SL200 80K  
200K  
1,250  
2,109  
297  
12  
12  
4
EP3SL340 135K 337.5K 1,040  
EP3SE50  
EP3SE80  
19K  
32K  
47.5K  
80K  
400  
495  
639  
864  
Stratix III  
Enhanced  
Family  
1,600  
2,150  
5,100  
500  
8
EP3SE110 43K 107.5K  
EP3SE260 102K 255K  
672  
8
1,594  
12  
Notes to Table 1–1:  
(1) MLAB ROM mode supports twice the number of MLAB RAM Kbits.  
(2) For total ROM Kbits, use this equation to calculate:  
Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]  
(3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the Clock Networks and PLLs in Stratix  
III Devices chapter in volume 1 of the Stratix III Device Handbook for the availability of the PLLs for each device.  
The Stratix III logic family (L) offers balanced logic, memory, and multipliers to  
address a wide range of applications, while the enhanced family (E) offers more  
memory and multipliers per logic and is ideal for wireless, medical imaging, and  
military applications.  
Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer  
to Table 1–2 and Table 1–3).  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
 
 
 
 
1–4  
Chapter 1: Stratix III Device Family Overview  
Features Summary  
Table 1–2 lists the Stratix III FPGA package options and I/O pin counts.  
Table 1–2. Package Options and I/O Pin Counts (Note 1)  
484-Pin  
FineLine  
BGA (2)  
780-Pin  
FineLine  
BGA (2)  
1152-Pin  
FineLine  
BGA (2)  
1517-Pin  
1760-Pin  
Device  
EP3SL50  
FineLine BGA FineLine BGA  
(3)  
(3)  
296  
296  
488  
488  
EP3SL70  
EP3SL110  
EP3SL150  
EP3SL200  
EP3SL340  
EP3SE50  
488  
744  
744  
744  
744 (4)  
488  
488 (5)  
976  
976  
1,120  
296  
488  
EP3SE80  
488  
744  
744  
744  
EP3SE110  
EP3SE260  
Notes to Table 1–2:  
488  
488 (5)  
976  
(1) The arrows indicate vertical migration.  
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p,CLK1n,CLK3p,CLK3n,CLK8p,CLK8n,  
CLK10p,and CLK10n) that can be used for data inputs.  
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p,  
CLK8n,CLK10p,and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp,  
PLL_L1_CLKn,PLL_L4_CLKp,PLL_L4_CLKn,PLL_R4_CLKp,PLL_R4_CLKn,PLL_R1_CLKp,  
and PLL_R1_CLKn) that can be used for data inputs.  
(4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package.  
(5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package.  
All Stratix III devices support vertical migration within the same package (for  
example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin  
FineLine BGA package). Vertical migration allows you to migrate to devices whose  
dedicated pins, configuration pins, and power pins are the same for a given package  
across device densities.  
To ensure that a board layout supports migratable densities within one package  
®
offering, enable the applicable vertical migration path within the Quartus II  
software. On the Assignments menu, point to Device and click Migration Devices.  
You can migrate from the L family to the E family without increasing the number of  
LEs available. This minimizes the cost of vertical migration.  
Table 1–3 lists the Stratix III FineLine BGA (FBGA) package sizes.  
Table 1–3. FineLine BGA Package Sizes  
Dimension  
Pitch (mm)  
484 Pin  
1.00  
780 Pin  
1.00  
1152 Pin  
1.00  
1517 Pin  
1.00  
1760 Pin  
1.00  
2
Area (mm )  
529  
841  
1,225  
35/35  
1,600  
40/40  
1,849  
43/43  
Length/Width (mmmm)  
23/23  
29/29  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
 
 
 
 
 
 
 
Chapter 1: Stratix III Device Family Overview  
1–5  
Features Summary  
Table 1–4 lists the Stratix III Hybrid FineLine BGA (HBGA) package sizes.  
Table 1–4. Hybrid FineLine BGA Package Sizes  
Dimension  
780 Pin  
1.00  
1152 Pin  
1.00  
Pitch (mm)  
2
Area (mm )  
1,089  
33/33  
1,600  
40/40  
Length/Width (mmmm)  
Stratix III devices are available in up to three speed grades: –2, –3, and –4, with –2  
being the fastest. Stratix III devices are offered in both commercial and industrial  
temperature range ratings with leaded and lead-free packages. Selectable Core  
Voltage is available in specially marked low-voltage devices (L ordering code suffix).  
Table 1–5 lists the Stratix III device speed grades.  
Table 1–5. Speed Grades for Stratix III Devices (Part 1 of 2)  
780-Pin  
Hybrid  
FineLine  
BGA  
1152-Pin  
Hybrid  
FineLine  
BGA  
484 -Pin  
FineLine  
BGA  
780-Pin  
FineLine  
BGA  
1152-Pin  
FineLine  
BGA  
1517-Pin  
FineLine  
BGA  
1760-Pin  
FineLine  
BGA  
Temperature  
Grade  
Device  
–2, –3, –4,  
–4L  
–2, –3,–4,  
–4L  
Commercial  
Industrial  
EP3SL50  
EP3SL70  
EP3SL110  
EP3SL150  
–3, –4, –4L  
–3, –4, –4L  
–2, –3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
–3, –4, –4L  
–3, –4, –4L  
–2, –3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
–3, –4, –4L  
–3, –4, –4L  
–2,–3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
–3, –4, –4L  
–3, –4, –4L  
–2,–3, –4,  
–4L  
–2,–3, –4,  
–4L  
–2,–3, –4,  
–4L  
Commercial  
EP3SL200  
EP3SL340  
EP3SE50  
Industrial (1)  
Commercial  
Industrial (1)  
–3, –4, –4L  
–3, –4, –4L  
–3, –4, –4L  
–2, –3, –4  
–3, –4, –4L  
–2, –3, –4  
–3, –4, –4L  
–2, –3, –4  
–3, –4, –4L  
–2, –3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
–3, –4, –4L  
–3, –4, –4L  
–2, –3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
EP3SE80  
–3, –4, –4L  
–3, –4, –4L  
–2,–3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
Industrial  
EP3SE110  
–3, –4, –4L  
–3, –4, –4L  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
 
 
1–6  
Chapter 1: Stratix III Device Family Overview  
Architecture Features  
Table 1–5. Speed Grades for Stratix III Devices (Part 2 of 2)  
780-Pin  
Hybrid  
FineLine  
BGA  
1152-Pin  
484 -Pin  
FineLine  
BGA  
780-Pin  
FineLine  
BGA  
1152-Pin  
FineLine  
BGA  
1517-Pin  
FineLine  
BGA  
1760-Pin  
FineLine  
BGA  
Temperature  
Grade  
Hybrid  
FineLine  
BGA  
Device  
–2, –3, –4,  
–4L  
–2,– 3, –4,  
–4L  
–2, –3, –4,  
–4L  
Commercial  
EP3SE260  
Industrial (1)  
–3, –4, –4L  
–3, –4, –4L  
–3, –4,–4L  
Note to Table 1–5:  
(1) For EP3SL340, EP3SL200, and EP3SE260 devices, the industrial junction temperature range for –4L is 0–100°C, regardless of supply voltage.  
Architecture Features  
The following section describes the various features of the Stratix III family FPGAs.  
Logic Array Blocks and Adaptive Logic Modules  
The Logic Array Block (LAB) is composed of basic building blocks known as  
Adaptive Logic Modules (ALMs) that can be configured to implement logic,  
arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains,  
shared arithmetic chains, LAB control signals, local interconnect, and register chain  
connection lines. ALMs are part of a unique, innovative logic structure that delivers  
faster performance, minimizes area, and reduces power consumption. ALMs expand  
the traditional 4-input look-up table architecture to 7 inputs, increasing performance  
by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize  
DSP performance with dedicated functionality to efficiently implement adder trees  
and other complex arithmetic functions. The Quartus II Compiler places associated  
logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,  
and register chain connections for performance and area efficiency.  
The Stratix III LAB has a new derivative called Memory LAB (or MLAB), which adds  
SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all  
LAB features. MLABs support a maximum of 320 bits of simple dual-port Static  
Random Access Memory (SRAM). Each ALM in an MLAB can be configured as a  
16×2 block, resulting in a configuration of 16×20 simple dual port SRAM block. MLAB  
and LAB blocks always co-exist as pairs in all Stratix III families, allowing up to 50%  
of the logic (LABs) to be traded for memory (MLABs).  
f
f
For more information about LABs and ALMs, refer to the Logic Array Blocks and  
Adaptive Logic Modules in Stratix III Devices chapter.  
For more information about MLAB modes, features and design considerations, refer  
to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter.  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
 
Chapter 1: Stratix III Device Family Overview  
1–7  
Architecture Features  
MultiTrack Interconnect  
In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP  
blocks, and device I/O pins are provided by the MultiTrack interconnect structure  
with DirectDrive technology. The MultiTrack interconnect consists of continuous,  
performance-optimized row and column interconnects that span fixed distances. A  
routing structure with fixed length resources for all devices allows predictable and  
repeatable performance when migrating through different device densities. The  
MultiTrack interconnect provides 1-hop connection to 34 adjacent LABs, 2-hop  
connections to 96 adjacent LABs and 3-hop connections to 160 adjacent LABs.  
DirectDrive technology is a deterministic routing technology that ensures identical  
routing resource usage for any function regardless of placement in the device. The  
MultiTrack interconnect and DirectDrive technology simplify the integration stage of  
block-based designing by eliminating the reoptimization cycles that typically follow  
design changes and additions. The Quartus II Compiler also automatically places  
critical design paths on faster interconnects to improve design performance.  
f
For more information, refer to the MultiTrack Interconnect in Stratix III Devices chapter.  
TriMatrix Embedded Memory Blocks  
TriMatrix embedded memory blocks provide three different sizes of embedded  
SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory  
includes the following blocks:  
320-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers,  
and shift registers  
9-Kbit M9K blocks that can be used for general purpose memory applications  
144-Kbit M144K blocks that are ideal for processor code storage, packet and video  
frame buffering  
Each embedded memory block can be independently configured to be a single- or  
TM  
dual-port RAM, ROM, or shift register via the Quartus II MegaWizard Plug-In  
Manager. Multiple blocks of the same type can also be stitched together to produce  
larger memories with minimal timing penalty. TriMatrix memory provides up to  
16,272 Kbits of embedded SRAM at up to 600 MHz operation.  
f
For more information about TriMatrix memory blocks, modes, features, and design  
considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices  
chapter.  
DSP Blocks  
Stratix III devices have dedicated high-performance digital signal processing (DSP)  
blocks optimized for DSP applications requiring high data throughput. Stratix III  
devices provide you with the ability to implement various high-performance DSP  
functions easily. Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000,  
voice over Internet Protocol (VoIP), H.264 video compression, and high-definition  
television (HDTV) require high-performance DSP blocks to process data. These  
system designs typically use DSP blocks to implement finite impulse response (FIR)  
filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier  
transform (FFT) functions, and discrete cosine transform (DCT) functions.  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
1–8  
Chapter 1: Stratix III Device Family Overview  
Architecture Features  
Stratix III devices have up to 112 DSP blocks. The architectural highlights of the  
Stratix III DSP block are the following:  
High-performance, power optimized, fully pipelined multiplication operations  
Native support for 9-bit, 12-bit, 18-bit, and 36-bit word lengths  
Native support for 18-bit complex multiplications  
Efficient support for floating point arithmetic formats (24-bit for Single Precision  
and 53-bit for Double Precision)  
Signed and unsigned input support  
Built-in addition, subtraction, and accumulation units to efficiently combine  
multiplication results  
Cascading 18-bit input bus to form tap-delay lines  
Cascading 44-bit output bus to propagate output results from one block to the next  
block  
Rich and flexible arithmetic rounding and saturation units  
Efficient barrel shifter support  
Loopback capability to support adaptive filtering  
DSP block multipliers can optionally feed an adder/subtractor or accumulator in the  
block depending on user configuration. This option saves ALM routing resources and  
increases performance, because all connections and blocks are inside the DSP block.  
Additionally, the DSP Block input registers can efficiently implement shift registers  
for FIR filter applications, and the Stratix III DSP blocks support rounding and  
saturation. The Quartus II software includes megafunctions that control the mode of  
operation of the DSP blocks based on user parameter settings.  
f
For more information, refer to the DSP Blocks in Stratix III Devices chapter.  
Clock Networks and PLLs  
Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock  
Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are  
organized into a hierarchical clock structure that provides up to 104 unique clock  
domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16  
GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant.  
Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and  
up to 10 outputs per PLL. Every output can be independently programmed, creating a  
unique, customizable clock frequency. Inherent jitter filtration and fine granularity  
control over multiply, divide ratios, and dynamic phase-shift reconfiguration provide  
the high-performance precision required in today’s high-speed applications. Stratix III  
PLLs are feature rich, supporting advanced capabilities such as clock switchover,  
reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs  
can be used for general-purpose clock management supporting multiplication, phase  
shifting, and programmable duty cycle. Stratix III PLLs also support external  
feedback mode, spread-spectrum input clock tracking, and post-scale counter  
cascading.  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
Chapter 1: Stratix III Device Family Overview  
1–9  
Architecture Features  
f
For more information, refer to the Clock Networks and PLLs in Stratix III Devices  
chapter.  
I/O Banks and I/O Structure  
Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32,  
36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases  
device migration. The I/O banks contain circuitry to support external memory  
interfaces at speeds up to 533 MHz and high-speed differential I/O interfaces meeting  
up to 1.6 Gbps performance. It also supports high-speed differential inputs and  
outputs running at speeds up to 800 MHz.  
Stratix III devices support a wide range of industry I/O standards, including  
single-ended, voltage referenced single-ended, and differential I/O standards. The  
Stratix III I/O supports programmable bus hold, programmable pull-up resistor,  
programmable slew rate, programmable drive strength, programmable output delay  
control, and open-drain output. Stratix III devices also support on-chip series (RS) and  
on-chip parallel (RT) termination with auto calibration for single-ended I/O standards  
and on-chip differential termination (RD) for LVDS I/O standards on Left/Right I/O  
banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks.  
f
For more information, refer to the Stratix III Device I/O Features chapter.  
External Memory Interfaces  
The Stratix III I/O structure has been completely redesigned to provide flexibility and  
enable high-performance support for existing and emerging external memory  
standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAM II at  
frequencies of up to 533 MHz.  
Packed with features such as dynamic on-chip termination, trace mismatch  
compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable  
DQ group widths, Stratix III I/Os supply the built-in functionality required for rapid  
and robust implementation of external memory interfaces. Double data-rate support  
is found on all sides of the Stratix III device. Stratix III devices provide an efficient  
architecture to quickly and easily fit wide external memory interfaces exactly where  
you want them.  
A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the  
Stratix III device I/O, along with the Quartus II timing analysis tool (TimeQuest),  
provide the total solution for the highest reliable frequency of operation across  
process voltage and temperature.  
f
For more information about external memory interfaces, refer to the External Memory  
Interfaces in Stratix III Devices chapter.  
High-Speed Differential I/O Interfaces with DPA  
Stratix III devices contain dedicated circuitry for supporting differential standards at  
speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the  
following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2,  
SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×,  
4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
 
1–10  
Chapter 1: Stratix III Device Family Overview  
Architecture Features  
4×, 6×, 7×, 8×, and 10× SERDES modes when using the dedicated DPA circuitry. DPA  
minimizes bit errors, simplifies PCB layout and timing management for high-speed  
data transfer, and eliminates channel-to-channel and channel-to-clock skew in  
high-speed data transmission systems. Soft CDR can also be implemented, enabling  
low-cost 1.6-Gbps clock embedded serial links.  
Stratix III devices have the following dedicated circuitry for high-speed differential  
I/O support:  
Differential I/O buffer  
Transmitter serializer  
Receiver deserializer  
Data realignment  
Dynamic phase aligner (DPA)  
Soft CDR functionality  
Synchronizer (FIFO buffer)  
PLLs  
f
For more information, refer to the High Speed Differential I/O Interfaces with DPA in  
Stratix III Devices chapter.  
Hot Socketing and Power-On Reset  
Stratix III devices are hot-socketing compliant. Hot socketing is also known as hot  
plug-in or hot swap, and power sequencing support without the use of any external  
devices. Robust on-chip hot-socketing and power-sequencing support ensures proper  
device operation independent of the power-up sequence. You can insert or remove a  
Stratix III board in a system during system operation without causing undesirable  
effects to the running system bus or the board that was inserted into the system.  
The hot-socketing feature makes it easier to use Stratix III devices on PCBs that also  
contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. With the  
Stratix III hot socketing feature, you do not need to ensure a specific power-up  
sequence for each device on the board.  
f
For more information, refer to the Hot Socketing and Power-On Reset in Stratix III  
Devices chapter.  
Configuration  
Stratix III devices are configured using one of the following four configuration  
schemes:  
Fast passive parallel (FPP)  
Fast active serial (AS)  
Passive serial (PS)  
Joint Test Action Group (JTAG)  
®
All configuration schemes use either an external controller (for example, a MAX II  
device or microprocessor), a configuration device, or a download cable.  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
Chapter 1: Stratix III Device Family Overview  
1–11  
Architecture Features  
Stratix III devices support configuration data decompression, which saves  
configuration memory space and time. This feature allows you to store compressed  
configuration data in configuration devices or other memory and transmit this  
compressed bitstream to Stratix III devices. During configuration, the Stratix III  
device decompresses the bitstream in real time and programs its SRAM cells.  
Stratix III devices support decompression in the FPP when using a MAX II  
device/microprocessor plus flash, fast AS, and PS configuration schemes. The  
Stratix III decompression feature is not available in the FPP when using the enhanced  
configuration device and JTAG configuration schemes.  
f
For more information, refer to the Configuring Stratix III Devices chapter.  
Remote System Upgrades  
Stratix III devices feature remote system upgrade capability, allowing error-free  
deployment of system upgrades from a remote location securely and reliably. Soft  
logic (either the Nios embedded processor or user logic) implemented in a Stratix III  
device can download a new configuration image from a remote location, store it in  
configuration memory, and direct the dedicated remote system upgrade circuitry to  
initiate a reconfiguration cycle. The dedicated circuitry performs error detection  
during and after the configuration process, and can recover from an error condition  
by reverting back to a safe configuration image, and provides error status  
information. This dedicated remote system upgrade circuitry is unique to Stratix  
series FPGAs and helps to avoid system downtime.  
f
For more information, refer to the Remote System Upgrades with Stratix III Devices  
chapter.  
IEEE 1149.1 (JTAG) Boundary-Scan Testing  
Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan  
Test (BST) architecture offers the capability to test pin connections without using  
physical test probes and capture functional data while a device is operating normally.  
Boundary-scan cells in the Stratix III device can force signals onto pins or capture data  
from pin or logic array signals. Forced test data is serially shifted into the  
boundary-scan cells. Captured data is serially shifted out and externally compared to  
expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for  
Stratix III device in-circuit reconfiguration (ICR).  
f
For more information, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in  
Stratix III Devices chapter.  
Design Security  
Stratix III devices are high-density, high-performance FPGAs with support for 256-bit  
volatile and non-volatile security keys to protect designs against copying, reverse  
engineering, and tampering. Stratix III devices have the ability to decrypt a  
configuration bitstream using the Advanced Encryption Standard (AES) algorithm,  
an industry standard encryption algorithm that is FIPS-197 certified and requires a  
256-bit security key.  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
1–12  
Chapter 1: Stratix III Device Family Overview  
Architecture Features  
The design security feature is available when configuring Stratix III FPGAs using the  
fast passive parallel (FPP) configuration mode with an external host (such as a MAX II  
device or microprocessor), or when using fast active serial (AS) or passive serial (PS)  
configuration schemes.  
f
For more information about the design security feature, refer to the Design Security in  
Stratix III Devices chapter.  
SEU Mitigation  
Stratix III devices have built-in error detection circuitry to detect data corruption due  
to soft errors in the configuration random-access memory (CRAM) cells. This feature  
allows all CRAM contents to be read and verified continuously during user mode  
operation to match a configuration-computed CRC value. The enhanced CRC circuit  
and frame-based configuration architecture allows detection and location of multiple,  
single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a  
reference design, allows don’t-care soft errors in the CRAM to be ignored during  
device operation. This provides a steep decrease in the effective soft error rate,  
increasing system reliability.  
On-chip memory block SEU mitigation is also offered using the ninth bit and a  
configurable megafunction in the Quartus II software for MLAB and M9K blocks  
while the M144K memory blocks have built-in error correction code (ECC) circuitry.  
f
For more information about the dedicated error detection circuitry, refer to the SEU  
Mitigation in Stratix III Devices chapter.  
Programmable Power  
Stratix III delivers Programmable Power, the only FPGA with user programmable  
power options balancing today’s power and performance requirements. Stratix III  
devices utilize the most advanced power-saving techniques, including a variety of  
process, circuit, and architecture optimizations and innovations. In addition, user  
controllable power reduction techniques provide an optimal balance of performance  
and power reduction specific for each design configured into the Stratix III FPGA. The  
Quartus II software (starting from version 6.1) automatically optimizes designs to  
meet the performance goals while simultaneously leveraging the programmable  
power-saving options available in the Stratix III FPGA without the need for any  
changes to the design flow.  
f
For more information about Programmable Power in Stratix III devices, refer to the  
following documents:  
Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter  
AN 437: Power Optimization in Stratix III FPGAs  
Stratix III Programmable Power White Paper  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
Chapter 1: Stratix III Device Family Overview  
1–13  
Reference and Ordering Information  
Signal Integrity  
Stratix III devices simplify the challenge of signal integrity through a number of chip,  
package, and board level enhancements to enable efficient high-speed data transfer  
into and out of the device. These enhancements include:  
8:1:1 user I/O/Gnd/VCC ratio to reduce the loop inductance in the package  
Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank,  
to help limit simultaneous switching noise  
Programmable slew-rate support with up to four settings to match desired I/O  
standard, control noise, and overshoot  
Programmable output-current drive strength support with up to six settings to  
match desired I/O standard performance  
Programmable output-delay support to control rise/fall times and adjust duty  
cycle, compensate for skew, and reduce simultaneous switching outputs (SSO)  
noise  
Dynamic OCT with auto calibration support for series and parallel OCT and  
differential OCT support for LVDS I/O standard on the left/right banks  
f
f
For more information about SI support in the Quartus II software, refer to the  
Quartus II Handbook.  
For more information about how to use the various configuration, PLL, external  
memory interfaces, I/O, high-speed differential I/O, power, and JTAG pins, refer to  
the Stratix III Device Family Pin Connection Guidelines.  
Reference and Ordering Information  
The following section describes Stratix III device software support and ordering  
information.  
Software Support  
Stratix III devices are supported by the Altera Quartus II design software, version 6.1  
and later, which provides a comprehensive environment for  
system-on-a-programmable-chip (SOPC) design. The Quartus II software includes  
HDL and schematic design entry, compilation and logic synthesis, full simulation and  
®
advanced timing analysis, SignalTap II logic analyzer, and device configuration.  
f
For more information about the Quartus II software features, refer to the Quartus II  
Handbook.  
The Quartus II software supports a variety of operating systems. The specific  
operating system for the Quartus II software can be obtained from the Quartus II  
Readme.txt file or the Operating System Support section of the Altera website. It also  
supports seamless integration with industry-leading EDA tools through the  
®
NativeLink interface.  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
1–14  
Chapter 1: Stratix III Device Family Overview  
Chapter Revision History  
Ordering Information  
Figure 1–1 shows the ordering codes for Stratix III devices.  
f
For more information about a specific package, refer to the Stratix III Device Package  
Information chapter.  
Figure 1–1. Stratix III Device Packaging Ordering Information  
EP3SL  
150  
F
1152  
C
2
ES  
Family Signature  
Optional Suffix  
Indicatesspecific deviceoptions  
EP3SL:Stratix III Logic  
ES: Engineering sample  
N: Lead-free devices  
L: Low-voltage devices  
EP3SE: Stratix III DSP/Memory  
Device Type  
Speed Grade  
50  
70  
2, 3, or 4, with 2 being the fastest  
80  
110  
150  
200  
260  
340  
Operating Temperature  
C: Commercial temperature(t = 0 C to 85 C)  
J
I:  
Industrial temperature (t =-40 C to 100 C)  
J
Package Type  
Pin Count  
Number of pins for a particular package:  
F:  
FineLine BGA (FBGA)  
484  
H:  
Hybrid FineLine BGA (HBGA)  
780  
1152  
1517  
1760  
Chapter Revision History  
Table 1–6 lists the revision history for this chapter.  
Table 1–6. Chapter Revision History (Part 1 of 2)  
Date  
March 2010  
May 2009  
Version  
Changes Made  
Updated for the Quartus II software version 9.1 SP2 release:  
Updated Table 1–2.  
1.8  
1.7  
1.6  
Updated “I/O Banks and I/O Structure” section.  
Updated “Software” and “Signal Integrity” sections.  
Updated “Features” section.  
February 2009  
Updated Table 1–1.  
Removed “Referenced Documents” section.  
Updated “Features” section.  
October 2008  
1.5  
Updated Table 1–1 and Table 1–5.  
Updated New Document Format.  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
 
 
Chapter 1: Stratix III Device Family Overview  
1–15  
Chapter Revision History  
Table 1–6. Chapter Revision History (Part 2 of 2)  
Date  
Version  
Changes Made  
Updated “Introduction”.  
Updated Table 1–1.  
Updated Table 1–2.  
Added Table 1–5.  
May 2008  
1.4  
Updated “Reference and Ordering Information”.  
Updated package type information in Figure 1–1.  
Updated Table 1–1.  
November 2007  
October 2007  
1.3  
1.2  
Updated Table 1–2.  
Minor typo fixes.  
Added Table 1–4.  
Added section “Referenced Documents”.  
Added live links for references.  
Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in  
Table 1–1.  
May 2007  
1.1  
1.0  
November 2006  
Initial Release.  
© March 2010 Altera Corporation  
Stratix III Device Handbook, Volume 1  
1–16  
Chapter 1: Stratix III Device Family Overview  
Chapter Revision History  
Stratix III Device Handbook, Volume 1  
© March 2010 Altera Corporation  
配单直通车
EP3SL110F780C3N产品参数
型号:EP3SL110F780C3N
是否Rohs认证: 符合
生命周期:End Of Life
包装说明:BGA, BGA780,28X28,40
Reach Compliance Code:compliant
ECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01
风险等级:5.2
其他特性:IT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY
最大时钟频率:717 MHz
JESD-30 代码:S-PBGA-B780
长度:29 mm
输入次数:488
逻辑单元数量:107500
输出次数:488
端子数量:780
最高工作温度:85 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:BGA
封装等效代码:BGA780,28X28,40
封装形状:SQUARE
封装形式:GRID ARRAY
电源:1.2/3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified
座面最大高度:3.5 mm
子类别:Field Programmable Gate Arrays
最大供电电压:0.94 V
最小供电电压:0.86 V
标称供电电压:0.9 V
表面贴装:YES
技术:CMOS
温度等级:OTHER
端子形式:BALL
端子节距:1 mm
端子位置:BOTTOM
宽度:29 mm
Base Number Matches:1
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