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Configuration Devices for SRAM-Based

LUT Devices

CF52005-3.0

Datasheet

This datasheet describes configuration devices for SRAM-based look-up table (LUT)

devices.

Supported Devices

Table 1 lists the supported Altera^configuration devices.

Table 1. Altera Configuration Devices

Cascaded

Support

Recommended

Device

EPC1

Memory Size (Bits)

ISP Support

Reprogrammable

Operating Voltage (V)

1,046,496

1,695,680

65,536

No

Yes

No

Yes

No

Yes

No

5.0 or 3.3

5.0

EPC2

EPC1064

EPC1064V

EPC1213

EPC1441

65,536

No

3.3

212,942

440,800

Yes

No

5.0

5.0 or 3.3

Features

Configuration devices for SRAM-based LUT devices offer the following features:

■

Configures Altera ACEX^1K, APEX^20K (including APEX 20K, APEX 20KC, and

APEX 20KE), APEX II, Arria^GX, Cyclone^, Cyclone II, FLEX^10K (including

FLEX 10KE and FLEX 10KA) Mercury^, Stratix^, Stratix GX, Stratix II, and

Stratix II GX devices

■

Easy-to-use four-pin interface

Low current during configuration and near-zero standby mode current

Programming support with the Altera Programming Unit (APU) and

programming hardware from Data I/O, BP Microsystems, and other third-party

programmers

■

Available in compact plastic packages

■

8-pin plastic dual in-line (PDIP) package

20-pin plastic J-lead chip carrier (PLCC) package

32-pin plastic thin quad flat pack (TQFP) package

■

EPC2 device has reprogrammable flash configuration memory

QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark

Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their

respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor

products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use

of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders

for products or services.

ISO

9001:2008

Registered

101 Innovation Drive

San Jose, CA 95134

www.altera.com

January 2012 Altera Corporation

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Page 2

Functional Description

■

5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.

1149.1 JTAG interface

■

Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1

Supports programming through Serial Vector Format File (.svf), Jam^Standard

Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File

(.jbc), and the Quartus^II and MAX+PLUS^II softwares using the USB-Blaster^,

MasterBlaster^, ByteBlaster^II, EthernetBlaster, or ByteBlasterMV^download

cable

■

Supports programming through Programmer Object File (.pof) for EPC1 and

EPC1441 devices

nINIT_CONFpin allows INIT_CONFJTAG instruction to begin FPGA configuration

f For more information about enhanced configuration (EPC) devices, refer to the

Enhanced Configuration (EPC) Devices Datasheet.

f For more information about serial configuration (EPCS) devices, refer to the Serial

Configuration (EPCS) Devices Datasheet.

Functional Description

With SRAM-based devices, configuration data must be reloaded each time the device

powers up, the system initializes, or when new configuration data is needed. Altera

configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K,

APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix,

Stratix GX, Stratix II, and Stratix II GX devices.

Table 2 lists the supported configuration devices required to configure the ACEX 1K,

APEX 20K, APEX 20KC, APEX 20KE, APEX II, Cyclone, Cyclone II, FLEX 10K,

FLEX 10KA, FLEX 10KE, FLEX 6000/A, FLEX 8000A, Mercury, Stratix, Stratix GX, or

Stratix II device.

Table 2. Supported Configuration Devices (Part 1 of 4)

Data Size (Bits)

EPC1064 or

EPC1064V

Device Family

Device

EP1K10

EPC1213 EPC1441

EPC1

EPC2

(1)

159,160

473,720

—

1

2

3

2

3

4

6

EP1K30

—

1

ACEX 1K

EP1K50

784,184

1

EP1K100

1,335,720

993,360

—

1

EP20K100

EP20K200

EP20K400

EP20K200C

EP20K400C

EP20K600C

EP20K1000C

APEX 20K

1,950,800

3,880,720

1,968,016

3,909,776

5,673,936

8,960,016

—

APEX 20KC

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Functional Description

Page 3

Table 2. Supported Configuration Devices (Part 2 of 4)

Data Size (Bits)

EPC1064 or

EPC1064V

Device Family

Device

EPC1213 EPC1441

EPC1

EPC2

(1)

EP20K30E

354,832

648,016

—

1

2

3

4

6

8

3

4

6

11

1

EP20K60E

EP20K100E

EP20K160E

EP20K200E

EP20K300E

EP20K400E

EP20K600E

EP20K1000E

EP20K1500E

EP2A15

—

1

1,008,016

1,524,016

1,968,016

2,741,616

3,909,776

5,673,936

8,960,016

12,042,256

1,168,688

1,646,544

2,543,016

4,483,064

627,376

1

—

1

APEX 20KE

EP2A25

APEX II

Cyclone

EP2A40

EP2A70

EP1C3

EP1C4

925,000

1

(2)

EP1C6

1,167,216

2,326,528

3,559,608

1,265,792

1,983,536

3,892,496

6,848,608

9,951,104

14,319,216

118,000

1

(2)

EP1C12

—

1

(2)

EP1C20

2

EP2C5

1

2

3

5

6

9

1

2

EP2C8

EP2C20

Cyclone II

FLEX 10K

FLEX 10KA

EP2C35

EP2C50

EP2C70

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

EPF10K10A

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

231,000

1

376,000

1

498,000

—

1

621,000

1

892,000

1

1,200,000

120,000

—

1

406,000

1

621,000

—

1

1,200,000

1,600,000

3,300,000

—

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 4

Functional Description

Table 2. Supported Configuration Devices (Part 3 of 4)

Data Size (Bits)

EPC1064 or

EPC1064V

Device Family

Device

EPC1213 EPC1441

EPC1

EPC2

(1)

EPF10K30E

EPF10K50E

EPF10K50S

EPF10K100B

EPF10K100E

EPF10K130E

EPF10K200E

EPF10K200S

EPF6010A

473,720

784,184

—

1

784,184

1

1,200,000

1,335,720

1,838,360

2,756,296

260,000

—

1

FLEX 10KE

1

2

—

EPF6016(5.0 V)/

EPF6016A

FLEX 6000/A

260,000

398,000

40,000

—

1

—

1

—

EPF6024A

EPF8282A /

EPF8282AV(3.3 V)

EPF8452A

EPF8636A

EPF8820A

EPF81188A

EPF81500A

EP1M120

EP1M350

EP1S10

64,000

96,000

1

—

1

—

1

FLEX 8000A

Mercury

128,000

1

192,000

1

250,000

—

1

1,303,120

4,394,032

3,534,640

5,904,832

7,894,144

10,379,368

12,389,632

17,543,968

23,834,032

3,534,640

7,894,144

12,389,632

—

3

(3)

3

EP1S20

4

5

EP1S25

Stratix

EP1S30

7

EP1S40

8

EP1S60

11

15

3

EP1S80

EP1SGX10

EP1SGX25

EP1SGX40

Stratix GX

5

8

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Functional Description

Page 5

Table 2. Supported Configuration Devices (Part 4 of 4)

Data Size (Bits)

EPC1064 or

EPC1064V

Device Family

Device

EPC1213 EPC1441

EPC1

EPC2

(1)

EP2S15

5,000,000

10,100,000

17,100,000

27,500,000

39,600,000

52,400,000

—

3

EP2S30

EP2S60

EP2S90

EP2S130

EP2S180

7

11

17

24

31

Stratix II

Notes to Table 2:

(1) Raw Binary File (.rbf) were used to determine these sizes.

(2) This number is calculated with the Cyclone series compression feature enabled.

(3) EP1S10 ES devices requires four EPC2 devices.

Figure 1 shows the configuration device block diagram.

Figure 1. Configuration Device Block Diagram

FPGA (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441

DCLK

Address

Counter

CLK

ENA

Oscillator

nRESET

Oscillator

Control

Address

Decode

Logic

nCS

nCASC (1)

Error

Detection

Circuitry

EPROM

Array

(2)

OE

DATA

Shift

Register

DATA

FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V

Address

Counter

CLK

ENA

DCLK

nRESET

Address

Decode

Logic

nCASC (1)

nCS

OE

EPROM

Array

DATA

Shift

Register

DATA

Notes to Figure 1:

(1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading.

(2) The OEpin is a bidirectional open-drain pin.

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 6

Device Configuration

The EPC1, EPC2, and EPC1441 devices store configuration data in its erasable

programmable read-only memory (EPROM) array and serially clock data out using

an internal oscillator. The OE nCS, and DCLKpins supply the control signals for the

,

address counter and the DATAoutput tri-state buffer. The configuration device sends a

serial bitstream of configuration data to its DATApin, which is routed to the DATA0

input of the FPGA.

The control signals for configuration devices, OE, nCS, and DCLK, interface directly with

the FPGA control signals, nSTATUS CONF DONE, and DCLK. All Altera FPGAs can be

,

_

configured by a configuration device without requiring an external intelligent

controller.

1

An EPC2 device cannot configure FLEX 8000 or FLEX 6000 devices. For configuration

devices that support FLEX 8000 or FLEX 6000 devices, refer to Table 2.

Figure 2 shows the basic configuration interface connections between the

configuration device and the Altera FPGA.

Figure 2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device ⁽¹⁾

V

CC

Configuration

Device

(3)

(2)

(3)

FPGA

DCLK

DATA

DCLK

DATA0

OE (3)

nCS (3)

nINIT_CONF (2)

nSTATUS

CONF_DONE

nCONFIG

N.C.

nCASC

n

MSEL

nCEO

nCE

N.C.

GND

Notes to Figure 2:

(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.

(2) The nINIT CONFpin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up

resistor is not required on the nINIT CONF/nCONFIGline. The nINIT CONFpin does not need to be connected if its functionality is not used.

If the nINIT CONFpin is not used or unavailable, nCONFIGmust be pulled to V_CCeither directly or through a resistor.

_

(3) EPC2devices have internal programmable pull-up resistors on OEand nCSpins. If internal pull-up resistors are used, donot use external pull-up

resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check

the Disable nCS and OE pull-ups on configuration device option when you generate programming files.

The EPC2 device allows you to begin configuration of the FPGA using an additional

pin, nINIT

nCONFIGpin of the FPGA, which allows the INIT

FPGA configuration. The INIT CONFJTAG instruction causes the EPC2 device to drive

the nINIT CONFpin low, which in turn pulls the nCONFIGpin low. Pulling the nCONFIG

pin low on the FPGA will reset the device. When the JTAG state machine exits this

state, the nINIT CONFpin is released and pulled high by an internal 1-k resistor,

which in turn pulls the nCONFIGpin high to begin configuration. If you do not use the

nINIT CONFpin, disconnect the nINIT CONFpin, and pull the nCONFIGpin of the FPGA

to V_CCeither directly or through a resistor.

_

CONF. The nINIT

_

CONFpin of the EPC2 device can be connected to the

_

CONFJTAG instruction to begin

_

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Device Configuration

Page 7

The EPC2 device’s OEand nCSpins have internal programmable pull-up resistors. If

you use internal pull-up resistors, do not use external pull-up resistors on these pins.

The internal pull-up resistors are set by default in the Quartus II software. To turn off

the internal pull-up resistors, check the Disable nCS and OE pull-ups on

configuration device option when you generate programming files.

The configuration device’s OEand nCSpins control the tri-state buffer on its DATA

output pin and enable the address counter and oscillator. When the OEpin is driven

low, the configuration device resets the address counter and tri-states its DATApin. The

nCSpin controls the DATAoutput of the configuration device. If the nCSpin is held high

after the OEreset pulse, the counter is disabled and the DATAoutput pin is tri-stated. If

the nCSpin is driven low after the OEreset pulse, the counter and DATAoutput pin are

enabled. When OEis driven low again, the address counter is reset and the DATA

output pin is tri-stated, regardless of the state of the nCSpin.

If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2

configuration device, you can cascade multiple EPC1 or EPC2 devices together. If

multiple EPC1 or EPC2 devices are required, the nCASCand nCSpins provide

handshaking between the configuration devices.

1

EPC1441 and EPC1064/EPC1064V devices cannot be cascaded.

When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II,

FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with

cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain

determines its mode of operation. The first configuration device in the chain is the

master, while subsequent configuration devices are slaves. The nINIT

EPC2 master device can be connected to the nCONFIGpin of the FPGAs, which allows

the INIT CONFJTAG instruction to begin FPGA configuration. The nCSpin of the

master configuration device is connected to the CONF DONEpin of the FPGAs, while its

_CONFpin of the

_

nCASCpin is connected to the nCSpin of the next slave configuration device in the

chain. Additional EPC1 or EPC2 devices can be chained together by connecting the

nCASCpin to the nCSpin of the next EPC1 or EPC2 slave device in the chain. The last

device’s nCSinput comes from the previous device, while its nCASCpin is left floating.

All other configuration pins, DCLK, DATA, and OE, are connected to every device in the

chain.

f For more information about configuration interface connections, including pull-up

resistor values, supply voltages, and MSELpin setting, refer to the configuration

chapter in the appropriate device handbook.

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 8

Device Configuration

Figure 3 shows the basic configuration interface connections between a configuration

device chain and the Altera FPGA.

Figure 3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices ⁽¹⁾

V

CC

Slave

Configuration

Device

Master

Configuration

Device

(3)

(2)

(3)

FPGA

DCLK

DATA0

nSTATUS

CONF_DONE

nCONFIG

DCLK

DATA

OE (3)

nCS (3)

nINIT_CONF

DCLK

DATA

nCS

nCASC

N.C.

nCASC

n

(2)

OE

MSEL

N.C.

nCEO

nCE

GND

Notes to Figure 3:

(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.

(2) The nINIT CONFpin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up

resistor is not required on the nINIT CONF/nCONFIGline. The nINIT CONFpin does not need to be connected if its functionality is not used.

If the nINIT CONFpin is not used or unavailable, nCONFIGmust be pulled to V_CCeither directly or through a resistor.

_

(3) EPC2devices have internal programmable pull-up resistors on OEand nCSpins. If internal pull-up resistors are used, donot use external pull-up

resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check

the Disable nCS and OE pull-ups on configuration device option when you generate programming files.

When the first device in a configuration device chain is powered-up or reset, its nCS

pin is driven low because it is connected to the CONF_DONEpin of the FPGA. Because

both OEand nCSpins are low, the first device in the chain recognizes it as the master

device and controls configuration. Since the slave devices’ nCSpin is fed by the

previous devices’ nCASCpin, its nCSpin is high after power-up and reset. In the slave

configuration devices, the DATAoutput is tri-stated and DCLKis an input. During

configuration, the master device supplies the clock through DCLKto the FPGA and to

any slave configuration devices. The EPC1 or EPC2 master device also provides the

first stream of data to the FPGA during multi-device configuration. After the EPC1 or

EPC2 master device finishes sending configuration data, it tri-states its DATApin to

avoid contention with other configuration devices. The EPC1 or EPC2 master device

also drives its nCASCpin low, which pulls the nCSpin of the next device low. This

action signals the EPC1 or EPC2 slave device to start sending configuration data to the

FPGAs.

The EPC1 or EPC2 master device clocks all slave configuration devices until

configuration is complete. When all configuration data is transferred and the nCSpin

on the EPC1 or EPC2 master device is driven high by the FPGA’s CONF_DONEpin, the

EPC1 or EPC2 master device then goes into zero-power (idle) state. The EPC2 master

device drives DATAhigh and DCLKlow, while the EPC1 and EPC1441 device tri-state

DATAand drive DCLKlow.

If the nCSpin on the EPC1 or EPC2 master device is driven high before all

configuration data is transferred, the EPC1 or EPC2 master device drives its OEsignal

low, which in turn drives the FPGA’s nSTATUSpin low, indicating a configuration

error. Additionally, if the configuration device generates its data and detects that the

CONF

_DONEpin has not gone high, it recognizes that the FPGA has not configured

successfully. EPC1 and EPC2 devices wait for 16 DCLKcycles after the last

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Power and Operation

Page 9

configuration bit was sent for the CONF

_

DONEpin to reach a high state. In this case, the

configuration device pulls its OEpin low, which in turn drives the target device’s

nSTATUSpin low. Configuration automatically restarts if the Auto-restart

configuration on error option is turned on in the Quartus II software from the

General tab of the Device & Pin Options dialog box or the MAX+PLUS II software’s

Global Project Device Options dialog box (Assign menu).

f For more information about FPGA configuration and configuration interface

connections between configuration devices and Altera FPGAs, refer to the

configuration chapter in the appropriate device handbook.

Power and Operation

This section describes power-on reset (POR) delay, error detection, and 3.3-V and

5.0-V operation of Altera configuration devices.

Power-On Reset

During initial power-up, a POR delay occurs to permit voltage levels to stabilize.

When configuring an FPGA with one EPC1, EPC2, or EPC1441 device, the POR delay

occurs inside the configuration device and the POR delay is a maximum of 200 ms.

When configuring a FLEX 8000 device with one EPC1213, EPC1064, or EPC1064V

device, the POR delay occurs inside the FLEX 8000 device and the POR delay is

typically 100 ms, with a maximum of 200 ms.

During POR, the configuration device drives its OEpin low. This low signal delays

configuration because the OEpin is connected to the target FPGA’s nSTATUSpin. When

the configuration device completes POR, it releases its open-drain OEpin, which is

then pulled high by a pull-up resistor.

1

You should power up the FPGA before the configuration device exits POR to avoid

the master configuration device from entering slave mode.

If the FPGA is not powered up before the configuration device exits POR, the

CONF_DONE/nCSline is high because of the pull-up resistor. When the configuration

device exits POR and releases OE, it sees nCShigh, which signals the configuration

device to enter slave mode. Therefore, configuration will not begin because the DATA

output is tri-stated and DCLKis an input pin in slave mode.

Error Detection Circuitry

The EPC1, EPC2, and EPC1441 configuration devices have built-in error detection

circuitry for configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, or

Stratix II GX devices.

Built-in error detection circuitry uses the nCSpin of the configuration device, which

monitors the CONF_DONEpin on the FPGA. If the nCSpin on the EPC1 or EPC2 master

device is driven high before all configuration data is transferred, the EPC1 or EPC2

master device drives its OEsignal low, which in turn drives the FPGA’s nSTATUSpin

low, indicating a configuration error. Additionally, if the configuration device

generates its data and detects that the CONF

_

DONEpin has not gone high, it recognizes

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 10

Power and Operation

that the FPGA has not configured successfully. EPC1 and EPC2 devices wait for

16 DCLKcycles after the last configuration bit was sent for the CONF DONEpin to reach a

_

high state. In this case, the configuration device pulls its OEpin low, which in turn

drives the target device’s nSTATUSpin low. Configuration automatically restarts if the

Auto-restart configuration on error option is turned on in the Quartus II software

from the General tab of the Device & Pin Options dialog box or the MAX+PLUS II

software’s Global Project Device Options dialog box (Assign menu).

In addition, if the FPGA detects a cyclic redundancy check (CRC) error in the received

data, it will flag the error by driving the nSTATUSsignal low. This low signal on

nSTATUSdrives the OEpin of the configuration device low, which resets the

configuration device. CRC checking is performed when configuring all Altera FPGAs.

3.3-V or 5.0-V Operation

Power the EPC1, EPC2, and EPC 1441 configuration device at 3.3 V or 5.0 V. For each

configuration device, an option must be set for the 3.3-V or 5.0-V operation.

For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is controlled

by a programming bit in the .pof. The Low-Voltage mode option in the Options tab of

the Configuration Device Options dialog box in the Quartus II software or the Use

Low-Voltage Configuration EPROM option in the Global Project Device Options

dialog box (Assign menu) in the MAX+PLUS II software sets this parameter. For

example, EPC1 devices are programmed automatically to operate in 3.3-V mode when

configuring FLEX 10KA devices, which have a V_CCvoltage of 3.3 V. In this example,

the EPC1 device’s VCCpin is connected to a 3.3-V power supply.

For EPC2 devices, this option is set externally by the VCCSELpin. In addition, the EPC2

device has an externally controlled option, set by the VPPSELpin, to adjust the

programming voltage to 5.0 V or 3.3 V. The functions of the VCCSELand VPPSELpins

are described below. These pins are only available in the EPC2 devices.

■

VCCSELpin—For EPC2 configuration devices, 5.0-V or 3.3-V operation is controlled

by the VCCSELoption pin. The device functions in 5.0-V mode when VCCSELis

connected to GND and 3.3-V mode when VCCSELis connected to V_CC

.

■

VPPSELpin—The V_PPprogramming power pin of the EPC2 device is normally tied

to V_CC. For EPC2 devices operating at 3.3 V, it is possible to improve ISP time by

setting V_PPto 5.0 V. For all other configuration devices, V_PPmust be tied to V_CC

.

The VPPSELpin of the EPC2 device must be set in accordance with the VPPpin of

the EPC2 device. If the VPPpin is supplied by a 5.0-V power supply, VPPSELmust

be connected to GND and if the VPPpin is supplied by a 3.3-V power supply,

VPPSELmust be connected to V_CC

.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Power and Operation

Page 11

Table 3 lists the relationship between the V_CCand V_PPvoltage levels and the required

logic level for VCCSELand VPPSELpins. A high logic level means the pin should be

connected to V_CC, while a low logic level means the pin should be connected to GND.

Table 3. VCCSEL and VPPSEL Pin Functions on the EPC2 Device

VCC Voltage Level

(V)

VPP Voltage Level

(V)

VCCSEL Pin Logic

Level

VPPSEL Pin Logic

Level

3.3

5.0

3.3

5.0

High

Low

High

Low

At a 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except for DATA, DCLK, and

nCASCpins. The DATAand DCLKpins are used only to interface between the EPC2

device and the FPGA it is configuring. Table 4 lists the voltage tolerences of all EPC2

device pins.

Table 4. EPC2 Device Input and Bidirectional Pin Voltage Tolerance

5.0-V Operation

3.3-V Operation

5.0-V Tolerant

3.3-V Tolerant

5.0-V Tolerant

3.3-V Tolerant

DATA

DCLK

v

—

v

n

CASC

OE

CS

n

VCCSEL

VPPSEL

nINIT_CONF

TDI

TMS

TCK

If one EPC1, EPC2, or EPC1441 configuration device is powered at 3.3 V, the nSTATUS

and CONF DONEpull-up resistors must be connected to 3.3 V. If these configuration

devices are powered at 5.0 V, the nSTATUSand CONF

connected to either 3.3 V or 5.0 V.

_

DONEpull-up resistors can be

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 12

Programming and Configuration File Support

The Quartus II and MAX+PLUS II softwares provide programming support for Altera

configuration devices. During compilation, the Quartus II and MAX+PLUS II

softwares automatically generates a .pof, which is used to program the configuration

devices. In a multi-device configuration, the software combines the programming

files for multiple ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II,

FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices into one or

more configuration devices. The software allows you to select the appropriate

configuration device to store the data for each FPGA.

All Altera configuration devices are programmable using Altera programming

hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition,

many third-party programmers offer programming hardware that supports Altera

configuration devices.

1

An EPC2 device can be programmed with a .pof generated for an EPC1 or EPC1441

device. An EPC1 device can be programmed with a .pof generated for an EPC1441

device.

EPC2 configuration devices can be programmed in-system through its

industry-standard four-pin JTAG interface. ISP capability in the EPC2 devices provide

ease in prototyping and FPGA functionality. When programming multiple EPC2

devices in a JTAG chain, the Quartus II and MAX+PLUS II softwares and other

programming methods employ concurrent programming to simultaneously program

multiple devices and reduce programming time. EPC2 devices can be programmed

and erased up to 100 times.

After programming an EPC2 device in-system, FPGA configuration is initiated by the

INIT

_CONFJTAG instruction of the EPC2 device. For more information, refer to

Table 6.

f For more information about programming and configuration support, refer to the

following documents:

■

Altera Programming Hardware Data Sheet

USB-Blaster Download Cable User Guide

MasterBlaster Serial/USB Communications Cable User Guide

ByteBlaster II Download Cable User Guide

ByteBlasterMV Download Cable User Guide

BitBlaster Serial Download Cable Data Sheet

You can also program the configuration devices using the Quartus II or MAX+PLUS II

software with the APU or the appropriate configuration device programming adapter.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Programming and Configuration File Support

Page 13

Table 5 lists the programming adapter to use with each configuration device.

Table 5. Programming Adapters

Device

Package

20-pin J-Lead

32-pin TQFP

8-pin DIP

Adapter

PLMJ1213

PLMT1213

PLMJ1213

PLMT1064

EPC2

EPC1

20-pin J-Lead

8-pin DIP

EPC1441

20-pin J-Lead

32-pin TQFP

To program Altera configuration devices using the Quartus II software and the APU,

follow these steps:

1. Choose the Quartus II Programmer (Tools menu).

2. Load the appropriate .pof by clicking Add. The Device column displays the

device for the current programming file.

3. Insert a blank configuration device into the programming adapter’s socket.

4. Turn on the Program/Configure. You can also turn on Verify to verify the contents

of a programmed device against the programming data loaded from a

programming file.

5. Click Start.

6. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device.

To program Altera configuration devices using the MAX+PLUS II software and the

APU, follow these steps:

1. Open the MAX+PLUS II Programmer.

2. Load the appropriate .pof using the Select Programming File dialog box (File

menu). By default, the Programmer loads the current project’s .pof. The Device

field displays the device for the current programming file.

3. Insert a blank configuration device into the programming adapter’s socket.

4. Click Program.

5. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device.

If you are cascading EPC1 or EPC2 devices, you must generate multiple .pof. The first

device .pof have the same name as the project, while the second device .pof have the

same name as the first, but with a “_1” extension (e.g., top_1.pof).

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 14

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

The EPC2 device provides JTAG BST circuitry that complies with the IEEE Std.

1149.1-1990 specification. You can perform JTAG BST before or after configuration, but

not during configuration. Table 6 lists the JTAG instructions supported by the EPC2

device.

Table 6. EPC2 Device JTAG Instructions

JTAG Instruction

OPCODE

Description

Allows a snapshot of a signal at the device pins to be captured and

examined during normal device operation and permits an initial data

pattern output at the device pins.

SAMPLE/PRELOAD

00 0101 0101

Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing

results at the input pins.

EXTEST

BYPASS

00 0000 0000

11 1111 1111

Places the 1-bit bypass register between the TDIand TDOpins,

which allows the BST data to pass synchronously through a selected

device to adjacent devices during normal device operation.

Selects the device IDCODEregister and places it between the TDI

and TDOpins, allowing the device IDCODEto be serially shifted out of

the TDOpin. The device IDCODEfor the EPC2 configuration device is

shown below:

IDCODE

00 0101 1001

00 0111 1001

0000 0001000000000010 00001101110 1

Selects the USERCODEregister and places it between the TDIand

TDOpins, allowing the USERCODEto be serially shifted out of the

TDO pin. The 32-bit USERCODEis a programmable user-defined

pattern.

USERCODE

Initiates the FPGA re-configuration process by pulsing the

nINIT_CONFpin low, which is connected to the FPGAs nCONFIG

pins. After this instruction is updated, the nINIT_CONFpin is pulsed

low when the JTAG state machine enters the Run-Test/Idle state. The

nINIT_CONFpin is then released and nCONFIGis pulled high by the

resistor after the JTAG state machine goes out of Run-Test/Idle state.

The FPGA configuration starts after the nCONFIGpin goes high. As a

result, the FPGA is configured with the new configuration data stored

in the configuration device. You can add this function to your

programming file (.pof, .jam, .jbc) in the Quartus II software by

enabling the Initiate configuration after programming option in the

Programmer options window (Options menu). This instruction is

also used by the MAX+PLUS II software, .jam files, and .jbc files.

INIT_CONF

00 0110 0001

These instructions are used when programming an EPC2 device

using JTAG ports with a USB-Blaster, MasterBlaster, ByteBlaster II,

EthernetBlaster, or ByteBlasterMV download cable, or using a .jam,

.jbc, or .svf file using an embedded processor.

ISP Instructions

—

f For more information, refer to AN39: IEEE 1149.1 JTAG Boundary-Scan Testing in Altera

Devices.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

Page 15

Figure 4 shows the timing requirements for the JTAG signals.

Figure 4. EPC2 Device JTAG Waveforms

TMS

TDI

t_JCP

t_JCH

t_JCL

t_JPH

t_JPSU

TCK

TDO

t

t_JPXZ

t_JPCO

JPZX

t_JSSU

t_JSH

Signal

to be

Captured

t_JSZX

t_JSCO

t_JSXZ

Signal

to be

Driven

Table 7 lists the timing parameters and values for configuration devices.

Table 7. JTAG Timing Parameters and Values

Symbol

Parameter

Min

100

50

20

45

—

20

Max

—

25

—

25

Unit

t_JCP

TCKclock period

ns

t_JCH

TCKclock high time

TCKclock low time

t_JCL

t_JPSU

t_JPH

JTAG port setup time

JTAG port hold time

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

45

t_JSCO

t_JSZX

t_JSXZ

Update register clock to output

Update register high impedance to valid output

Update register valid output to high impedance

—

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 16

Timing Information

Figure 5 shows the timing waveform when using a configuration device.

Figure 5. Timing Waveform Using a Configuration Device

nINIT_CONF or VCC/nCONFIG

t_POR

OE/nSTATUS

nCS/CONF_DONE

t_CH

t_DSU

t_CL

DCLK

DATA

t_OEZX

t_DH

D₂

D₀

D₁

D₃

D_n

(1)

t_CO

User I/O

User Mode

Tri-State

INIT_DONE

Note to Figure 5:

(1) The EPC2 device drives DCLKlowand DATAhigh after configuration. The EPC1 and EPC1441 devices drive DCLKlow and tri-state DATAafter

configuration.

Table 8 lists the timing parameters when using EPC2 devices at 3.3 V.

Table 8. Timing Parameters when Using EPC2 devices at 3.3 V

Symbol

t_POR

t_OEZX

t_CE

t_DSU

t_DH

Parameter

Min

—

30

0

Typ

—

7.7

65

—

Max

200

80

Units

ms

ns

(1)

POR delay

OE high to DATAoutput enabled

OE high to first rising edge on DCLK

Datasetup time before rising edge on DCLK

Datahold time after rising edge on DCLK

DCLKto DATAout

300

—

ns

—

ns

t_CO

—

5

30

ns

t_CDOE

f_CLK

t_MCH

t_MCL

t_SCH

t_SCL

t_CASC

t_CCA

t_OEW

t_OEC

t_NRCAS

DCLKto DATAenable/disable

30

ns

DCLKfrequency

12.5

100

—

MHz

ns

DCLKhigh time for the first device in the configuration chain

DCLKlow time for the first device in the configuration chain

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

DCLKrising edge to nCASC

40

—

100

—

ns

—

ns

25

ns

n

CSto nCASCcascade delay

15

ns

OE low pulse width (reset) to guarantee counter reset

OE low (reset) to DCLKdisable delay

OE low (reset) to nCASCdelay

—

ns

30

ns

30

ns

Note to Table 8:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Timing Information

Page 17

Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.

Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V

Symbol Parameter

t_POR

t_OEZX

t_CE

t_DSU

t_DH

Min

—

30

0

Typ

—

4

Max

200

80

Units

ms

ns

(1)

POR delay

OE high to DATAoutput enabled

OE high to first rising edge on DCLK

Datasetup time before rising edge on DCLK

Datahold time after rising edge on DCLK

DCLKto DATAout

300

—

ns

—

ns

t_CO

—

2

30

ns

t_CDOE

f_CLK

t_MCH

t_MCL

t_SCH

t_SCL

t_CASC

t_CCA

t_OEW

t_OEC

t_NRCAS

DCLKto DATAenable/disable

30

ns

DCLKfrequency

10

MHz

ns

DCLKhigh time for the first device in the configuration chain

DCLKlow time for the first device in the configuration chain

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

DCLKrising edge to nCASC

50

—

100

—

125

—

250

—

ns

—

ns

25

ns

nCSto nCASCcascade delay

15

ns

OE low pulse width (reset) to guarantee counter reset

OE low (reset) to DCLKdisable delay

OE low (reset) to nCASCdelay

—

ns

30

ns

30

ns

Note to Table 9:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.

Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at

5.0 V.

Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)

Symbol

t_POR

t_OEZX

t_CE

t_DSU

t_DH

Parameter

Min

—

30

0

Typ

—

10

50

—

Max

200

50

Units

ms

ns

(1)

POR delay

OE high to DATAoutput enabled

OE high to first rising edge on DCLK

Datasetup time before rising edge on DCLK

Datahold time after rising edge on DCLK

DCLKto DATAout

200

—

ns

—

ns

t_CO

—

6.7

30

—

20

ns

t_CDOE

f_CLK

t_MCH

t_MCL

t_SCH

t_SCL

t_CASC

t_CCA

DCLKto DATAenable/disable

20

ns

DCLKfrequency

16.7

75

MHz

ns

DCLKhigh time for the first device in the configuration chain

DCLKlow time for the first device in the configuration chain

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

DCLKrising edge to nCASC

75

ns

—

ns

—

ns

20

ns

nCSto nCASCcascade delay

10

ns

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 18

Timing Information

Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2)

Symbol

t_OEW

Parameter

OE low pulse width (reset) to guarantee counter reset

OE low (reset) to DCLKdisable delay

Min

100

—

Typ

—

Max

—

Units

ns

t_OEC

20

ns

t_NRCAS

OE low (reset) to nCASCdelay

—

25

ns

Note to Table 10:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.

Table 11 lists the timing parameters when using EPC1, EPC1064, EPC1064V, EPC1213,

and EPC1441 devices when configuring the FLEX 8000 device.

Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441

Devices

EPC1064 and

EPC1213

EPC1 and

EPC1441

EPC1064V

Symbol

Parameter

Unit

Min

Max

75

Min

—

100

0

Max

50

—

75

—

6

Min

Max

50

—

75

—

8

t_OEZX

OE high to DATAoutput enabled

—

50

0

ns

MHz

ns

t_CSZX

t_CSXZ

t_CSS

t_CSH

t_DSU

t_DH

n

CSlow to DATAoutput enabled

—

75

—

100

—

4

CS high to DATAoutput disabled

CSlow setup time to first DCLKrising edge

CSlow hold time after DCLKrising edge

150

0

Datasetup time before rising edge on DCLK

Datahold time after rising edge on DCLK

DCLKto DATAout delay

75

50

0

50

0

t_CO

—

160

—

80

—

100

—

100

—

50

—

100

—

t_CK

Clock period

240

—

f_CK

Clock frequency

t_CL

DCLKlow time

120

—

75

—

90

75

150

—

50

—

60

50

100

—

50

—

50

100

t_CH

DCLKhigh time

t_XZ

OE low or nCS high to DATAoutput disabled

OE pulse width to guarantee counter reset

Last DCLK+ 1 to nCASClow delay

Last DCLK+ 1 to DATAtri-state delay

t_OEW

t_CASC

t_CKXZ

t_CEOUT

150

—

nCShigh to nCASChigh delay

—

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Operating Conditions

Page 19

Operating Conditions

Table 12 through Table 19 list information about absolute maximum ratings,

recommended operating conditions, DC operating conditions, and capacitance for

configuration devices.

(1)

Table 12. Absolute Maximum Ratings

Symbol Parameter

Supply voltage

Conditions

Min

–2.0

—

Max

7.0

50

Unit

V

(2)

V_CC

With respect to GND

(2)

V_I

DC input voltage

With respect to GND

V

I_MAX

I_OUT

P_D

DC V_CCor GND current

DC output current, per pin

Power dissipation

—

mA

mW

° C

–25

—

25

—

250

150

135

T_STG

T_AMB

T_J

Storage temperature

Ambient temperature

Junction temperature

No bias

–65

—

Under bias

Table 13. Recommended Operating Conditions

Symbol

Parameter

Supply voltage for 5.0-V operation

Supply voltage for 3.3-V operation

Input voltage

Conditions

Min

Max

Unit

V

4.75

(4.50)

5.25

(5.50)

(3) (4)

,

V_CC

(3) (4)

,

3.0 (3.0)

3.6 (3.6)

V

V_CC+ 0.3

V_I

With respect to GND

–0.3

V

(5)

V_O

Output voltage

—

For commercial use

For industrial use

—

0

V_CC

70

85

20

V

° C

ns

T_A

Operating temperature

–40

—

t_R

t_F

Input rise time

Input fall time

—

ns

Table 14. DC Operating Conditions

Symbol

Parameter

High-level input voltage

Low-level input voltage

Conditions

Min

2.0

Max

Unit

V

V_CC+ 0.3

V_IH

—

(5)

V_IL

–0.3

2.4

0.8

—

V

5.0-V mode high-level TTL output

voltage

(6)

I_OH= –4 mA DC

V

V_OH

3.3-V mode high-level CMOS

output voltage

(6)

I_OH= –0.1 mA DC

V_CC– 0.2

—

V

(6)

V_OL

I_I

Low-level output voltage

Input leakage current

I_OL= 4 mA DC

—

0.4

10

V

V_I= V_CCor GND

V_O= V_CCor GND

–10

A

I_OZ

Tri-state output off-state current

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 20

Operating Conditions

Table 15. EPC1064, EPC1064V, and EPC1213 Devices I_CCSupply Current Values

Unit

Symbol

Parameter

Conditions

Min

—

Typ

100

10

Max

I_CC0

I_CC1

V_CCsupply current (standby)

—

200

50

A

V_CCsupply current (during configuration)

—

mA

Table 16. EPC2 Device Values

Symbol Parameter

Conditions

Min

Typ

Max

Unit

I_CC0

V_CCsupply current (standby) V_CC= 5.0 V or 3.3 V

—

50

100

µA

V_CCsupply current (during

V_CC= 5.0 V or 3.3 V

configuration)

I_CC1

—

18

1

50

—

mA

Internal pull up (OE, nCS

,

R_CONF

Configuration pins

k

nINIT_CONF)

Table 17. EPC1 Device I_CCSupply Current Values

Symbol

Parameter

Conditions

Min

—

Typ

50

30

10

Max

100

50

Unit

µA

I_CC0

V_CCsupply current (standby)

—

V_CC= 5.0 V

—

mA

I_CC1

V_CCsupply current (during configuration)

V_CC= 3.3 V

—

16.5

Table 18. EPC1441 Device I_CCSupply Current Values

Symbol

Parameter

Conditions

—

Min

—

Typ

30

15

5

Max

60

Unit

µA

I_CC0

V_CCsupply current (standby)

I_CC1

V_CCsupply current (during configuration)

V_CC= 5.0 V

V_CC= 3.3 V

—

30

mA

—

10

Table 19. Capacitance ⁽⁷⁾

Symbol

Parameter

Conditions

Min

—

Max

10

Unit

pF

C_IN

Input pin capacitance

Output pin capacitance

V_IN= 0 V, f = 1.0 MHz

V_OUT= 0 V, f = 1.0 MHz

C_OUT

—

10

pF

Notes to Table 12 through Table 19:

(1) For more information, refer to the Operating Requirements for Altera Devices Datasheet.

(2) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than

100 mA and periods shorter than 20 ns under no-load conditions.

(3) Numbers in parentheses are for industrial temperature range devices.

(4) Maximum V_CCrise time is 100 ms.

(5) Certain EPC2 device pins are driven to 5.75 V when operated with a 3.3-V V_CC. For more information, refer to Table 4 on page 11.

(6) The I_OHparameter refers to high-level TTL or CMOS output current and the I_OLparameter refers to low-level TTL or CMOS output current.

(7) Capacitance is sample tested only.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Pin Information

Page 21

Pin Information

Table 20 lists the pin functions of the EPC1, EPC2, and EPC1441 devices during device

configuration.

f For more information about pin information of EPC devices, refer to the Enhanced

Configuration (EPC) Devices Datasheet.

f For more information about pin information of EPCS devices, refer to the Serial

Configuration (EPCS) Devices Datasheet.

Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3)

Pin Number

Pin Name

Pin Type

Description

8-Pin

20-Pin

PLCC

32-Pin

(1)

(2)

PDIP

TQFP

Serial data output. The DATApin connects to the DATA0pin

of the FPGA. DATAis latched into the FPGA on the rising

edge of DCLK

.

DATA

1

2

31

Output

The DATApin is tri-stated before configuration and when

the nCSpin is high. After configuration, the EPC2 device

drives DATAhigh, while the EPC1 and EPC1441 device

tri-state DATA

.

Clock output when configuring with a single configuration

device or when the configuration device is the first

(master) device in a chain. Clock input for the next (slave)

configuration devices in a chain. The DCLKpin connects to

the DCLKpin of the FPGA.

Rising edges on DCLKincrement the internal address

counter and present the next bit of data on the DATApin.

The counter is incremented only if the OEinput is held

high, the nCSinput is held low, and all configuration data

has not been transferred to the target device.

DCLK

2

4

2

Bidirectional

After configuration or when OE is low, the EPC1, EPC2 and

EPC1441 device drive DCLKlow.

Output enable (active high) and reset (active low). The OE

pin connects to the nSTATUSpin of the FPGA.

A low logic level resets the address counter. A high logic

level enables DATAand the address counter to count. If this

pin is low (reset) during configuration, the internal

Open-drain

oscillator becomes inactive and DCLKdrives low. For more

OE

3

8

7

bidirectional information, refer to “Error Detection Circuitry” on page 9.

The OE pin has an internal programmable 1-k resistor in

EPC2 devices. If internal pull-up resistors are used, do not

use external pull-up resistors on these pins. You can

disable the internal pull-up resistors through the Disable

nCS and OE pull-ups on configuration device option.

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 22

Pin Information

Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 2 of 3)

Pin Number

Pin Name

Pin Type

Description

8-Pin

20-Pin

PLCC

32-Pin

(1)

(2)

PDIP

TQFP

Chip select input (active low). The nCSpin connects to the

DONEpin of the FPGA.

CONF

_

A low input allows DCLKto increment the address counter

and enables DATAto drive out. If the EPC1 or EPC2 device

is reset (OEpulled low) while nCS is low, the device

initializes as the master device in a configuration chain. If

the EPC1 or EPC2 device is reset (OEpulled low) while nCS

is high, the device initializes as a slave device in the chain.

nCS

4

9

10

Input

The nCSpin has an internal programmable 1-k resistor

in EPC2 devices. If internal pull-up resistors are used, do

not use external pull-up resistors on these pins. You can

disable the internal pull-up resistors through the Disable

nCS and OE pull-ups on configuration device option.

Cascade select output (active low).

This output goes low when the address counter has

reached its maximum value. When the address counter has

reached its maximum value, the configuration device has

sent all its configuration data to the FPGA. In a chain of

EPC1 or EPC2 devices, the nCASCpin of one device is

connected to the nCSpin of the next device, which permits

DCLKto clock data from the next EPC1 or EPC2 device in

the chain. For single EPC1 or EPC2 device and the last

device in the chain, nCASC is left floating.

nCASC

6

12

15

Output

This pin is only available in EPC1 and EPC2 devices, which

support data cascading.

Allows the INIT

configuration. The nINIT

CONFIGpin of the FPGA.

_

CONFJTAG instruction to initiate

_CONFpin connects to the

n

If multiple EPC2 devices are used to configure an FPGA,

the nINIT CONFof the first EPC2 device pin is tied to the

FPGA’s nCONFIGpin, while subsequent devices'

INIT CONFpins are left floating.

_

Open-Drain

Output

nINIT

_

CONF

N/A

13

16

n

_

The INIT CONFpin has an internal 1-k pull-up resistor

_

that is always active in EPC2 devices.

This pin is only available in EPC2 devices.

JTAG data input pin. Connect this pin to V_CCif the JTAG

circuitry is not used.

TDI

TDO

TMS

N/A

11

1

13

28

25

Input

This pin is only available in EPC2 devices.

JTAG data output pin. Do not connect this pin if the JTAG

circuitry is not used.

Output

Input

This pin is only available in EPC2 devices.

JTAG mode select pin. Connect this pin to V_CCif the JTAG

circuitry is not used.

19

This pin is only available in EPC2 devices.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Pin Information

Page 23

Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 3 of 3)

Pin Number

Pin Name

Pin Type

Description

8-Pin

20-Pin

PLCC

32-Pin

(1)

(2)

PDIP

TQFP

JTAG clock pin. Connect this pin to GND if the JTAG

circuitry is not used.

TCK

N/A

3

32

Input

This pin is only available in EPC2 devices.

Mode select for V_CCsupply. VCCSELmust be connected to

GND if the device uses a 5.0-V power supply (V_CC= 5.0 V).

VCCSELmust be connected to V_CCif the device uses a

3.3-V power supply (V_CC= 3.3 V).

VCCSEL

VPPSEL

VPP

N/A

5

3

Input

Power

This pin is only available in EPC2 devices.

Mode select for V_PP. supply. VPPSELmust be connected to

GND if V_PPuses a 5.0-V power supply (V_PP= 5.0 V).

VPPSELmust be connected to V_CCif V_PPuses a 3.3-V

power supply (V_PP= 3.3 V).

14

18

17

23

This pin is only available in EPC2 devices.

Programming power pin. For the EPC2 device, this pin is

normally tied to V_CC. If the V_CCof the EPC2 device is 3.3 V,

tie V_PPto 5.0 V to improve ISP time. For EPC1 and

EPC1441 devices, V_PPmust be tied to V_CC.

This pin is only available in EPC2 devices.

Power pin.

VCC

7, 8

5

20

10

27

12

Power

Ground pin. Place a 0.2-µF decoupling capacitor between

the VCC and GND pins.

GND

Ground

Notes to Table 20:

(1) This package is available for EPC1 and EPC1441 devices only.

(2) This package is available for EPC2 and EPC1441 devices only.

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 24

Package

Figure 6 and Figure 7 show the configuration device package pin-outs.

Figure 6. EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441 Package Pin-Out Diagrams ⁽¹⁾

32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

N.C.

VCC

N.C.

1

2

3

4

5

6

7

8

N.C.

DCLK

N.C.

OE

3

2

1

20 19

18

DCLK

N.C.

4

5

6

7

8

VCC

N.C.

17

16

15

14

DATA

DCLK

OE

1

2

3

4

8

7

6

5

VCC

N.C.

VCC

nCASC(2)

GND

N.C.

OE

N.C.

nCS

N.C.

9

10 11 12 13 14 15 16

9

10 11 12 13

32-Pin TQFP

20-Pin PLCC

8-Pin PDIP

EPC1441

EPC1064

EPC1064V

EPC1

EPC1441

EPC1213

EPC1064

EPC1064V

EPC1441

EPC1213

EPC1064

EPC1064V

Notes to Figure 6:

(1) EPC1 and EPC1441 devices are one-time programmable devices. ISP is not available in these devices.

(2) The nCASCpin is available on EPC1 devices, which allows them to be cascaded. For EPC1441 devices, nCASCis a reserved pin and should

be left unconnected.

Figure 7. EPC2 Package Pin-Out Diagrams

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

N.C.

DCLK

VCCSEL

N.C.

24

23

22

21

20

19

18

N.C.

VPP

N.C.

3

2

1

20 19

18

DCLK

VCCSEL

N.C.

4

5

6

7

8

VPP

N.C.

17

16

15

14

N.C.

OE

N.C.

VPPSEL

8

17

16

N.C.

OE

9

10 11 12 13 14 15

9

10 11 12 13

32-Pin TQFP

20-Pin PLCC

f For more information about package outlines and drawings, refer to the Package and

Thermal Resistance page.

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

Ordering Codes

Page 25

Ordering Codes

Table 21 lists the ordering codes for the EPC1, EPC2, and EPC1441 configuration

devices.

Table 21. Configuration Device Ordering Codes

Device

EPC1

Package

Temperature

Commercial

Industrial

Ordering Code

EPC1LC20

20-pin PLCC

8-pin PDIP

32-pin TQFP

20-pin PLCC

32-pin TQFP

20-pin PLCC

8-pin PDIP

EPC1

EPC1LI20

EPC1

Commercial

Industrial

EPC1PC8

EPC1

EPC1PI8

EPC2

Commercial

Industrial

EPC2TC32

EPC2

EPC2TI32

EPC2

Commercial

Industrial

EPC2LC20

EPC2

EPC2LI20

EPC1441

Commercial

Industrial

EPC1441TC32

EPC1441TI32

EPC1441LC20

EPC1441LI20

EPC1441PC8

EPC1441PI8

Commercial

Industrial

Commercial

Industrial

Document Revision History

Table 22 lists the revision history for this document.

Table 22. Document Revision History

Date

Version

Changes

January 2012

3.0

Minor text edits.

■ Updated “Features” section.

December 2009

2.4

■ Removed “Referenced Documents” section.

■ Updated “Features” and “IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing”

sections.

■ Updated Table 5–2 and Table 5–16.

■ Added “Referenced Documents” section.

■ Updated new document format.

October 2008

2.3

April 2007

2.2

2.0

1.0

Added document revision history.

July 2004

Added Stratix II and Cyclone II device information throughout chapter.

Initial Release.

September 2003

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

Page 26

Document Revision History

Configuration Devices for SRAM-Based LUT Devices

January 2012 Altera Corporation

型号:	EPC1PC8
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	ALTERA CORP
零件包装代码：	DIP
包装说明：	DIP, DIP8,.3
针数：	8
Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.61
风险等级：	3.79
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	2131650
Samacsys Pin Count：	8
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Dual-In-Line Packages
Samacsys Footprint Name：	8-Pin Plastic Dual In-Line Package (PDIP)—Wire Bond
Samacsys Released Date：	2019-12-27 06:19:51
Is Samacsys：	N
其他特性：	IT CAN ALSO OPERATE AT 5V SUPPLY
最大时钟频率 (fCLK)：	10 MHz
I/O 类型：	COMMON
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0
长度：	9.398 mm
内存密度：	1046496 bit
内存集成电路类型：	CONFIGURATION MEMORY
内存宽度：	1
湿度敏感等级：	1
功能数量：	1
端子数量：	8
字数：	1046496 words
字数代码：	1046496
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	1046496X1
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	4.318 mm
子类别：	OTP ROMs
最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	NO
技术：	MOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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