FAN7930CMX原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号FAN7930CMX的概述

FAN7930CMX芯片概述 FAN7930CMX是一款高性能的电源管理芯片，广泛用于各种消费电子产品中。该芯片由Fairchild Semiconductor公司（现为ON Semiconductor的一部分）设计并生产，其独特的结构和功能使其在能源效率和小型化设计领域具有优势。FAN7930CMX主要用于DC-DC转换器、LED驱动器和电池管理系统，具备多种保护功能，如过流保护、过温保护和欠压锁定功能，确保系统的安全和稳定运行。详细参数 FAN7930CMX的技术参数包括输入电压范围、输出电流、开关频率、效率等。具体参数如下： - 输入电压范围：4.5V至30V - 输出电流：最大可达到3A - 开关频率：典型为300kHz，调整范围根据具体应用而定 - 效率：在负载条件下，最高可达92%以上 - 工作温度范围：-40℃至+125℃ - 封装形式：SOIC-8封装，适合多种PCB...

产品型号FAN7930CMX的Datasheet PDF文件预览

October 2010

FAN7930C

Critical Conduction Mode PFC Controller

Features

Description

PFC-Ready Signal

The FAN7930C is an active power factor correction

(PFC) controller for boost PFC applications that operate

in critical conduction mode (CRM). It uses a voltage-

mode PWM that compares an internal ramp signal with

the error amplifier output to generate a MOSFET turn-off

signal. Because the voltage-mode CRM PFC controller

does not need rectified AC line voltage information, it

saves the power loss of an input voltage sensing network

necessary for a current-mode CRM PFC controller.

Input Voltage Absent Detection

Maximum Switching Frequency Limitation

Internal Soft-Start and Startup without Overshoot

Internal Total Harmonic Distortion (THD) Optimizer

Precise Adjustable Output Over-Voltage Protection

Open-Feedback Protection and Disable Function

Zero-Current Detector (ZCD)

FAN7930C provides over-voltage protection (OVP),

open-feedback protection, over-current protection

(OCP), input-voltage-absent detection, and under-

voltage lockout protection (UVLO). The PFC-ready pin

can be used to trigger other power stages when PFC

output voltage reaches the proper level with hysteresis.

The FAN7930C can be disabled if the INV pin voltage is

lower than 0.45V and the operating current decreases to

a very low level. Using a new variable on-time control

method, THD is lower than the conventional CRM boost

PFC ICs.

150μs Internal Startup Timer

MOSFET Over-Current Protection (OCP)

Under-Voltage Lockout with 3.5V Hysteresis

Low Startup and Operating Current

Totem-Pole Output with High State Clamp

+500/-800mA Peak Gate Drive Current

8-Pin SOP

Related Resources

Applications

AN-8035 — Design Consideration for Boundary

Conduction Mode PFC Using FAN7930

Adapter

Ballast

LCD TV, CRT TV

SMPS

Ordering Information

Operating

Temperature Range

Packing

Part Number

Top Mark

Package

Method

FAN7930CM

Rail

-40 to +125°C

FAN7930C 8-Lead Small Outline Package (SOP)

FAN7930CMX

Tape & Reel

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Application Diagram

Figure 1.

Typical Boost PFC Application

Internal Block Diagram

Figure 2.

Functional Block Diagram

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Pin Configuration

Figure 3.

Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter

should be resistively divided to 2.5V.

INV

RDY

COMP

This pin is used to detect PFC output voltage reaching a pre-determined value. When output

voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an (open-drain)

output type.

This pin is the output of the transconductance error amplifier. Components for the output voltage

compensation should be connected between this pin and GND.

This pin is the input of the over-current protection comparator. The MOSFET current is sensed

using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is

included to filter switching noise.

This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than

1.5V, then goes lower than 1.4V, the MOSFET is turned on.

ZCD

GND

This pin is used for the ground potential of all the pins. For proper operation, the signal ground

and the power ground should be separated.

This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and

-800mA, respectively. For proper operation, the stray inductance in the gate driving path must be

minimized.

OUT

V_CC

This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

Max.

V_Z

Unit

Supply Voltage

I_OH, I_OL

I_CLAMP

I_DET

Peak Drive Output Current

-800

-10

+500

+10

8.0

Driver Output Clamping Diodes V_O>V_CCor V_O<-0.3V

Detector Clamping Diodes

-10

Error Amplifier Input, Output, ZCD and RDY Pin⁽¹⁾

CS Input Voltage⁽²⁾

-0.3

-10.0

V_IN

6.0

T_J

T_A

Operating Junction Temperature

Operating Temperature Range

+150

+125

+150

2.5

°C

-40

-65

T_STG

Storage Temperature Range

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

Electrostatic Discharge

Capability

ESD

2.0

Notes:

1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA.

2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical

specifications are not guaranteed during such a short time.

Thermal Impedance

Symbol

Parameter

Min.

Max.

Unit

Thermal Resistance, Junction-to-Ambient⁽³⁾

150

°C/W

Θ_JA

Note:

3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.

www.fairchildsemi.com

FAN7930C • Rev. 1.0.0

Electrical Characteristics

V_CC= 14V, T_A= -40°C~+125°C, unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_CCSection

V_START

V_STOP

Start Threshold Voltage

Stop Threshold Voltage

UVLO Hysteresis

V_CCIncreasing

V_CCDecreasing

7.5

3.0

8.5

3.5

9.5

4.0

HY_UVLO

V_Z

Zener Voltage

I_CC=20mA

V_OP

Recommended Operating Range

Supply Current Section

I_STARTStartup Supply Current

I_OPOperating Supply Current

V_CC=V_START-0.2V

120

1.5

2.5

160

190

3.0

µA

Output Not Switching

I_DOP

Dynamic Operating Supply Current 50kHZ, C_I=1nF

Operating Current at Disable V_INV=0V

4.0

230

I_OPDIS

Error Amplifier Section

V_REF1

ΔV_REF1

ΔV_REF2

I_EA,BS

Voltage Feedback Input Threshold1 T_A=25°C

2.465

2.500

0.1

2.535

10.0

Line Regulation

V_CC=14V~20V

µA

(4)

Temperature Stability of V_REF1

Input Bias Current

V_INV=1V~4V

-0.5

0.5

I_EAS,SR

Output Source Current

V_INV=V_REF-0.1V

V_INV=V_REF+0.1V

V_INV=1V, V_CS=0V

-12

µA

I_EAS,SK

V_EAH

V_EAZ

g_m

Output Sink Current

Output Upper Clamp Voltage

6.0

0.9

6.5

1.0

115

7.0

1.1

140

Zero-Duty Cycle Output Voltage

Transconductance⁽⁴⁾

µmho

Maximum On-Time Section

t_ON,MAX1

t_ON,MAX2

Maximum On-Time Programming 1 T_A=25°C, V_ZCD=1V

35.5

11.2

41.5

13.0

47.5

14.8

µs

T_A=25°C,

Maximum On-Time Programming 2

I_ZCD=0.469mA

Current-Sense Section

Current-Sense Input Threshold

Voltage Limit

V_CS

I_CS,BS

t_CS,D

0.7

0.8

-0.1

350

0.9

1.0

500

Input Bias Current

V_CS=0V~1V

-1.0

µA

dV/dt=1V/100ns,

from 0V to 5V

Current-Sense Delay to Output⁽⁴⁾

Continued on the following page…

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Electrical Characteristics

V_CC= 14V, T_A= -40°C~+125°C, unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Units

Zero-Current Detect Section

V_ZCD

Input Voltage Threshold⁽⁴⁾

1.35

0.05

5.5

1.50

0.10

6.2

1.65

0.15

7.5

1.00

1.0

-4

HY_ZCDDetect Hysteresis⁽⁴⁾

V_CLAMPHInput High Clamp Voltage

V_CLAMPLInput Low Clamp Voltage

I_ZCD,BSInput Bias Current

I_ZCD,SRSource Current Capability⁽⁴⁾

I_ZCD,SKSink Current Capability⁽⁴⁾

I_DET=3mA

I_DET= -3mA

V_ZCD=1V~5V

T_A=25°C

0.65

-0.1

-1.0

µA

T_A=25°C

Maximum Delay From ZCD to Output

Turn-On⁽⁴⁾

dV/dt=-1V/100ns,

from 5V to 0V

t_ZCD,D

100

9.2

200

Output Section

V_OH

V_OL

Output Voltage High

I_O=-100mA, T_A=25°C

I_O=200mA, T_A=25°C

C_IN=1nF

11.0

1.0

12.8

2.5

Output Voltage Low

Rising Time⁽⁴⁾

Falling Time⁽⁴⁾

t_RISE

t_FALL

100

14.5

C_IN=1nF

V_O,MAXMaximum Output Voltage

V_CC=20V, I_O=100µA

V_CC=5V, I_O=100µA

11.5

13.0

V_O,UVLOOutput Voltage with UVLO Activated

Restart / Maximum Switching Frequency Limit Section

t_RST

f_MAX

Restart Timer Delay

Maximum Switching Frequency⁽⁴⁾

150

300

350

µs

250

kHz

RDY Pin

I_RDY,SKOutput Sink Current

V_RDY,SATOutput Saturation Voltage

I_RDY,LKOutput Leakage Current

Soft-Start Timer Section

500

µA

I_RDY,SK=2mA

320

Output High Impedance

t_SS

UVLO Section

Internal Soft-Soft⁽⁴⁾

V_RDY

Output Ready Voltage

2.166 2.240 2.314

0.189

HY_RDYOutput Ready Hysteresis

Protections

V_OVP

OVP Threshold Voltage

T_A=25°C

2.620 2.675 2.730

0.120 0.175 0.230

HY_OVPOVP Hysteresis

V_EN

HY_EN

T_SD

Enable Threshold Voltage

0.40

0.050

125

0.45

0.10

140

0.50

0.15

155

Enable Hysteresis

Thermal Shutdown Temperature⁽⁴⁾

Hysteresis Temperature of TSD⁽⁴⁾

°C

T_HYS

Note:

4. These parameters, although guaranteed by design, are not production tested.

www.fairchildsemi.com

FAN7930C • Rev. 1.0.0

Comparison of FAN7530 and FAN7930C

Function

FAN7530

FAN7930C

FAN7930C Advantages

No External Circuit for PFC Output UVLO

Reduce Power Loss and BOM Cost Caused by

PFC Out UVLO Circuit

PFC Ready Pin

None

Integrated

Versatile Open-Drain Pin

Abnormal CCM Operation Prohibited

Frequency Limit

None

Integrated

Abnormal Inductor Current Accumulation can be

Prohibited

Increase System Reliability by testing for input

supply voltage

V_IN-Absent Detection

Guarantee Stable Operation at Short Electric

Power Failure

Reduce Voltage and Current Stress at Startup

Soft-Start and

Overshoot

Prevention

Integrated

Internal

Eliminate Audible Noise due to Unwanted OVP

Triggering

No External Resistor is Needed

THD Optimizer

TSD

External

None

Stable and Reliable TSD Operation

Converter Temperature Range Limited Range

140°C with 60°C

Hysteresis

Comparison between FAN7930 and FAN7930C

Function

FAN7930

FAN7930C

FAN7930C Remark

If PFC rated output voltage is assumed 390V:

FAN7930: V_{RDY_HIGH}trigger voltage = 349V

V_{RDY_LOW}trigger voltage = 256V

RDY Threshold

2.240V

FAN7930C: V_{RDY_HIGH}trigger voltage = 349V

V_{RDY_LOW}trigger voltage = 320V

RDY Hysteresis

0.600V

None

0.189V

Control Range

Compensation

Integrated

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Typical Performance Characteristics

Figure 4. Voltage Feedback Input Threshold 1 (V_REF1

vs. T_A

)

Figure 5. Start Threshold Voltage (V_START) vs. T_A

Figure 6. Stop Threshold Voltage (V_STOP) vs. T_A

Figure 7. Startup Supply Current (I_START) vs. T_A

Figure 8. Operating Supply Current (I_OP) vs. T_A

Figure 9. Output Upper Clamp Voltage (V_EAH) vs. T_A

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Typical Performance Characteristics

Figure 10. Zero Duty Cycle Output Voltage (V_EAZ

vs. T_A

)

Figure 11. Maximum On-Time Program 1 (t_ON,MAX1

vs. T_A

)

Figure 12. Maximum On-Time Program 2 (t_ON,MAX2

vs. T_A

)

Figure 13. Current-Sense Input Threshold Voltage

Limit (V_CS) vs. T_A

Figure 14. Input High Clamp Voltage (V_CLAMPH) vs. T_AFigure 15. Input Low Clamp Voltage (V_CLAMPL) vs. T_A

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Typical Performance Characteristics

Figure 16. Output Voltage High (V_OH) vs. T_A

Figure 17. Output Voltage Low (V_OL) vs. T_A

Figure 19. Output Ready Voltage (V_RDY) vs. T_A

Figure 21. OVP Threshold Voltage (V_OVP) vs. T_A

Figure 18. Restart Timer Delay (t_RST) vs. T_A

Figure 20. Output Saturation Voltage (V_RDY,SAT

vs. T_A

)

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Applications Information

1. Startup: Normally, supply voltage (V_CC) of a PFC

block is fed from the additional power supply, which can

be called standby power. Without this standby power,

auxiliary winding for zero current detection can be used

as a supply source. Once the supply voltage of the PFC

block exceeds 12V, internal operation is enabled until

the voltage drops to 8.5V. If V_CCexceeds V_Z, 20mA

current is sinking from V_CC

Figure 23. Circuit Around INV Pin

Figure 22. Startup Circuit

2. INV Block: Scaled-down voltage from the output is

the input for the INV pin. Many functions are embedded

based on the INV pin: transconductance amplifier,

output OVP comparator, disable comparator, and output

UVLO comparator.

For the output voltage control, a transconductance

amplifier is used instead of the conventional voltage

amplifier. The transconductance amplifier (voltage-

controlled current source) aids the implementation of the

OVP and disable functions. The output current of the

amplifier changes according to the voltage difference of

the inverting and non-inverting input of the amplifier. To

cancel down the line input voltage effect on power factor

correction, the effective control response of the PFC

block should be slower than the line frequency and this

conflicts with the transient response of controller. Two-

pole one-zero type compensation may be used to meet

both requirements.

Figure 24. Timing Chart for INV Block

3. RDY Output: When the INV voltage is higher than

2.24V, RDY output is triggered HIGH and lasts until the

INV voltage is lower than 2.051V. When input AC

voltage is quite high, for example 240V_AC, PFC output

voltage is always higher than RDY threshold, regardless

of boost converter operation. In this case, the INV

voltage is already higher than 2.24V before PFC V_CC

touches V_START; however, RDY output is not triggered to

HIGH until V_CCtouches V_START. After boost converter

operation stops, RDY is not pulled LOW because the

INV voltage is higher than the RDY threshold. When V_CC

of the PFC drops below 5V, RDY is pulled LOW even

though PFC output voltage is higher than threshold. The

RDY pin output is open drain, so needs an external pull-

up resistor to supply the proper power source. The RDY

pin output remains floating until V_CCis higher than 2V.

The OVP comparator shuts down the output drive block

when the voltage of the INV pin is higher than 2.675V

and there is 0.175V hysteresis. The disable comparator

disables operation when the voltage of the inverting

input is lower than 0.35V and there is 100mV hysteresis.

An external small-signal MOSFET can be used to

disable the IC, as shown in Figure 23. The IC operating

current decreases to reduce power consumption if the

IC is disabled. Error! Reference source not found. is

the timing chart of the internal circuit near the INV pin

when rated PFC output voltage is 390V_DCand V_CC

supply voltage is 15V.

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

(see Equation 1). Positive voltage is induced (see

Equation 2) when the power switch turns off.

AUX

= −

⋅ V

AUX

(1)

(2)

IND

AUX

⋅

− V

)

PFCOUT

IND

where:

V_AUXis the auxiliary winding voltage;

T_INDis boost inductor turns;

T_INDauxiliary winding turns;

V_ACis input voltage for PFC converter; and

V_{OUT_PFC}is output voltage from the PFC converter.

Figure 25. Two Cases of RDY Triggered HIGH

Figure 27. Circuit Near ZCD

Because auxiliary winding voltage can swing from

negative to positive voltage, the internal block in ZCD

pin has both positive and negative voltage clamping

circuits. When the auxiliary voltage is negative, internal

circuit clamps the negative voltage at the ZCD pin

around 0.65V by sourcing current to the serial resistor

between the ZCD pin and the auxiliary winding. When

the auxiliary voltage is higher than 6.5V, current is

sinked through a resistor from the auxiliary winding to

the ZCD pin.

Figure 28. Auxiliary Voltage Depends on

MOSFET Switching

Figure 26. Two Cases of RDY Triggered LOW

The auxiliary winding voltage is used to check the boost

inductor current zero instance. When boost inductor

current becomes zero, there is a resonance between

boost inductor and all capacitors at the MOSFET drain

pin: including C_OSSof the MOSFET; an external

capacitor at the D-S pin to reduce the voltage rising and

falling slope of the MOSFET; a parasitic capacitor at

inductor; and so on to improve performance. Resonated

voltage is reflected to the auxiliary winding and can be

used for detecting zero current of boost inductor and

4. Zero-Current Detection: Zero-current detection

(ZCD) generates the turn-on signal of the MOSFET

when the boost inductor current reaches zero using an

auxiliary winding coupled with the inductor. When the

power switch turns on, negative voltage is induced at the

auxiliary winding due to the opposite winding direction

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

valley position of MOSFET voltage stress. For valley

detection, a minor delay by the resistor and capacitor is

needed. A capacitor increases the noise immunity at the

ZCD pin. If ZCD voltage is higher than 1.5V, an internal

ZCD comparator output becomes HIGH and LOW when

the ZCD goes below 1.4V. At the falling edge of

comparator output, internal logic turns on the MOSFET.

current is reset to zero at the next switch on; inductor

current builds up at every switching cycle and can be

raised to very high current that exceeds the current

rating of the power switch or diode. This can seriously

damage the power switch and result in burn down. To

avoid this, maximum switching frequency limitation is

embedded. If ZCD signal is applied again within 3.3μs

after the previous rising edge of gate signal, this signal

is ignored internally and FAN7930C waits for another

ZCD signal. This slightly degrades the power factor

performance at light load and high input voltage.

Figure 31. Maximum Switching Frequency

Limit Operation

5. Control: The scaled output is compared with the

internal reference voltage and sinking or sourcing

current is generated from the COMP pin by the

transconductance amplifier. The error amplifier output is

compared with the internal sawtooth waveform to give

proper turn-on time based on the controller.

Figure 29. Auxiliary Voltage Threshold

When no ZCD signal is available, the PFC controller

cannot turn on the MOSFET, so the controller checks

every switching off time and forces MOSFET turn on

when the off time is longer than 150μs. This is called the

restart timer, which triggers MOSFET turn-on at startup

and may be used at the input voltage zero-cross period.

Figure 32. Control Circuit

Unlike a conventional voltage-mode PWM controller,

FAN7930C turns on the MOSFET at the falling edge of

ZCD signal. On-instance is determined by the external

signal and the turn-on time lasts until the error amplifier

output (V_COMP) and sawtooth waveform meet. When

load is heavy, output voltage decreases, scaled output

decreases, COMP voltage increases to compensate low

output, turn-on time lengthens to give more inductor

turn-on time, and increased inductor current raises the

output voltage. This is how PFC negative feedback

controller regulates output.

150μs

Figure 30. Restart Timer at Startup

Because the MOSFET turn-on depends on the ZCD

input, switching frequency may increase to higher than

several megahertz due to the miss-triggering or noise

on the nearby ZCD pin. If the switching frequency is

higher than needed for critical conduction mode (CRM),

operation mode shifts to continuous conduction mode

(CCM). In CCM, unlike CRM where the boost inductor

The maximum of V_COMPis limited to 6.5V, which dictates

the maximum turn-on time, and switching stops when

V_COMPis lower than 1.0V.

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

6. Soft-Start: When V_CCreaches V_START, the internal

reference voltage is increased like a stair step for 5ms.

As a result, V_COMPis also raised gradually and MOSFET

turn-on time increases smoothly. This reduces voltage

and current stress on the power switch during startup.

0.155 V / μs

Figure 33. Turn-On Time Determination

The roles of PFC controller are regulating output voltage

and input current shaping to increase power factor. Duty

control based on the output voltage should be fast

enough to compensate output voltage dip or overshoot.

For the power factor, however, the control loop must not

react to the fluctuating AC input voltage. These two

requirements conflict; therefore, when designing a

feedback loop, the feedback loop should be least 10

times slower than AC line frequency. That slow

response is made by C1 at compensator. R1 makes

gain boost around operation region and C2 attenuates

gain at higher frequency. Boost gain by R1 helps raise

the response time and improves phase margin.

Figure 36. Soft-Start Sequence

7. Startup without Overshoot: Feedback control speed

of PFC is quite slow. Due to the slow response, there is

a gap between output voltage and feedback control.

That is why over-voltage protection (OVP) is critical at

the PFC controller and voltage dip caused by fast load

changes from light to heavy is diminished by a bulk

capacitor. OVP is easily triggered at startup phase.

Operation on and off by OVP at startup may cause

audible noise and can increase voltage stress at startup,

which is normally higher than in normal operation. This

operation is better when soft-start time is very long.

However, too much startup time enlarges the output

voltage building time at light load. FAN7930C has

overshoot avoidance at startup. During startup, the

feedback loop is controlled by an internal proportional

gain controller and, when the output voltage reaches the

rated value, it switches to an external compensator after

a transition time of 30ms. This internal proportional gain

controller eliminates overshoot at startup and an

external conventional compensator takes over

successfully afterward.

Figure 34. Compensators Gain Curve

For the transconductance error amplifier side, gain

changes based on differential input. When the error is

large, gain is large to make the output dip or peak to

suppress quickly. When the error is small, low gain is

used to improve power factor performance.

250μmho

115μmho

Figure 35. Gain Characteristic

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Figure 37. Startup Control without Overshoot

Figure 39. Input and Output Current Near Input

Voltage Peak Zero Cross

8. THD Optimization: Total Harmonic Distortion (THD)

is the factor that dictates how closely input current

shape matches sinusoidal form. The turn-on time of the

PFC controller is almost constant over one AC line

period due to the extremely low feedback control

response. The turn-off time is determined by the current

decrease slope of the boost inductor made by the input

voltage and output voltage. Once inductor current

becomes zero, resonance between C_OSSand the boost

inductor makes oscillating waveforms at the drain pin

and auxiliary winding. By checking the auxiliary winding

voltage through the ZCD pin, the controller can check

the zero current of boost inductor. At the same time, a

minor delay is inserted to determine the valley position

of drain voltage. The input and output voltage difference

is at its maximum at the zero cross point of AC input

voltage. The current decrease slope is steep near the

zero cross region and more negative inductor current

flows during a drain voltage valley detection time. Such

a negative inductor current cancels down the positive

current flows and input current becomes zero, called

“zero-cross distortion” in PFC.

To improve this, lengthened turn-on time near the zero

cross region is a well-known technique, though the

method may vary and may be proprietary. FAN7930C

optimizes this by sourcing current through the ZCD pin.

Auxiliary winding voltage becomes negative when the

MOSFET turns on and is proportional to input voltage.

The negative clamping circuit of ZCD outputs the

current to maintain the ZCD voltage at a fixed value.

The sourcing current from the ZCD is directly

proportional to the input voltage. Some portion of this

current is applied to the internal sawtooth generator,

together with a fixed-current source. Theoretically, the

fixed-current source and the capacitor at sawtooth

generator determine the maximum turn-on time when no

current is sourcing at ZCD clamp circuit and available

turn-on time gets shorter proportional to the ZCD

sourcing current.

Figure 38. Input and Output Current Near Input

Voltage Peak

Figure 40. Circuit of THD Optimizer

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

suddenly interrupted during two or three AC line

periods; V_CCis still live during that time, but output

voltage drops because there is no input power source.

Consequently, the control loop tries to compensate for

the output voltage drop and V_COMPreaches its

maximum. This lasts until AC input voltage is live again.

When AC input voltage is live again, high V_COMPallows

high switching current and more stress is put on the

MOSFET and diode. To protect against this, FAN7930C

checks if the input AC voltage exists. If input does not

exist, soft-start is reset and waits until AC input is live

again. Soft-start manages the turn-on time for smooth

operation when it detects AC input is applied again and

applies less voltage and current stress on startup.

Figure 41. Effect of THD Optimizer

10. Current Sense: The MOSFET current is sensed

using an external sensing resistor for over-current

protection. If the CS pin voltage is higher than 0.8V, the

By THD optimizer, turn-on time over one AC line period

is proportionally changed, depending on input voltage.

Near zero cross, lengthened turn-on time improves THD

performance.

over-current protection comparator generates

protection signal. An internal RC filter of 40kΩ and 8pF

is included to filter switching noise.

9. V_INAbsent Detection: To save power loss caused by

input voltage sensing resistors and to optimize THD, the

FAN7930C omits AC input voltage detection. Therefore,

no information about AC input is available from the

internal controller. In many cases, the V_CCof PFC

controller is supplied by a independent power source,

like standby power. In this scheme, some mismatch

may exist. For example, when the electric power is

11. Gate Driver Output: FAN7930C contains a single

totem-pole output stage designed for a direct drive of

the power MOSFET. The drive output is capable of up

to +500/-800mA peak current with a typical rise and fall

time of 50ns with 1nF load. The output voltage is

clamped to 13V to protect the MOSFET gate even if the

V_CCvoltage is higher than 13V.

V_OUT

V_IN

Though V_INis

eliminated, operation of

controller is normal due

to the large bypass

capacitor.

V_AUX

D_MAX

f_MIN

D_MIN

MOSFET gate

NewV_COMP

f_MIN

V_INAbsence Detected

I_DS

Smooth

Soft-Start

FAN7930 Rev.00

Figure 43. Operation with V_INAbsent Circuit

Figure 42. Operation without V_INAbsent Circuit

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

PCB Layout Guide

PFC block normally handles high switching current and

the voltage low energy signal path can be affected by

the high energy path. Cautious PCB layout is mandatory

for stable operation.

5. A stabilizing capacitor for V_CCis recommended as

close as possible to the V_CCand ground pins. If it is

difficult, place the SMD capacitor as close to the

corresponding pins as possible.

1. The gate drive path should be as short as possible.

The closed-loop that runs from the gate driver,

MOSFET gate, and MOSFET source to ground of

PFC controller should be as close as possible. This

is also crossing point between power ground and

signal ground. Power ground path from the bridge

diode to the output bulk capacitor should be short

and wide. The sharing position between power

ground and signal ground should be only at one

position to avoid ground loop noise. Signal path of

PFC controller should be short and wide for

external components to contact.

2. PFC output voltage sensing resistor is normally

high to reduce current consumption. This path can

be affected by external noise. To reduce noise

potential at the INV pin, a shorter path for output

sensing is recommended. If a shorter path is not

possible, place some dividing resistors between

PFC output and the INV pin — closer to the INV pin

is better. Relative high voltage close to the INV pin

can be helpful.

3. ZCD path is recommended close to auxiliary

winding from boost inductor and to the ZCD pin. If

that is difficult, place a small capacitor (below 50pF)

to reduce noise.

Figure 44. Recommended PCB Layout

4. The switching current sense path should not share

with another path to avoid interference. Some

additional components may be needed to reduce

the noise level applied to the CS pin.

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Typical Application Circuit

Output Voltage

(Maximum

Current)

Input Voltage

Range

Rated Output

Power

Application

Device

FAN7930C

LCD TV Power Supply

90-265V_AC

195W

390V (0.5A)

Features

Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.

Power factor at rated load is higher than 0.98 at universal input.

Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.

Key Design Notes

When auxiliary V_CCsupply is not available, V_CCpower can be supplied through Zero Current Detect (ZCD)

winding. The power consumption of R103 is quite high, so its power rating needs checking.

Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should

be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need

to strike a balance between power consumption and noise immunity.

Quick-charge diode D106 can be eliminated. Without D106, system operation is normal due to the controller’s

highly reliable protection features.

1. Schematic

Optional

D106

600V 3A

D105

600V 8A

230mH,

49:6

DC OUTPUT

LP101,EER3124N

BD101,

600V,15A

V_AUX

R103,

10k,1W

C104,

12nF

R109

Q101

FCPF

20N60

D102,

UF4004

FAN7930C

D103,1N414

R108

4.7

V_CC

Out

C102,

680nF

Com

INV

GND

C114 C115

,2.2n ,2.2n

C101,

220nF

R101,1M-

V_CCfor another power stage

ZNR101

,10D471

Circuit for V_CC. If external V_CCis used, this circuit is not needed.

Circuit for V_CCfor another power stage thus components structure and values may vary.

Figure 45. Demonstration Circuit

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

2. Transformer

Figure 46. Transformer Schematic Diagram

3. Winding Specification

Barrier Tape

Winding

Method

Position

Bottom

Top

Pin (S → F)

9, 10 → 7, 8

Wire

Turns

TOP

BOT

N_p

0.1φ×50

Solenoid Winding

Insulation: Polyester Tape t = 0.025mm, 3 Layers

N_AUX2 → 4 0.3φ

Insulation: Polyester Tape t = 0.025mm, 4 Layers

Solenoid Winding

4. Electrical Characteristics

Specification

230μH ±7%

Remark

Inductance

9, 10 → 7, 8

100kHz, 1V

5. Core & Bobbin

Core: EER3124, Samhwa (PL-7) (Ae=97.9mm²)

Bobbin: EER3124

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

6. Bill of Materials

Part #

Value

Resister

1MΩ

Note

Part #

Value

Switch

Note

R101

R102

R103

R104

1/2W

Q101

FCPF20N60

20A, 600V, SuperFET

Diode

330kΩ

10kΩ

D101

D102

1N4746

UF4004

1W, 18V, Zener Diode

1A, 400V Glass Passivated

High-Efficiency Rectifier

1/4W

30kΩ

R107

R108

R109

1/4W

D103

D104

1N4148

1A, 100V Small-Signal Diode

10kΩ

4.7kΩ

8A, 600V, General-Purpose

Rectifier

D105

D106

47kΩ

10kΩ

R110

1/4W

3A, 600V, General-Purpose

Rectifier

R111

R112, 113, 114

R115

0.80kΩ

3.9kΩ

1/4W

IC101

FAN7930C

CRM PFC Controller

75kΩ

Capacitor

Fuse

C101

C102

C103

C104

C105

C107

C108

C109

C110

C112

C111

C114

C115

220nF/275V_AC

680nF/275V_AC

0.68µF/630V

12nF/50V

Box Capacitor

FS101

TH101

BD101

LF101

5A/250V

5D-15

NTC

Box Capacitor

Bridge Diode

Ceramic Capacitor

SMD (1206)

100nF/50V

33µF/50V

15A, 600V

Line Filter

Electrolytic Capacitor

Ceramic Capacitor

220nF/50V

47nF/50V

23mH

Transformer

EER3124

1nF/50V

Ae=97.9mm²

ZNR

47nF/50V

220µF/450V

2.2nF/450V

Electrolytic Capacitor ZNR101

Box Capacitor

10D471

Box Capacitor

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

Physical Dimensions

5.00

4.80

0.65

3.81

1.75

6.20

5.80

4.00

3.80

5.60

PIN ONE

INDICATOR

1.27

(0.33)

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

1.75 MAX

0.51

0.33

0.10 C

x 45°

OPTION A - BEVEL EDGE

0.50

0.25

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

0.40

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 47. 8-Lead Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

FAN7930C • Rev. 1.0.0

www.fairchildsemi.com

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FAN7930CMX产品参数

型号:	FAN7930CMX
Brand Name：	Fairchild Semiconductor
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	FAIRCHILD SEMICONDUCTOR CORP
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
制造商包装代码：	8LD, SOIC,JEDEC MS-012, .150" NARROW BODY
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
风险等级：	7.81
Is Samacsys：	N
模拟集成电路 - 其他类型：	POWER FACTOR CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	20 V
最小输入电压：	9.5 V
标称输入电压：	14 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	0.5 A
标称输出电压：	13 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	14 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Switching Regulator or Controllers
最大供电电流 (Isup)：	4 mA
标称供电电压 (Vsup)：	14 V
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	350 kHz
温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm
Base Number Matches：	1

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