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产品型号FDC6506P的概述

芯片FDC6506P的概述 FDC6506P是一款由Fairchild Semiconductor（目前为ON Semiconductor的一部分）设计的高性能电流检测放大器，广泛应用于电源管理、汽车电子、高频开关电源等多个领域。该芯片以其高精度、高灵敏度和低噪声特性，在电流监测与采集方面表现出色。通过提供实时电流信息，FDC6506P能够有效提升电源管理系统的效率和稳定性。 FDC6506P的主要功能包括电流检测、误差放大以及多路信号输入的支持。该芯片尺寸小巧，极大地便利了PCB设计和布局，适合于空间受限的应用。其内置的高增益放大器设计使其在信号处理过程中能够保留信号的完整性，从而达成更好的系统性能。芯片FDC6506P的详细参数 FDC6506P的主要技术规格包括： - 工作电压范围：2.5V至5.5V - 增益：高达50 V/V - 输入偏置电流：最大仅为10nA - 带宽：最...

产品型号FDC6506P的Datasheet PDF文件预览

February 1999

FDC6506P

Dual P-Channel Logic Level PowerTrench MOSFET

Features

General Description

These P-Channel logic level MOSFETs are produced using

Fairchild Semiconductor's advanced PowerTrench

process that has been especially tailored to minimize

on-state resistance and yet maintain low gate charge for

superior switching performance.

• -1.8 A, -30 V. R_DS(on)= 0.170 Ω @ V_GS= -10 V

R_DS(on)= 0.280 Ω @ V_GS= -4.5 V

• Low gate charge (2.3nC typical).

• Fast switching speed.

These devices have been designed to offer exceptional

power dissipation in a very small footprint for applications

where the bigger more expensive SO-8 and TSSOP-8

packages are impractical.

• High performance trench technology for extremely

low R_DS(ON)

• SuperSOT^TM-6 package: small footprint (72% smaller

than standard SO-8); low profile (1mm thick).

Applications

• Load switch

• Battery protection

• Power management

SuperSOT ^TM-6

T_A= 25°C unless otherwise noted

Absolute Maximum Ratings

Symbol

Parameter

Ratings

Units

V_DSS

V_GSS

I_D

Drain-Source Voltage

Gate-Source Voltage

-30

(Note 1a)

Drain Current - Continuous

- Pulsed

-1.8

-10

(Note 1a)

(Note 1b)

P_D

Power Dissipation for Single Operation

0.96

0.9

(Note 1c)

0.7

T_J, T_stg

Operating and Storage Junction Temperature Range

-55 to +150

Thermal Characteristics

(Note 1a)

(Note 1)

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

130

C/W

Package Outlines and Ordering Information

Device Marking

506

Device

Reel Size

Tape Width

Quantity

3000 units

FDC6506P

7’’

8mm

1999 Fairchild Semiconductor Corporation

FDC6506P Rev. C

T_A= 25°C unless otherwise noted

Electrical Characteristics

Symbol

Parameter

Test Conditions

Min Typ Max Units

Off Characteristics

BV_DSS

Drain-Source Breakdown Voltage

V_GS= 0 V, I_D= -250

-30

DSS

Breakdown Voltage Temperature

Coefficient

I_D= -250 A, Referenced to 25 C

-20

mV/ C

∆

T_J

I_DSS

Zero Gate Voltage Drain Current

V_DS= -24 V, V_GS= 0 V

-1

I_GSSF

I_GSSR

Gate-Body Leakage Current, Forward V_GS= 20 V, V_DS= 0 V

Gate-Body Leakage Current, Reverse V_GS= -20 V, V_DS= 0 V

100

-100

(Note 2)

On Characteristics

V_GS(th)

Gate Threshold Voltage

V_DS= V_GS, I_D= -250

-1

-1.8

-3

GS(th)

Gate Threshold Voltage

Temperature Coefficient

I_D= -250 A, Referenced to 25 C

mV/ C

∆

T_J

∆

R_DS(on)

Static Drain-Source

On-Resistance

V_GS= -10 V, I_D= -1.8 A

0.14

0.20

0.22

0.17

0.27

0.28

Ω

_GS= -10 V, I_D= -1.8 A @125 C

_GS= -4.5 V, I_D= -1.4 A

I_D(on)

g_FS

On-State Drain Current

V_GS= -10 V, V_DS= - 5 V

-10

Forward Transconductance

V_DS= -5 V, I_D= -1.8 A

Dynamic Characteristics

C_iss

C_oss

C_rss

Input Capacitance

_DS= -15 V, V_GS= 0 V,

190

f = 1.0 MHz

Output Capacitance

Reverse Transfer Capacitance

(Note 2)

Switching Characteristics

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

_DD= -15 V, I_D= -1 A,

_GS= -4.5 V, R_GEN= 6

Ω

Q_g

Q_gs

Q_gd

_DS= -5 V, I_D= -1.8 A,

_GS= -10 V

2.3

3.5

0.8

Drain-Source Diode Characteristics and Maximum Ratings

I_S

Maximum Continuous Drain-Source Diode Forward Current

-0.8

-1.2

(Note 2)

V_SD

Drain-Source Diode Forward Voltage V_GS= 0 V, I_S= -0.8 A

-0.8

Notes:

R_θJAis the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface

of the drain pins. R_θJCis guaranteed by design while R_θJAis determined by the user's board design.Both devices are assumed to be operating and

sharing the dissipated heat energy equally.

a) 130 °C/W when

b) 140 °C/W when

c) 180 °C/W when

mounted on a 0.125 in²

pad of 2 oz. copper.

mounted on a 0.005 in²

pad of 2 oz. copper.

mounted on a 0.0015 in²

pad of 2 oz. copper.

Scale

1 : 1 on letter size paper

2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%

FDC6506P Rev. C

Typical Characteristics

2.5

V_GS=-10V

-7.0V

-5.5V

V_GS=-4.0V

-4.5V

1.5

-5.0V

-4.0V

-6.0V

-7.0V

-10V

-3.5V

-3.0V

0.5

-I_D, DRAIN CURRENT (A)

-V_DS, DRAIN TO SOURCE VOLTAGE (V)

Figure 2. On-Resistance Variation

Figure 1. On-Region Characteristics.

with Drain Current and Gate Voltage.

0.5

0.4

0.3

0.2

0.1

1.4

I_D=-1.8A

I_D=-1.0A

V_GS=-10V

1.3

1.2

1.1

T_J=125^oC

25^oC

0.9

0.8

0.7

-50

-25

100

125

150

-V_GS, GATE TO SOURCE VOLTAGE (V)

T_J, JUNCTION TEMPERATURE (^oC)

Figure 3. On-Resistance Variation

with Temperature.

Figure 4. On-Resistance Variation

with Gate-to-Source Voltage.

V_GS=0

T_J=-55^oC

V_DS=-5V

25^oC

125^o

T_J=125^oC

25^oC

0.1

-55^oC

0.01

0.001

0.3

0.6

0.9

1.2

1.5

-V_SD, BODY DIODE VOLTAGE (V)

-V_GS, GATE TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics.

Figure 6. Body Diode Forward Voltage

Variation with Source Current

and Temperature.

FDC6506P Rev. C

Typical Characteristics (continued)

300

240

180

120

f=1MHz

V_GS=0V

I_D= -1.8A

V_DS=-5.0V

-10V

C_iss

-15V

C_oss

C_rss

-V_DS, DRAIN TO SOURCE VOLTAGE (V)

Q_g, GATE CHARGE (nC)

Figure 7. Gate-Charge Characteristics.

Figure 8. Capacitance Characteristics.

SINGLE PULSE

R_θ_JA=180°C/W

TA= 25°C

0.3

0.1

V_GS= -10V

SINGLE PULSE

R_θ

= 180°C/W

0.03

0.01

T_A= 25°C

0.01

0.1

0.2

0.5

0.1

100

300

-V , DRAIN-SOURCE VOLTAGE (V)

SINGLE PULSE TIME (SEC)

Figure 9. Maximum Safe Operating Area.

Figure 10. Single Pulse Maximum

Power Dissipation.

D = 0.5

0.5

(t) = r(t) * R

=180°C/W

0.2

0.1

P(pk)

0.1

0.05

0.02

0.01

- T = P * R

(t)

Single Pulse

0.02

Duty Cycle, D = t / t

0.01

0.0001

0.001

0.01

0.1

, TIME (sec)

100

300

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.

Transient themal response will change depending on the circuit board design.

FDC6506P Rev. C

SuperSOT^TM-6 Tape and Reel Data and Package Dimensions

SSOT-6 Packaging

Configuration: Figure 1.0

Customize Label

Antistatic Cover Tape

Conductive Embossed

Carrier Tape

F63TNR

Label

631

Pin 1

SSOT-6 Packaging Information

Standard

(no flow code)

Packaging Option

D87Z

Packaging type

TNR

10,000

13”

SSOT-6 Unit Orientation

Qty per Reel/Tube/Bag

Reel Size

3,000

7” Dia

Box Dimension (mm)

Max qty per Box

184x187x47 343x343x64

9,000

0.0158

0.1440

20,000

0.0158

0.4700

343mm x 342mm x 64mm

F63TNR Label

Weight per unit (gm)

Weight per Reel (kg)

Intermediate box for D87ZOption

Note/Comments

F63TNR

Label

F63TNR Label sample

LOT: CBVK741B019

F63TNR

Label

QTY: 3000

SPEC:

184mm x

184mm x 47mm

Pizza Box for

Standard Option

FSID: FDC633N

D/C1: D9842

D/C2:

QTY1:

QTY2:

SPEC REV:

CPN:

QARV:

(F63TNR)2

Trailer

SSOT-6 Tape Leader

Configuration: Figure 2.0

Carrier Tape

Components

Cover Tape

Trailer Tape

160mm minimum

Leader Tape

390mm minimum

1998 Fairchild Semiconductor Corporation

December 1998, Rev. B

SuperSOT^TM-6 Tape and Reel Data and Package Dimensions, continued

SSOT-6 Embossed Carrier Tape

Configuration: Figure 3.0

User Direction of Feed

Dimensions are in millimeter

Pkg type

SSOT-6

(8mm)

3.23

+/-0.10

3.18

+/-0.10

8.0

+/-0.3

1.55

+/-0.05

1.00

+/-0.125

1.75

+/-0.10

6.25

min

3.50

+/-0.05

4.0

+/-0.1

4.0

+/-0.1

1.37

+/-0.10

0.255

+/-0.150

5.2

+/-0.3

0.06

+/-0.02

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

rotational and lateral movement requirements (see sketches A, B, and C).

0.5mm

maximum

20 deg maximum

Typical

component

cavity

center line

0.5mm

maximum

20 deg maximum component rotation

Typical

component

center line

Sketch A (Side or Front Sectional View)

Component Rotation

Sketch C (Top View)

Component lateral movement

Sketch B (Top View)

Component Rotation

SSOT-6 Reel Configuration: Figure 4.0

W1 Measured at Hub

Dim A

Max

Dim A

max

See detail AA

Dim N

7” Diameter Option

B Min

Dim C

See detail AA

Dim D

min

13” Diameter Option

W2 max Measured at Hub

DETAIL AA

Dim W2

Dimensions are in inches and millimeters

Reel

Option

Tape Size

8mm

Dim A

Dim B

Dim C

Dim D

Dim N

Dim W1

Dim W3 (LSL-USL)

7.00

177.8

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

2.165

0.331 +0.059/-0.000

8.4 +1.5/0

0.567

14.4

0.311 – 0.429

7.9 – 10.9

7” Dia

13.00

330

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

4.00

100

0.331 +0.059/-0.000

8.4 +1.5/0

0.567

14.4

0.311 – 0.429

7.9 – 10.9

8mm

13” Dia

December 1998, Rev. B

SuperSOT^TM-6 Tape and Reel Data and Package Dimensions, continued

SuperSOT -6 (FS PKG Code 31, 33)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0158

1998 Fairchild Semiconductor Corporation

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

CoolFET™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench™

QS™

CROSSVOLT™

E²CMOS^TM

FACT™

FACT Quiet Series™

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

TinyLogic™

FAST^®

FASTr™

GTO™

HiSeC™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or

In Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

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