FDS3992现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

September 2002

FDS3992

N-Channel PowerTrench^®MOSFET

100V, 4.5A, 62mΩ

Features

Applications

•

r_DS(ON)= 54mΩ (Typ.), V_GS= 10V, I_D= 4.5A

Q_g(tot) = 11nC (Typ.), V_GS= 10V

Low Miller Charge

•

DC/DC converters and Off-Line UPS

Distributed Power Architectures and VRMs

Primary Switch for 24V and 48V Systems

High Voltage Synchronous Rectifier

Direct Injection / Diesel Injection Systems

42V Automotive Load Control

Low Q_RRBody Diode

Optimized efficiency at high frequencies

UIS Capability (Single Pulse and Repetitive Pulse)

Formerly developmental type 82745

Electronic Valve Train Systems

(1)

(2)

(8)

(7)

Branding Dash

5

1

(3)

(4)

(6)

(5)

2

3

4

SO-8

MOSFET Maximum Ratings T_A= 25°C unless otherwise noted

Symbol

V_DSS

V_GS

Parameter

Ratings

100

Units

Drain to Source Voltage

Gate to Source Voltage

Drain Current

V

±20

Continuous (T_A= 25^oC, V_GS= 10V, R_θJA= 50^oC/W)

Continuous (T_A= 100^oC, V_GS= 10V, R_θJA= 50^oC/W)

Pulsed

4.5

2.8

A

I_D

Figure 4

167

A

E_AS

Single Pulse Avalanche Energy (Note 1)

Power dissipation

Derate above 25^oC

mJ

W

mW/^oC

^oC

2.5

P_D

20

T_J, T_STG

Operating and Storage Temperature

-55 to 150

Thermal Characteristics

R_θJA

R_θJC

Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)

50

85

25

^oC/W

Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)

Thermal Resistance, Junction to Case (Note 2)

Package Marking and Ordering Information

Device Marking

Device

Package

Reel Size

Tape Width

12mm

Quantity

FDS3992

SO-8

330mm

2500 units

FDS3992 Rev. B

Electrical Characteristics T_A= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

B_VDSS

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

I_D= 250µA, V_GS= 0V

100

-

V

_DS= 80V

-

1

I_DSS

µA

nA

V_GS= 0V

T_C= 150^oC

250

±100

I_GSS

V_GS= ±20V

On Characteristics

V_GS(TH)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 250µA

2

-

4

V

I_D= 4.5A, V_GS= 10V

0.054 0.062

0.072 0.108

I

_D= 2A, V_GS= 6V

-

r_DS(ON)

Drain to Source On Resistance

Ω

I

T

_D= 4.5A, V_GS= 10V,

-

0.107 0.123

_C= 150^oC

Dynamic Characteristics

C_ISS

Input Capacitance

-

750

118

27

-

pF

nC

V_DS= 25V, V_GS= 0V,

f = 1MHz

C_OSS

C_RSS

Q_g(TOT)

Q_g(TH)

Q_gs

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge at 10V

Threshold Gate Charge

-

V_GS= 0V to 10V

11

15

1.9

-

V_GS= 0V to 2V

1.4

3.5

2.1

2.8

V_DD= 50V

_D= 4.5A

I_g= 1.0mA

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

I

Q_gs2

-

Q_gd

-

Switching Characteristics (V_GS= 10V)

t_ON

t_d(ON)

t_r

Turn-On Time

Turn-On Delay Time

Rise Time

-

47

-

ns

8

23

28

26

-

V

_DD= 50V, I_D= 4.5A

_GS= 10V, R_GS= 27Ω

t_d(OFF)

t_f

Turn-Off Delay Time

Fall Time

-

t_OFF

Turn-Off Time

81

Drain-Source Diode Characteristics

I

_SD= 4.5A

_SD= 2A

-

1.25

1.0

48

V

V_SD

Source to Drain Diode Voltage

t_rr

Reverse Recovery Time

Reverse Recovery Charge

I_SD= 4.5A, dI_SD/dt= 100A/µs

ns

nC

Q_RR

65

Notes:

1: Starting T = 25°C, L = 37mH, I = 3A.

J

AS

2: R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

θJA

drain pins. R

is guaranteed by design while R

is determined by the user’s board design.

θJC

θCA

2

3: R

is measured with 1.0 in copper on FR-4 board

θJA

FDS3992 Rev. B

Typical Characteristics T_A= 25°C unless otherwise noted

5

4

3

2

1

0

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 10V

GS

0

25

50

75

100

125

150

25

50

75

T , CASE TEMPERATURE ( C)

C

100

125

150

o

T

, AMBIENT TEMPERATURE ( C)

A

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs

Case Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

o

R

=50 C/W

0.2

θJA

0.1

0.05

0.02

0.01

0.1

P

DM

t

1

0.01

0.001

t

2

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t /t

1

2

PEAK T = P

J

x Z

x R

+ T

DM

θJA

θJA A

-5

-4

-3

-2

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

200

o

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

T = 25 C

A

FOR TEMPERATURES

ABOVE 25 C DERATE PEAK

CURRENT AS FOLLOWS:

100

10

1

o

150 - T

125

C

I = I

25

V

= 10V

GS

-5

-4

-3

-2

-1

0

1

2

3

10

t, PULSE WIDTH (s)

10

Figure 4. Peak Current Capability

FDS3992 Rev. B

Typical Characteristics T_A= 25°C unless otherwise noted

200

100

7

10µs

o

STARTING T = 25 C

J

10

1

o

STARTING T = 150 C

100µs

J

1

1ms

OPERATION IN THIS

AREA MAY BE

10ms

LIMITED BY r

DS(ON)

100ms

0.1

0.01

SINGLE PULSE

If R = 0

= (L)(I )/(1.3*RATED BV

t

AV

- V

)

T

= MAX RATED

AS

DSS

DD

J

o

If R ≠ 0

= 25 C

1s

C

t

AV

= (L/R)ln[(I *R)/(1.3*RATED BV

- V ) +1]

DD

AS

DSS

0.1

1

10

100

300

0.01

0.1

1

10

100

V

, DRAIN TO SOURCE VOLTAGE (V)

t , TIME IN AVALANCHE (ms)

AV

DS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

Figure 5. Forward Bias Safe Operating Area

30

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

o

T

= 25 C

A

V

= 10V

GS

V

= 15V

DD

25

20

15

10

5

25

20

15

10

5

V

= 7V

GS

o

V

= 6V

T

= 150 C

GS

J

o

T

= 25 C

J

V

= 5V

GS

o

T

= -55 C

J

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

0

0.5

1.0

1.5

2.0

V

, GATE TO SOURCE VOLTAGE (V)

V

, DRAIN TO SOURCE VOLTAGE (V)

GS

DS

Figure 7. Transfer Characteristics

Figure 8. Saturation Characteristics

80

75

70

65

60

55

50

2.5

2.0

1.5

1.0

0.5

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 6V

GS

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 10V

GS

V

= 10V, I = 4.5A

D

GS

-80

-40

0

40

80

120

160

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

o

I , DRAIN CURRENT (A)

T , JUNCTION TEMPERATURE ( C)

D

J

Figure 9. Drain to Source On Resistance vs Drain

Current

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDS3992 Rev. B

Typical Characteristics T_A= 25°C unless otherwise noted

1.2

1.0

0.8

0.6

1.2

1.1

1.0

0.9

V

= V , I = 250µA

DS D

I

= 250µA

GS

D

-80

-40

0

40

80

120

160

-80

-40

0

40

80

120

160

o

T , JUNCTION TEMPERATURE ( C)

J

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

2000

10

V = 50V

DD

C

= C + C

GS GD

ISS

1000

100

10

8

6

4

2

0

C

+ C

OSS

DS GD

C

= C

RSS

GD

WAVEFORMS IN

DESCENDING ORDER:

I

= 4.5A

= 2A

D

V

= 0V, f = 1MHz

1

GS

0.1

10

100

0

2

4

6

8

10

12

V

, DRAIN TO SOURCE VOLTAGE (V)

Q , GATE CHARGE (nC)

DS

g

Figure 13. Capacitance vs Drain to Source

Voltage

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

FDS3992 Rev. B

Test Circuits and Waveforms

V

BV

DSS

DS

t

P

V

DS

L

I

AS

V

DD

VARY t TO OBTAIN

P

+

-

R

REQUIRED PEAK I

G

AS

V

DD

V

GS

DUT

t

P

I

0V

0

AS

0.01Ω

t

AV

Figure 15. Unclamped Energy Test Circuit

Figure 16. Unclamped Energy Waveforms

V

DS

V

Q

DD

g(TOT)

V

DS

L

V

= 10V

GS

V

GS

+

V

DD

V

GS

-

V

= 2V

DUT

GS

Q

gs2

0

I

g(REF)

Q

g(TH)

Q

gd

gs

I

g(REF)

0

Figure 17. Gate Charge Test Circuit

Figure 18. Gate Charge Waveforms

V

DS

t

ON

OFF

t

d(OFF)

t

d(ON)

R

t

f

L

r

V

0

DS

90%

+

V

GS

V

DD

10%

-

DUT

90%

50%

R

GS

V

GS

50%

PULSE WIDTH

10%

V

GS

0

Figure 19. Switching Time Test Circuit

Figure 20. Switching Time Waveforms

FDS3992 Rev. B

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, T_JM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, P_DM, in an

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2. The area, in square inches is the top copper

area including the gate and source pads.

application.

Therefore the application’s ambient

temperature, T_A(^oC), and thermal resistance R_θJA(^oC/W)

must be reviewed to ensure that T_JMis never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

26

R

= 64 + -------------------------------

(EQ. 2)

θ JA

0.23 + Area

(T

– T )

JM

A

(EQ. 1)

P

= ------------------------------

DM

R_θJA

The transient thermal impedance (Z_θJA) is also effected by

varied top copper board area. Figure 22 shows the effect of

copper pad area on single pulse transient thermal

impedance. Each trace represents a copper pad area in

square inches corresponding to the descending list in the

graph. Spice and SABER thermal models are provided for

each of the listed pad areas.

In using surface mount devices such as the SO8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

dissipation ratings. Precise determination of P_DMis complex

and influenced by many factors:

Copper pad area has no perceivable effect on transient

thermal impedance for pulse widths less than 100ms. For

pulse widths less than 100ms the transient thermal

impedance is determined by the die and package.

Therefore, CTHERM1 through CTHERM5 and RTHERM1

through RTHERM5 remain constant for each of the thermal

models. A listing of the model component values is available

in Table 1.

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

200

5. Air flow and board orientation.

R

= 64 + 26/(0.23+Area)

θJA

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

150

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the R_θJAfor the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

100

50

0.001

0.01

0.1

1

2

10

AREA, TOP COPPER AREA (in )

Figure 21. Thermal Resistance vs Mounting

Pad Area

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

120

2

0.52 in

2

0.76 in

2

90

60

30

0

1.00 in

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

10

Figure 22. Thermal Impedance vs Mounting Pad Area

FDS3992 Rev. B

PSPICE Electrical Model

.SUBCKT FDS3992 2 1 3 ;

Ca 12 8 2.3e-10

rev Aug 2002

Cb 15 14 3.5e-10

Cin 6 8 7.47e-10

LDRAIN

DPLCAP

DRAIN

2

5

10

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

RLDRAIN

RSLC1

51

DBREAK

+

RSLC2

5

ESLC

11

51

Ebreak 11 7 17 18 108

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

-

+

50

-

17

DBODY

RDRAIN

6

8

EBREAK 18

-

ESG

EVTHRES

+

16

21

+

-

19

8

MWEAK

LGATE

EVTEMP

RGATE

GATE

1

6

+

-

18

22

It 8 17 1

MMED

9

20

MSTRO

8

RLGATE

Lgate 1 9 5.61e-9

Ldrain 2 5 1e-9

Lsource 3 7 1.98e-9

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

RLgate 1 9 56.1

RLdrain 2 5 10

RLsource 3 7 19.8

S1A

S2A

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

-

S1B

S2B

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

13

CB

CA

IT

14

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 25.e-3

Rgate 9 20 3.7

22

RVTHRES

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 20e-3

Rvthres 22 8 Rvthresmod 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))}

.MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7

+ CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6)

.MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5)

.MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54)

.MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7)

.MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1)

.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8)

.MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5)

.MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6)

.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)

.MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5)

.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

FDS3992 Rev. B

SABER Electrical Model

REV Aug 2002

template FDS3992 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)

dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)

dp..model dplcapmod = (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54)

m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0)

LDRAIN

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0)

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5)

c.ca n12 n8 = 2.3e-10

c.cb n15 n14 = 3.5e-10

c.cin n6 n8 = 7.47e-10

DPLCAP

5

DRAIN

2

10

RLDRAIN

RSLC1

51

RSLC2

ISCL

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

DBREAK

11

50

-

RDRAIN

6

8

ESG

DBODY

EVTHRES

+

16

21

+

-

spe.ebreak n11 n7 n17 n18 = 108

19

8

MWEAK

LGATE

EVTEMP

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

RGATE

GATE

+

6

-

18

22

EBREAK

+

MMED

1

9

20

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

MSTRO

8

17

18

-

RLGATE

LSOURCE

CIN

SOURCE

3

7

RSOURCE

i.it n8 n17 = 1

RLSOURCE

S1A

S2A

l.lgate n1 n9 = 5.61e-9

l.ldrain n2 n5 = 1e-9

l.lsource n3 n7 = 1.98e-9

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

S1B

S2B

13

CB

res.rlgate n1 n9 = 56.1

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 19.8

CA

IT

14

-

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

22

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

RVTHRES

res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1e-8

res.rdrain n50 n16 = 25e-3, tc1=1.15e-2,tc2=2.8e-5

res.rgate n9 n20 = 3.7

res.rslc1 n5 n51 = 1e-6, tc1=3.3e-3,tc2=1e-6

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 20e-3, tc1=1e-3,tc2=1e-6

res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5

res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.5e-6

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5))

}

FDS3992 Rev. B

SPICE Thermal Model

JUNCTION

th

REV Aug 2002

FDS3992

Copper Area =1.0 in²

CTHERM1 TH 8 4e-4

CTHERM2 8 7 5e-3

CTHERM3 7 6 6e-2

CTHERM4 6 5 9e-2

CTHERM5 5 4 3e-1

CTHERM6 4 3 4e-1

CTHERM7 3 2 9e-1

CTHERM8 2 TL 2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

CTHERM1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

8

7

RTHERM1 TH 8 5e-1

RTHERM2 8 7 6e-1

RTHERM3 7 6 4

RTHERM4 6 5 5

RTHERM5 5 4 8

RTHERM6 4 3 9

RTHERM7 3 2 15

RTHERM8 2 TL 23

6

5

SABER Thermal Model

Copper Area = 1.0 in²

template thermal_model th tl

thermal_c th, tl

{

CTHERM1 TH 8 4e-4

CTHERM2 8 7 5e-3

CTHERM3 7 6 6e-2

CTHERM4 6 5 9e-2

CTHERM5 5 4 3e-1

CTHERM6 4 3 4e-1

CTHERM7 3 2 9e-1

CTHERM8 2 TL 2

4

3

2

RTHERM1 TH 8 5e-1

RTHERM2 8 7 6e-1

RTHERM3 7 6 4

RTHERM4 6 5 5

RTHERM5 5 4 8

RTHERM6 4 3 9

RTHERM7 3 2 15

RTHERM8 2 TL 23

}

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT

CTHERM6

CTHERM7

CTHERM8

RTHERM6

RTHERM7

RTHERM8

0.04 in²

3.2e-1

8.5e-1

0.3

0.28 in²

3.5e-1

9.0e-1

1.8

0.52 in²

4.0e-1

9.0e-1

2.0

0.76 in²

4.0e-1

9.0e-1

2.0

1.0 in²

4.0e-1

9.0e-1

2.0

24

18

12

10

9

36

21

18

16

15

53

37

30

28

23

FDS3992 Rev. B

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

ACEx™

FACT™

ImpliedDisconnect™ PACMAN™

SPM™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™ FRFET™

DOME™

FACT Quiet Series™ ISOPLANAR™

POP™

Stealth™

®

FAST

FASTr™

LittleFET™

MicroFET™

MicroPak™

Power247™

PowerTrench

QFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

®

GlobalOptoisolator™ MICROWIRE™

QS™

EcoSPARK™

E CMOS™

EnSigna™

Across the board. Around the world.™ OCXPro™

The Power Franchise™

Programmable Active Droop™

GTO™

MSX™

MSXPro™

OCX™

QT Optoelectronics™ TinyLogic™

2

HiSeC™

Quiet Series™

TruTranslation™

2

I C™

RapidConfigure™

RapidConnect™

SILENT SWITCHER VCX™

SMART START™

UHC™

UltraFET

®

OPTOLOGIC

OPTOPLANAR™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. I1

电子百科

产品导航

产品型号FDS3992的概述

产品型号FDS3992的Datasheet PDF文件预览

FDS3992相关产品..

FDS3992相关文章