FDS8876现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

April 2005

FDS8876

N-Channel PowerTrench MOSFET

®

30V, 12.5A, 8.2mΩ

Features

General Description

r_DS(ON)= 8.2mΩ, V_GS= 10V, I_D= 12.5A

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using

either synchronous or conventional switching PWM

controllers. It has been optimized for low gate charge, low

r_DS(ON)= 10.2mΩ, V_GS= 4.5V, I_D= 11.4A

High performance trench technology for extremely low

r_DS(ON)

r

_DS(ON)and fast switching speed.

Low gate charge

High power and current handling capability

Applications

DC/DC converters

Branding Dash

5

6

7

8

4

3

2

1

5

1

2

3

4

SO-8

FDS8876 Rev. A

1

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MOSFET Maximum Ratings T_A= 25°C unless otherwise noted

Symbol

V_DSS

V_GS

Parameter

Ratings

30

Units

Drain to Source Voltage

Gate to Source Voltage

Drain Current

V

±20

Continuous (T_A= 25^oC, V_GS= 10V, R_θJA= 50^oC/W)

Continuous (T_A= 25^oC, V_GS= 4.5V, R_θJA= 50^oC/W)

Pulsed

12.5

11.4

A

I_D

Figure 4

105

A

E_AS

Single Pulse Avalanche Energy (Note 1)

mJ

Power dissipation

Derate above 25^oC

2.5

W

P_D

20

mW/^oC

^oC

T_J, T_STG

Operating and Storage Temperature

-55 to 150

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance, Junction to Case (Note 2)

25

50

85

^oC/W

Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)

Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)

Package Marking and Ordering Information

Device Marking

FDS8876

Device

FDS8876

Package

SO-8

Reel Size

330mm

Tape Width

Quantity

12mm

2500 units

FDS8876

FDS8876_NL (Note 4)

SO-8

330mm

Electrical Characteristics ^T_A= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

B_VDSS

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

I_D= 250µA, V_GS= 0V

30

-

V

_DS= 24V

1

I_DSS

µA

V_GS= 0V

T_A= 150^oC

-

250

±100

I_GSS

V_GS= ±20V

-

nA

On Characteristics

V_GS(TH)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 250µA

1.2

-

2.5

V

I_D= 12.5A, V_GS= 10V

-

0.0068 0.0082

0.0083 0.0102

I

_D= 11.4A, V_GS= 4.5V

r_DS(ON)

Drain to Source On Resistance

Ω

I_D= 12.5A, V_GS= 10V,

T_A= 150^oC

-

0.0109 0.0141

Dynamic Characteristics

C_ISS

C_OSS

C_RSS

R_G

Input Capacitance

-

1650

330

180

2.3

28

-

pF

Ω

V_DS= 15V, V_GS= 0V,

f = 1MHz

Output Capacitance

-

Reverse Transfer Capacitance

Gate Resistance

-

V_GS= 0.5V, f = 1MHz

V_GS= 0V to 10V

0.5

4.0

36

20

2

Q_g(TOT)

Q_g(5)

Q_g(TH)

Q_gs

Total Gate Charge at 10V

Total Gate Charge at 5V

Threshold Gate Charge

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

-

nC

V_DD= 15V

_D= 12.5A

I_g= 1.0mA

V_GS= 0V to 5V

V_GS= 0V to 1V

15

I

1.5

4.3

2.8

5.0

-

Q_gs2

Q_gd

-

2

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FDS8876 Rev. A

Switching Characteristics (V_GS= 10V)

t_ON

t_d(ON)

t_r

Turn-On Time

Turn-On Delay Time

Rise Time

-

63

ns

8

-

34

53

19

-

V_DD= 15V, I_D= 12.5A

_GS= 10V, R_GS= 10Ω

V

t_d(OFF)

t_f

Turn-Off Delay Time

Fall Time

-

t_OFF

Turn-Off Time

108

Drain-Source Diode Characteristics

I

_SD= 12.5A

-

1.25

1.0

21

V

V_SD

Source to Drain Diode Voltage

I_SD= 2.1A

t_rr

Reverse Recovery Time

I_SD= 12.5A, dI_SD/dt=100A/µs

ns

nC

Q_RR

Reverse Recovered Charge

10

Notes:

1: Starting T = 25°C, L = 1mH, I = 14.5A, V = 30V, V = 10V.

J

AS

DD

GS

2: R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

θJA

drain pins. R

is guaranteed by design while R

is determined by the user’s board design.

θJC

θJA

2

3: R

is measured with 1.0 in copper on FR-4 board

θJA

4: FDS8876_NL is lead free product. FDS8876_NL marking will appear on the reel label.

3

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FDS8876 Rev. A

Typical Characteristics T_A= 25°C unless otherwise noted

1.2

1.0

0.8

0.6

0.4

0.2

0

16

12

V

= 10V

GS

8

4

0

V

= 4.5V

GS

o

R

=50 C/W

θJA

0

25

50

75

100

125

150

25

50

75

100

125

150

o

T

, AMBIENT TEMPERATURE ( C)

T

, AMBIENT TEMPERATURE ( C)

A

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

o

R

=50 C/W

0.2

θJA

0.1

0.05

0.02

0.01

0.1

P

DM

t

1

0.01

t

2

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t /t

1

2

PEAK T = P

x Z

x R

+ T

A

J

DM

θJA

0.001

-5

-4

-3

-2

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

1400

TRANSCONDUCTANCE

o

T

= 25 C

MAY LIMIT CURRENT

IN THIS REGION

A

FOR TEMPERATURES

ABOVE 25 C DERATE PEAK

CURRENT AS FOLLOWS:

o

V

= 10V

GS

150 - T

A

I = I

25

125

V

= 4.5V

GS

100

10

-5

-4

-3

-2

-1

0

1

2

3

10

t, PULSE WIDTH (s)

10

Figure 4. Peak Current Capability

4

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FDS8876 Rev. A

Typical Characteristics T_A= 25°C unless otherwise noted

100

50

40

30

20

If R = 0

= (L)(I )/(1.3*RATED BV

PULSE DURATION = 80µs

t

- V

DD

)

AV

If R ≠ 0

AS

DSS

DUTY CYCLE = 0.5% MAX

V

= 15V

DD

t

AV

= (L/R)ln[(I *R)/(1.3*RATED BV

AS

- V ) +1]

DSS DD

o

T

= 25 C

J

10

o

STARTING T = 25 C

J

o

T

= 150 C

T

= -55 C

J

o

STARTING T = 150 C

J

10

0

1

2.0

2.5

3.0

3.5

0.01

0.1

1

10

100

t

, TIME IN AVALANCHE (ms)

V

GS

, GATE TO SOURCE VOLTAGE (V)

AV

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Unclamped Inductive Switching

Capability

Figure 6. Transfer Characteristics

50

40

30

20

10

0

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 10V

GS

V

= 5V

GS

40

30

V

= 3.5V

= 3V

GS

I

= 12.5A

D

V

GS

20

10

0

o

T

= 25 C

A

I

= 1A

D

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

2

4

6

8

10

0

0.2

0.4

0.6

0.8

V

, DRAIN TO SOURCE VOLTAGE (V)

V , GATE TO SOURCE VOLTAGE (V)

GS

DS

Figure 7. Saturation Characteristics

Figure 8. Drain to Source On Resistance vs Gate

Voltage and Drain Current

1.6

1.2

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= V , I = 250µA

DS D

GS

1.4

1.2

1.0

0.8

0.6

1.0

0.8

0.6

0.4

V

= 10V, I = 12.5A

D

GS

-80

-40

0

40

80

120

o

160

-80

-40

0

40

80

120

o

160

200

T , JUNCTION TEMPERATURE ( C)

J

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature

Figure 10. Normalized Gate Threshold Voltage vs

Junction Temperature

5

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FDS8876 Rev. A

Typical Characteristics T_A= 25°C unless otherwise noted

1.10

1.05

1.00

0.95

0.90

3000

C

= C + C

GD

ISS

GS

I

= 250µA

D

C

+ C

OSS

DS GD

1000

C

= C

GD

RSS

V

= 0V, f = 1MHz

GS

100

-80

-40

0

40

80

120

160

0.1

1

10

30

o

T , JUNCTION TEMPERATURE ( C)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

J

Figure 11. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

Figure 12. Capacitance vs Drain to Source

Voltage

10

V

= 15V

DD

8

6

4

2

0

WAVEFORMS IN

DESCENDING ORDER:

I

= 12.5A

= 1A

D

0

5

10

15

20

25

30

Q , GATE CHARGE (nC)

g

Figure 13. Gate Charge Waveforms for Constant Gate Currents

6

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FDS8876 Rev. A

Test Circuits and Waveforms

V

BV

DSS

DS

t

P

V

DS

L

I

AS

V

DD

VARY t TO OBTAIN

P

+

-

R

REQUIRED PEAK I

G

AS

V

DD

V

GS

DUT

t

P

I

0V

AS

0

0.01Ω

t

AV

Figure 14. Unclamped Energy Test Circuit

Figure 15. Unclamped Energy Waveforms

V

DS

V

Q

DD

g(TOT)

R

L

V

GS

V

DS

V

= 10V

GS

Q

g(5)

V

GS

+

-

Q

gs2

V

= 5V

GS

V

DD

DUT

V

= 1V

GS

I

g(REF)

0

Q

g(TH)

Q

gs

gd

I

g(REF)

0

Figure 16. Gate Charge Test Circuit

Figure 17. Gate Charge Waveforms

V

DS

t

ON

OFF

t

d(OFF)

t

d(ON)

R

t

f

L

r

V

DS

90%

+

V

GS

V

DD

10%

0

-

DUT

90%

50%

R

GS

V

GS

50%

PULSE WIDTH

10%

V

GS

0

Figure 18. Switching Time Test Circuit

Figure 19. Switching Time Waveforms

7

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FDS8876 Rev. A

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, T_JM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, P_DM, in an

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2. The area, in square inches is the top copper

area including the gate and source pads.

application.

Therefore the application’s ambient

temperature, T_A(^oC), and thermal resistance R_θJA(^oC/W)

must be reviewed to ensure that T_JMis never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

26

R

= 64 + -------------------------------

(EQ. 2)

θ JA

0.23 + Area

(T

– T )

JM

A

(EQ. 1)

P

= ------------------------------

DM

R_θJA

The transient thermal impedance (Z_θJA) is also effected by

varied top copper board area. Figure 22 shows the effect of

copper pad area on single pulse transient thermal

impedance. Each trace represents a copper pad area in

square inches corresponding to the descending list in the

graph. Spice and SABER thermal models are provided for

each of the listed pad areas.

In using surface mount devices such as the SO8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

dissipation ratings. Precise determination of P_DMis complex

and influenced by many factors:

Copper pad area has no perceivable effect on transient

thermal impedance for pulse widths less than 100ms. For

pulse widths less than 100ms the transient thermal

impedance is determined by the die and package.

Therefore, CTHERM1 through CTHERM5 and RTHERM1

through RTHERM5 remain constant for each of the thermal

models. A listing of the model component values is available

in Table 1.

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

200

5. Air flow and board orientation.

R

= 64 + 26/(0.23+Area)

θJA

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

150

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the R_θJAfor the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

100

50

0.001

0.01

0.1

1

2

10

AREA, TOP COPPER AREA (in )

Figure 21. Thermal Resistance vs Mounting

Pad Area

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

0.52 in

0.76 in

1.00 in

120

90

60

30

0

2

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

10

Figure 22. Thermal Impedance vs Mounting Pad Area

8

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FDS8876 Rev. A

PSPICE Electrical Model

.SUBCKT FDS8876 2 1 3 ;

Ca 12 8 10.3e-10

rev January 2005

Cb 15 14 10.3e-10

Cin 6 8 1.6e-9

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

LDRAIN

DPLCAP

DRAIN

2

5

10

Ebreak 11 7 17 18 33.7

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

RLDRAIN

RSLC1

51

DBREAK

+

RSLC2

5

ESLC

11

51

-

+

50

-

17

DBODY

RDRAIN

6

8

EBREAK 18

-

ESG

It 8 17 1

EVTHRES

+

16

21

+

-

19

8

MWEAK

Lgate 1 9 5.29e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 0.18e-10

LGATE

EVTEMP

RGATE

GATE

1

+

6

-

18

22

MMED

9

20

MSTRO

8

RLGATE

RLgate 1 9 52.9

RLdrain 2 5 10

RLsource 3 7 1.8

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

S1A

S2A

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

-

S1B

S2B

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 2.6e-3

Rgate 9 20 2.3

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 3.8e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

13

CB

CA

IT

14

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

22

RVTHRES

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}

.MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=5.6e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=5.7e-10 M=0.52 TT=7e-11 XTI=2)

.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6)

.MODEL DplcapMOD D (CJO=5.3e-10 IS=1e-30 N=10 M=0.37)

.MODEL MmedMOD NMOS (VTO=1.9 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3)

.MODEL MstroMOD NMOS (VTO=2.42 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=1.62 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)

.MODEL RdrainMOD RES (TC1=8.0e-3 TC2=1.0e-6)

.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)

.MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6)

.MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6)

.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

9

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FDS8876 Rev. A

SABER Electrical Model

REV January 2005

template FDS8876 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=5.6e-3,trs1=8e-4,trs2=2e-7,cjo=5.7e-10,m=0.52,tt=7e-11,xti=2)

dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6)

dp..model dplcapmod = (cjo=5.3e-10,isl=10e-30,nl=10,m=0.37)

m..model mmedmod = (type=_n,vto=1.9,kp=5,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=2.42,kp=150,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=1.62,kp=0.02,is=1e-30, tox=1,rs=0.1)

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5)

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4)

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5)

c.ca n12 n8 = 10.3e-10

LDRAIN

DPLCAP

DRAIN

2

5

10

RLDRAIN

RSLC1

51

c.cb n15 n14 = 10.3e-10

c.cin n6 n8 = 1.6e-9

RSLC2

ISCL

DBREAK

11

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

50

-

RDRAIN

6

8

ESG

DBODY

EVTHRES

+

16

21

+

-

19

8

spe.ebreak n11 n7 n17 n18 = 33.7

MWEAK

LGATE

EVTEMP

spe.eds n14 n8 n5 n8 = 1

RGATE

GATE

6

+

-

18

22

EBREAK

+

MMED

1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

9

20

MSTRO

8

17

18

-

RLGATE

LSOURCE

CIN

SOURCE

3

7

RSOURCE

i.it n8 n17 = 1

RLSOURCE

S1A

S2A

RBREAK

l.lgate n1 n9 = 5.29e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 0.18e-9

12

15

13

8

14

13

17

18

RVTEMP

19

S1B

S2B

13

CB

CA

res.rlgate n1 n9 = 52.9

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 1.8

IT

14

-

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

22

RVTHRES

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7

res.rdrain n50 n16 = 2.6e-3, tc1=8.0e-3,tc2=1.0e-6

res.rgate n9 n20 = 2.3

res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 3.8e-3, tc1=1e-3,tc2=3e-6

res.rvthres n22 n8 = 1, tc1=-2.0e-3,tc2=-6e-6

res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))

}

10

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FDS8876 Rev. A

SPICE Thermal Model

JUNCTION

th

REV January 2005

FDS8876

Copper Area =1.0 in²

CTHERM1 TH 8 2.0e-3

CTHERM2 8 7 5.0e-3

CTHERM3 7 6 1.0e-2

CTHERM4 6 5 4.0e-2

CTHERM5 5 4 9.0e-2

CTHERM6 4 3 2e-1

CTHERM7 3 2 1

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

CTHERM1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

8

7

CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1

RTHERM2 8 7 5e-1

RTHERM3 7 6 1

RTHERM4 6 5 5

RTHERM5 5 4 8

RTHERM6 4 3 12

RTHERM7 3 2 18

RTHERM8 2 TL 25

6

5

SABER Thermal Model

SABER thermal model FDS8876

Copper Area = 1.0 in²

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 8 =2.0e-3

ctherm.ctherm2 8 7 =5.0e-3

ctherm.ctherm3 7 6 =1.0e-2

ctherm.ctherm4 6 5 =4.0e-2

ctherm.ctherm5 5 4 =9.0e-2

ctherm.ctherm6 4 3 =2e-1

ctherm.ctherm7 3 2 1

4

3

2

ctherm.ctherm8 2 tl 3

rtherm.rtherm1 th 8 =1e-1

rtherm.rtherm2 8 7 =5e-1

rtherm.rtherm3 7 6 =1

rtherm.rtherm4 6 5 =5

rtherm.rtherm5 5 4 =8

rtherm.rtherm6 4 3 =12

rtherm.rtherm7 3 2 =18

rtherm.rtherm8 2 tl =25

}

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT

CTHERM6

CTHERM7

CTHERM8

RTHERM6

RTHERM7

RTHERM8

0.04 in²

1.2e-1

0.5

0.28 in²

1.5e-1

1.0

0.52 in²

2.0e-1

1.0

0.76 in²

2.0e-1

1.0

1.0 in²

2.0e-1

1.0

3.0

12

1.3

2.8

3.0

26

20

15

13

39

24

21

19

18

55

38.7

31.3

29.7

25

11

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FDS8876 Rev. A

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when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

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This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

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The datasheet is printed for reference information only.

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FDS8876 Rev. A

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