FM25040B-GTR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>F字母起始型号索引_>F字母起始型号索引第292页更新时间：2024-12-04 16:51:50

产品型号FM25040B-GTR的概述

芯片FM25040B-GTR的概述 FM25040B-GTR是一款高性能、低功耗的非易失性存储器，属于FM系列产品线。这款芯片采用了最新的EEPROM技术，广泛应用于需要存储配置数据和用户设置的嵌入式系统中。FM25040B-GTR因其高可靠性、快速的读写速度和较长的写入寿命，成为许多电子产品中的常见存储器解决方案。详细参数 FM25040B-GTR的主要参数如下： - 存储容量：512字节（64x8位） - 接口：I2C - 工作电压：2.5V至5.5V - 工作温度范围：-40°C至85°C - 写入周期：最多5毫秒 - 擦写寿命：100,000次 - 数据保持时间：超过20年 - 封装类型：SOP-8 - 引脚数量：8个 - 地址空间：支持多达32个设备连接 FM25040B-GTR具有较小的功耗特点，适用于便携式设备，同时其为寄存器分配机制也有助于简化系统的设计。厂家、包...

产品型号FM25040B-GTR的Datasheet PDF文件预览

Preliminary

FM25040B

4Kb Serial 5V F-RAM Memory

Features

4K bit Ferroelectric Nonvolatile RAM

Sophisticated Write Protection Scheme

•

Hardware Protection

Software Protection

•

Organized as 512 x 8 bits

High Endurance 1 Trillion (10¹²) Read/Writes

38 year Data Retention

Low Power Consumption

NoDelay™ Writes

Advanced High-Reliability Ferroelectric Process

•

250 µA Active Current (1 MHz)

4 µA (typ.) Standby Current

Very Fast Serial Peripheral Interface - SPI

Industry Standard Configuration

•

Up to 20 MHz maximum Bus Frequency

Direct hardware replacement for EEPROM

SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

•

Industrial Temperature -40° C to +85° C

8-pin “Green”/RoHS SOIC (-G)

Description

Pin Configuration

The FM25040B is a 4-kilobit nonvolatile memory

employing an advanced ferroelectric process. A

ferroelectric random access memory or F-RAM is

nonvolatile but operates in other respects as a RAM.

It provides reliable data retention for 38 years while

eliminating the complexities, overhead, and system

level reliability problems caused by EEPROM and

other nonvolatile memories.

VSS

VDD

HOLD

SCK

The FM25040B performs write operations at bus

speed. No write delays are incurred. Data is written to

the memory array immediately after it has been

successfully transferred to the device. The next bus

cycle may commence immediately without the need

for data polling. The FM25040B is capable of

supporting up to 10¹²read/write cycles, or a million

times more write cycles than EEPROM.

Pin Names

/CS

Function

Chip Select

/WP

Write Protect

Hold

Serial Clock

Serial Data Input

Serial Data Output

Supply Voltage 5V

Ground

/HOLD

SCK

VDD

VSS

These capabilities make the FM25040B ideal for

nonvolatile memory applications requiring frequent

or rapid writes. Examples range from data collection,

where the number of write cycles may be critical, to

demanding industrial controls where the long write

time of EEPROM can cause data loss.

Ordering Information

FM25040B-G

“Green” 8-pin SOIC

The FM25040B provides substantial benefits to users

FM25040B-GTR

“Green” 8-pin SOIC,

of serial EEPROM, in

hardware drop-in

Tape & Reel

replacement. The FM25040B uses the high-speed

SPI bus, which enhances the high-speed write

capability of F-RAM technology. The specifications

are guaranteed over an industrial temperature range

of -40°C to +85°C.

This is a product that has fixed target specifications but are subject

to change pending characterization results.

Ramtron International Corporation

1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-F-RAM, (719) 481-7000

www.ramtron.com

Rev. 1.2

Feb. 2011

Page 1 of 13

FM25040B - 4Kb 5V SPI F-RAM

Instruction Decode

Clock Generator

Control Logic

HOLD

SCK

Write Protect

64 x 64

FRAM Array

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

Figure 1. Block Diagram

Pin Descriptions

Pin Name

I/O

Description

/CS

Input

Chip Select. This active-low input activates the device. When high, the device enters low-

power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the

device internally activates the SCK signal. A falling edge on /CS must occur prior to every

op-code.

SCK

Input

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the

rising edge and outputs occur on the falling edge. Since the device is static, the clock

frequency may be any value between 0 and 20 MHz and may be interrupted at any time.

Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for

another task. When /HOLD is low, the current operation is suspended. The device ignores

any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low.

Write Protect: This active-low pin prevents all write operations, including those to the

status register. If high, write access is determined by the other write protection features, as

controlled through the status register. A complete explanation of write protection is

provided on page 6.

/HOLD

/WP

Input

Serial Input: All input data is driven to this pin. The pin is sampled on the rising edge of

SCK and is ignored at other times. It should always be driven to a valid logic level to meet

_DDspecifications.

* SI may be connected to SO for a single pin data interface.

Output

Serial Output: SO is the data output pin. It is driven actively during a read and remains tri-

state at all other times including when /HOLD is low. Data transitions are driven on the

falling edge of the serial clock.

* SO can be connected to SI for a single pin data interface since the part communicates in

half-duplex fashion.

Supply Voltage: 5V

Ground

VDD

VSS

Supply

Rev. 1.2

Feb. 2011

Page 2 of 13

FM25040B - 4Kb 5V SPI F-RAM

MHz. This high-speed serial bus provides high

Overview

performance serial communication to

host

The FM25040B is a serial F-RAM memory. The

memory array is logically organized as 512 x 8 and is

accessed using an industry standard Serial Peripheral

Interface or SPI bus. Functional operation of the F-

RAM is similar to serial EEPROMs. The major

difference between the FM25040B and a serial

EEPROM with the same pin-out relates to its

superior write performance. This makes the

FM25040B a drop-in replacement for most 4Kb SPI

EEPROMs that support Modes 0 & 3.

microcontroller. Many common microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25040B operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. A typical system

configuration uses one or more FM25040B devices

with a microcontroller that has a dedicated SPI port,

as Figure 2 illustrates. Note that the clock, data-in,

and data-out pins are common among all devices.

The Chip Select and Hold pins must be driven

separately for each FM25040B device.

Memory Architecture

When accessing the FM25040B, the user addresses

512 locations each with 8 data bits. These data bits

are shifted serially. The addresses are accessed using

the SPI protocol, which includes a chip select (to

permit multiple devices on the bus), an op-code

including the upper address bit, and a word address.

The word address consists of the lower 8-address

bits. The complete address of 9-bits specifies each

byte address uniquely.

For a microcontroller that has no dedicated SPI bus, a

general purpose port may be used. To reduce

hardware resources on the controller, it is possible to

connect the two data pins (SI, SO) together and tie

off (high) the /HOLD pin. Figure 3 shows a

configuration that uses only three pins.

Protocol Overview

Most functions of the FM25040B either are

controlled by the SPI interface or are handled

automatically by on-board circuitry. The access time

for memory operation essentially is zero, beyond the

time needed for the serial protocol. That is, the

memory is read or written at the speed of the SPI bus.

Unlike an EEPROM, it is not necessary to poll the

device for a ready condition since writes occur at bus

speed. That is, by the time a new bus transaction can

be shifted into the part, a write operation will be

complete. This is explained in more detail in the

interface section that follows.

The SPI interface is a synchronous serial interface

using clock and data lines. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25040B will begin monitoring

the clock and data lines. The relationship between the

falling edge of /CS, the clock and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25040B supports Modes 0 and 3. Figure 4 shows

the required signal relationships for Modes 0 and 3.

For both modes, data is clocked into the FM25040B

on the rising edge of SCK and data is expected on the

first rising edge after /CS goes active. If the clock

begins from a high state, it will fall prior to beginning

data transfer in order to create the first rising edge.

Users expect several obvious system benefits from

the FM25040B due to its fast write cycle and high

endurance as compared with EEPROM. However

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than an EEPROM

since it is completed quickly. By contrast, an

EEPROM requiring milliseconds to write is

vulnerable to noise during much of the cycle.

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the part. After /CS

is activated the first byte transferred from the bus

master is the op-code. Following the op-code, any

addresses and data are then transferred. Note that the

WREN and WRDI op-codes are commands with no

subsequent data transfer.

Note that the FM25040B contains no power

management circuits other than a simple internal

power-on reset. It is the user’s responsibility to

ensure that V_DDis within datasheet tolerances to

prevent incorrect operation. It is recommended

that the part is not powered down with chip

enable active.

Important: The /CS must go inactive (high) after

an operation is complete and before a new op-code

can be issued. There is one valid op-code only per

active chip select.

Serial Peripheral Interface – SPI Bus

The FM25040B employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to 20

Rev. 1.2

Feb. 2011

Page 3 of 13

FM25040B - 4Kb 5V SPI F-RAM

Figure 2. System Configuration with SPI port

Figure 3. System Configuration without SPI port

SPI Mode 0: CPOL=0, CPHA=0

SPI Mode 3: CPOL=1, CPHA=1

Figure 4. SPI Modes 0 & 3

Rev. 1.2

Feb. 2011

Page 4 of 13

FM25040B - 4Kb 5V SPI F-RAM

WREN - Set Write Enable Latch

The FM25040B will power up with writes disabled.

The WREN command must be issued prior to any

write operation. Sending the WREN op-code will

allow the user to issue subsequent op-codes for

write operations. These include writing the status

Data Transfer

All data transfers to and from the FM25040B occur

in 8-bit groups. They are synchronized to the clock

signal (SCK) and they transfer most significant bit

(MSB) first. The serial input data is clocked in on

the rising edge of SCK. The serial data output is

driven from the falling edge of SCK.

Command Structure

Sending the WREN op-code causes the internal

Write Enable Latch to be set. A flag bit in the status

WEL=1 indicates that writes are permitted. A write

to the status register has no effect on the WEL bit.

Completing any write operation will automatically

clear the write-enable latch and prevent further

writes without another WREN command. Figure 5

below illustrates the WREN command bus

configuration.

There are six commands called op-codes that can be

issued by the bus master to the FM25040B. They are

listed in the table below. These op-codes control the

functions performed by the memory. They can be

divided into three categories. First, there are

commands that have no subsequent data transfer.

They perform a single function, such as, enabling a

write operation. Second are commands followed by

one byte, either in or out. They operate on the status

transactions followed by address and one or more

bytes of data.

WRDI - Write Disable

The WRDI command disables all write activity by

clearing the Write Enable Latch. The user can verify

that writes are disabled by reading the WEL bit in

the status register and verifying that WEL=0. Figure

6 illustrates the WRDI command bus configuration.

Table 1. Op-code Commands

Name

Description

Op-code

0000_0110b

0000_0100b

0000_0101b

0000_0001b

0000_A011b

0000_A010b

Set Write Enable Latch

Write Disable

WREN

WRDI

RDSR

WRSR

READ

WRITE

Read Status Register

Write Status Register

Read Memory Data

Write Memory Data

Figure 5. WREN Bus Configuration

Figure 6. WRDI Bus Configuration

Rev. 1.2

Feb. 2011

Page 5 of 13

FM25040B - 4Kb 5V SPI F-RAM

WRSR – Write Status Register

RDSR - Read Status Register

The RDSR command allows the bus master to verify

the contents of the Status Register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25040B will return one byte with the

contents of the Status Register. The Status Register is

described in detail in the Status Register & Write

Protection section.

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status Register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive. Note

that on the FM25040B, /WP prevents writing to the

Status Register and the memory array. Prior to

sending the WRSR command, the user must send a

WREN command to enable writes. Note that

executing a WRSR command is a write operation and

therefore clears the Write Enable Latch. The bus

timing for RDSR and WRSR are shown below.

Figure 7. RDSR Bus Timing

Figure 8. WRSR Bus Timing

whether a write cycle is complete or not. The BP1 and

Status Register & Write Protection

BP0 bits control write protection features. They are

nonvolatile (shaded yellow). The WEL flag indicates

the state of the Write Enable Latch. This bit is

internally set by the WREN command and is cleared

by terminating a write cycle (/CS high) or by using

the WRDI command.

The write protection features of the FM25040B are

multi-tiered. First, a WREN op-code must be issued

prior to any write operation. Assuming that writes

are enabled using WREN, writes to memory are

controlled by the /WP pin and the Status Register.

When /WP is low, the entire part is write-protected.

When /WP is high, the memory protection is subject

to the Status register. Writes to the Status Register

are performed using the WREN and WRSR

commands and subject to the /WP pin. The Status

BP1 and BP0 are memory block write protection bits.

They specify portions of memory that are write-

protected as shown in the following table.

Table 3. Block Memory Write Protection

BP1

BP0

Protected Address Range

None

180h to 1FFh (upper ¼)

100h to 1FFH (upper ½)

000h to 1FFh (all)

Table 2. Status Register

Bit

BP1

BP0

Name

WEL

Bits 0 and 4-7 are fixed at 0 and cannot be modified.

Note that bit 0 (/RDY in EEPROMs) is wired low

since F-RAM writes have no delay and the memory

is never busy. All EEPROMs use Ready to indicate

Rev. 1.2

Feb. 2011

Page 6 of 13

FM25040B - 4Kb 5V SPI F-RAM

The BP1 and BP0 bits and the Write Enable Latch

are the only mechanisms that protect the memory

from writes. The remaining write protection features

protect inadvertent changes to the block protect bits.

The BP1 and BP0 bits allow software to selectively

write protect the array. These settings are only used

when the /WP pin is inactive and the WREN

command has been issued. The following table

summarizes the write protection conditions.

Table 4. Write Protection

WEL

/WP

Protected Blocks

Protected

Unprotected Blocks

Status Register

Protected

Unprotected

Memory Operation

Read Operation

The SPI interface, with its relatively high maximum

clock frequency, highlights the fast write capability

of the F-RAM technology. Unlike SPI-bus

EEPROMs, the FM25040B can perform sequential

writes at bus speed. No page register is needed and

any number of sequential writes may be performed.

After the falling edge of /CS, the bus master can issue

a READ op-code. Part of this op-code includes the

upper bit of the memory address. The next byte is the

lower 8-bits of the address. In total, the 9-bits specify

the address of the first byte of the read operation.

After the op-code is complete, the SI pin is ignored.

The bus master then issues 8 clocks, with one bit read

out for each. Addresses are incremented internally as

long as the bus master continues to issue clocks. If

the last address of 1FFh is reached, the counter will

roll over to 000h. Data is read MSB first. The rising

edge of /CS terminates a READ op-code operation..

The bus configuration for read and write operations is

shown below.

Write Operation

All writes to the memory array begin with a WREN

op-code. The bus master then issues a WRITE op-

code. Part of this op-code includes the upper bit of

the memory address. Bit 3 in the op-code corresponds

to A8. The next byte is the lower 8-bits of the address

A7-A0. In total, the 9-bits specify the address of the

first byte of the write operation. Subsequent bytes are

data and they are written sequentially. Addresses are

incremented internally as long as the bus master

continues to issue clocks. If the last address of 1FFh

is reached, the counter will roll over to 000h. Data is

written MSB first.

Hold

The /HOLD pin can be used to interrupt a serial

operation without aborting it. If the bus master takes

the /HOLD pin low while SCK is low, the current

operation will pause. Taking the /HOLD pin high

while SCK is low will resume an operation. The

transitions of /HOLD must occur while SCK is low,

but the SCK pin can toggle during a hold state.

Unlike EEPROMs, any number of bytes can be

written sequentially and each byte is written to

memory immediately after it is clocked in (after the

8^thclock). The rising edge of /CS terminates a

WRITE op-code operation.

Rev. 1.2

Feb. 2011

Page 7 of 13

FM25040B - 4Kb 5V SPI F-RAM

SCK

op-code

Byte Address

Data

MSB

LSB MSB

LSB

Hi-Z

Figure 9. Memory Write

SCK

op-code

Byte Address

MSB

LSB

Data Out

Hi-Z

MSB

LSB

Figure 10. Memory Read

Endurance can be optimized by ensuring frequently

accessed data is located in different rows.

Regardless, F-RAM read and write endurance is

effectively unlimited at the 20MHz clock speed.

Even at 2000 accesses per second to the same row, 15

years time will elapse before 10¹²endurance cycles

occur.

Endurance

Internally, a F-RAM operates with a read and restore

mechanism. Therefore, endurance cycles are applied

for each access: read or write. The F-RAM

architecture is based on an array of rows and

columns. Each access causes a cycle for an entire

row. In the FM25040B, a row is 64 bits wide. Every

8-byte boundary marks the beginning of a new row.

Rev. 1.2

Feb. 2011

Page 8 of 13

FM25040B - 4Kb 5V SPI F-RAM

Electrical Specifications

Absolute Maximum Ratings

Symbol

Description

Ratings

V_DD

V_IN

Power Supply Voltage with respect to V_SS

Voltage on any pin with respect to V_SS

-1.0V to +7.0V

and V_IN< V_DD+1.0V

T_STG

T_LEAD

V_ESD

Storage Temperature

-55°C to + 125°C

260° C

Lead Temperature (Soldering, 10 seconds)

Electrostatic Discharge Voltage

- Human Body Model (AEC-Q100-002 Rev. E)

- Charged Device Model (AEC-Q100-011 Rev. B)

- Machine Model (AEC-Q100-003 Rev. E)

Package Moisture Sensitivity Level

3.5kV

1.25kV

250V

MSL-1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating

only, and the functional operation of the device at these or any other conditions above those listed in the operational section of

this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device

reliability.

DC Operating Conditions (T_A= -40° C to + 85° C, V_DD= 4.5V to 5.5V unless otherwise specified)

Symbol

V_DD

Parameter

Min

Typ

Max

Units

Notes

Main Power Supply

VDD Supply Current

@ SCK = 1.0 MHz

@ SCK = 20.0 MHz

Standby Current

4.5

5.0

5.5

I_DD

0.25

4.0

I_SB

I_LI

I_LO

V_IH

V_IL

V_OH

µA

Input Leakage Current

Output Leakage Current

Input High Voltage

Input Low Voltage

Output High Voltage

@ I_OH= -1 mA

Output Low Voltage

@ I_OL= 2 mA

V_DD+ 0.3

0.3 V_DD

0.7 V_DD

-0.3

V_DD– 0.8

V_OL

0.4

V_HYS

Input Hysteresis

0.05 V_DD

Notes

1. SCK toggling between V_DD-0.3V and V_SS, other inputs V_SSor V_DD-0.3V.

2. SCK = SI = /CS=V_DD. All inputs V_SSor V_DD

3. V_INor V_OUT= V_SSto V_DD

4. This parameter is periodically sampled and not 100% tested.

Rev. 1.2

Feb. 2011

Page 9 of 13

FM25040B - 4Kb 5V SPI F-RAM

AC Parameters (T_A= -40° C to + 85° C, V_DD= 4.5V to 5.5V unless otherwise specified)

Symbol

f_CK

t_CH

t_CL

Parameter

Min

Max

Units

MHz

Notes

SCK Clock Frequency

Clock High Time

Clock Low Time

Chip Select Setup

Chip Select Hold

Output Disable

t_CSU

t_CSH

t_OD

t_ODV

t_OH

t_D

Output Data Valid

Output Hold

Deselect Time

t_R

Data In Rise Time

Data In Fall Time

Data Setup Time

Data Hold Time

/Hold Setup Time

/Hold Hold Time

/Hold Low to Hi-Z

/Hold High to Data Active

1,3

t_F

t_SU

t_H

t_HS

t_HH

t_HZ

t_LZ

Notes

1. t_CH+ t_CL= 1/f_CK

2. Rise and fall times measured between 10% and 90% of waveform.

3. This parameter is characterized and not 100% tested.

Capacitance (T_A= 25°C , f=1.0 MHz, V_DD= 5V)

Symbol

C_O

Parameter

Max

Units

Notes

Output Capacitance (SO)

Input Capacitance

C_I

Notes

1. This parameter is periodically sampled and not 100% tested.

AC Test Conditions

Input Pulse Levels

10% and 90% of V_DD

Input Rise and Fall Times

Input and Output Timing Levels

Output Load Capacitance

5 ns

0.5 V_DD

30 pF

Data Retention

Symbol

Parameter

Min

Max

Units

Years

Notes

T_DR

+85ºC

+80ºC

+75ºC

Rev. 1.2

Feb. 2011

Page 10 of 13

FM25040B - 4Kb 5V SPI F-RAM

Serial Data Bus Timing

tCSH

tCL

tCH

tCSU

1/tCK

SCK

tSU

tOH

tODV

tOD

/Hold Timing

tHS

tHH

SCK

tHH

tHS

HOLD

tHZ

tLZ

Power Cycle Timing

Power Cycle Timing (T_A= -40° C to + 85° C, V_DD= 4.5V to 5.5V unless otherwise specified)

Symbol

t_PU

Parameter

Min

Max

Units

µs

Notes

V_DD(min) to First Access Start

t_PD

Last Access Complete to V_DD(min)

V_DDRise Time

t_VR

µs/V

t_VF

V_DDFall Time

100

Notes

1. Slope measured at any point on V_DDwaveform.

Rev. 1.2

Feb. 2011

Page 11 of 13

FM25040B - 4Kb 5V SPI F-RAM

Mechanical Drawing

(8-pin SOIC - JEDEC Standard MS-012, Variation AA)

Refer to JEDEC MS-012 for complete dimensions and notes.

All dimensions in millimeters.

SOIC Package Marking Scheme

Legend:

XXXXXX= part number, P= package type (G=SOIC)

R=rev code, LLLLLLL= lot code

XXXXXXX-P

RLLLLLLL

RICYYWW

RIC=Ramtron Int’l Corp, YY=year, WW=work week

Example: FM25040B, “Green” SOIC package, Year 2010, Work Week 51

FM25040B-G

A00002G1

RIC1051

Rev. 1.2

Feb. 2011

Page 12 of 13

FM25040B - 4Kb 5V SPI F-RAM

Revision History

Revision

1.0

Date

Summary

11/10/2010

1/31/2011

2/15/2011

Initial Release

1.1

Added ESD ratings.

Changed t_PUand t_VFspec limits.

1.2

Rev. 1.2

Feb. 2011

Page 13 of 13

FM25040B-GTR相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

FM25040B-GTR产品参数

型号:	FM25040B-GTR
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	RAMTRON INTERNATIONAL CORP
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	unknown
HTS代码：	8542.32.00.71
风险等级：	5.15
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
内存密度：	4096 bit
内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	8
湿度敏感等级：	1
功能数量：	1
端子数量：	8
字数：	512 words
字数代码：	512
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	512X8
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最大待机电流：	0.00001 A
子类别：	SRAMs
最大压摆率：	0.004 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

电子百科

产品导航

产品型号FM25040B-GTR的概述

产品型号FM25040B-GTR的Datasheet PDF文件预览

FM25040B-GTR相关产品

FM25040B-GTR相关文章

IC37:专业IC行业平台