FQA55N10各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号FQA55N10的概述

芯片FQA55N10的概述 FQA55N10是一款高性能N沟道MOSFET（金属氧化物半导体场效应晶体管），广泛应用于开关电源、功率放大器及其他电流控制电路。其主要特点为低导通电阻和高电流能力，使其在许多电子设备中成为理想选择。由于其高效能，FQA55N10在电源管理和功率转换等领域得到了广泛应用。芯片FQA55N10的详细参数 FQA55N10的主要参数如下： - 最大漏极-源极电压（Vds）：100V - 最大漏极电流（Id）：55A - 最低栅极阈值电压（Vgs(th)）：2V 至 4V - 导通电阻（Rds(on)）：典型值在10mΩ（Vgs=10V时） - 栅源电压（Vgs）：±20V - 最大功耗（Pd）：94W - 工作温度范围（Tj）：-55°C 至 150°C 此外，FQA55N10的开关速度极快，非常适合高频率的应用，这使其在诸如DC-DC转换器、汽车电子及电动汽...

产品型号FQA55N10的Datasheet PDF文件预览

August 2000

QFET

FQA55N10

100V N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as audio amplifier,

high efficiency switching DC/DC converters, and DC motor

control.

•

61A, 100V, R

= 0.026Ω @V = 10 V

DS(on) GS

Low gate charge ( typical 75 nC)

Low Crss ( typical 130 pF)

Fast switching

100% avalanche tested

Improved dv/dt capability

175°C maximum junction temperature rating

! "

G !

TO-3P

FQA Series

D S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

Symbol

Parameter

FQA55N10

100

Units

Drain-Source Voltage

DSS

- Continuous (T = 25°C)

Drain Current

- Continuous (T = 100°C)

43.1

(Note 1)

Drain Current

- Pulsed

244

Gate-Source Voltage

± 25

GSS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

1100

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

V/ns

dv/dt

6.0

Power Dissipation (T = 25°C)

190

- Derate above 25°C

Operating and Storage Temperature Range

1.27

W/°C

°C

T , T

-55 to +175

STG

Maximum lead temperature for soldering purposes,

300

°C

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Thermal Resistance, Junction-to-Case

Thermal Resistance, Case-to-Sink

Thermal Resistance, Junction-to-Ambient

Typ

Max

0.79

Units

°C/W

θJC

θCS

θJA

0.24

Rev. A, July 2000

Electrical Characteristics

T = 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

100

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

= 250 µA, Referenced to 25°C

0.1

V/°C

∆T

= 100 V, V = 0 V

µA

DSS

Zero Gate Voltage Drain Current

= 80 V, T = 150°C

= 25 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

GSSF

= -25 V, V = 0 V

GSSR

On Characteristics

= V , I = 250 µA

Gate Threshold Voltage

2.0

4.0

Ω

GS(th)

Static Drain-Source

On-Resistance

DS(on)

= 10 V, I = 30.5 A

0.021 0.026

= 40 V, I = 30.5 A

(Note 4)

Forward Transconductance

Dynamic Characteristics

Input Capacitance

2100

640

2730

830

iss

= 25 V, V = 0 V,

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

130

170

Switching Characteristics

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

250

110

140

510

230

290

d(on)

= 50 V, I = 55 A,

= 25 Ω

d(off)

(Note 4, 5)

= 80 V, I = 55 A,

= 10 V

Drain-Source Diode Characteristics and Maximum Ratings

Maximum Continuous Drain-Source Diode Forward Current

244

1.5

Maximum Pulsed Drain-Source Diode Forward Current

= 0 V, I = 61 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

= 0 V, I = 55 A,

100

380

(Note 4)

dI / dt = 100 A/µs

Reverse Recovery Charge

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 0.44mH, I = 61A, V = 25V, R = 25 Ω, Starting T = 25°C

3. I ≤ 55A, di/dt ≤ 300A/µs, V ≤ BV Starting T = 25°C

DSS, J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A, July 2000

Typical Characteristics

V_GS

Top :

15.0 V

10.0 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

10²

10¹

10⁰

10²

10¹

10⁰

Bottom : 4.5 V

℃

175

℃

※

Notes :

※

Notes :

℃

-55

1. 250 s Pulse Test

1. V_DS= 40V

℃

2. T_C= 25

2. 250 s Pulse Test

-1

10^-1

10⁰

10¹

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

0.12

0.09

0.06

0.03

0.00

10²

10¹

10⁰

V_GS= 10V

V_GS= 20V

℃

175

※

Notes :

1. V_GS= 0V

※

℃

Note : T = 25

2. 250 s Pulse Test

-1

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

120

180

240

300

I_D, Drain Current [A]

V_SD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

6000

5000

4000

3000

2000

1000

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C_gd

_rss= C

V_DS= 50V

V_DS= 80V

iss

※

Notes :

C_oss

1. V_GS= 0 V

2. f = 1 MHz

rss

※

Note : I_D= 55A

-1

10⁰

10¹

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A, July 2000

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※Notes :

1. V_GS= 0 V

2. I_D= 250 μA

0.9

※

Notes :

1. V_GS= 10 V

2. I_D= 27.5 A

0.8

-100

-50

100

150

200

-100

-50

100

150

200

T_J, Junction Temperature [^oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

10³

Operation in This Area

is Limited by R _DS(on)

10 µs

10²

10¹

10⁰

100 µs

1 ms

10 ms

※

Notes :

1. T_C= 25 ^o

2. T_J= 175 ^o

3. Single Pulse

-1

10⁰

10¹

10²

100

125

150

175

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

1 0 ⁰

D = 0 .5

0 .2

※

N o te s

1 . Z _θ_{J C}(t)

2 . D u ty F a c to r, D = t₁/t₂

3 . T _{J M}T _CP _DZ _θ_{J C}(t)

℃

/W M a x.

0 .7 9

1 0 ^-1

0 .1

0 .0 5

P_DM

0 .0 2

t₁

0 .0 1

t₂

s in g le p u ls e

1 0 ^-2

1 0 ^-5

1 0 ^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t₁, S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Curve

Rev. A, July 2000

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50KΩ

as DUT

Q_g

12V

200nF

10V

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

10V

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

----

E_AS

L I_AS

V_DS

I _D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. A, July 2000

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

V_DS

I _SD

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A, July 2000

Package Dimensions

TO-3P

15.60 ±0.20

4.80 ±0.20

13.60 ±0.20

9.60 ±0.20

+0.15

ø3.20 ±0.10

1.50

–0.05

2.00 ±0.20

3.00 ±0.20

1.00 ±0.20

1.40 ±0.20

+0.15

–0.05

0.60

5.45TYP

[5.45 ±0.30]

5.45TYP

[5.45 ±0.30]

Rev. A, July 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

HiSeC™

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

Bottomless™

CoolFET™

CROSSVOLT™

E²CMOS™

FACT™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench^®

QFET™

VCX™

FACT Quiet Series™

QS™

FAST^®

Quiet Series™

SuperSOT™-3

SuperSOT™-6

FASTr™

GTO™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL.

As used herein:

result in significant injury to the user.

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. A, January 2000

FQA55N10相关文章

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FQA55N10产品参数

型号:	FQA55N10
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	TO-3P
包装说明：	FLANGE MOUNT, R-PSFM-T3
针数：	3
Reach Compliance Code：	compliant
ECCN代码：	EAR99
风险等级：	5.34
雪崩能效等级（Eas）：	1100 mJ
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	100 V
最大漏极电流 (Abs) (ID)：	61 A
最大漏极电流 (ID)：	61 A
最大漏源导通电阻：	0.026 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：	R-PSFM-T3
JESD-609代码：	e3
元件数量：	1
端子数量：	3
工作模式：	ENHANCEMENT MODE
最高工作温度：	175 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	FLANGE MOUNT
峰值回流温度（摄氏度）：	NOT APPLICABLE
极性/信道类型：	N-CHANNEL
最大功率耗散 (Abs)：	190 W
最大脉冲漏极电流 (IDM)：	244 A
认证状态：	Not Qualified
子类别：	FET General Purpose Power
表面贴装：	NO
端子面层：	Matte Tin (Sn)
端子形式：	THROUGH-HOLE
端子位置：	SINGLE
处于峰值回流温度下的最长时间：	NOT APPLICABLE
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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