FSQ0270RNA原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

December 2006

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA

Green Mode Fairchild Power Switch (FPS™)

Features

Description

Internal Avalanche Rugged 700V SenseFET

Consumes only 0.8W at 230 V_AC& 0.5W Load with

Burst-Mode Operation

Precision Fixed Operating Frequency, 100kHz

Internal Start-up Circuit and Built-in Soft-Start

The FSQ0170RNA, FSQ0270RNA, FSQ0370RNA

consists of an integrated current mode Pulse Width

Modulator (PWM) and an avalanche-rugged 700V Sense

FET. It is specifically designed for high-performance off-

line Switch Mode Power Supplies (SMPS) with minimal

external components. The integrated PWM controller

features include: a fixed-frequency generating oscillator,

Under-Voltage Lockout (UVLO) protection, Leading

Edge Blanking (LEB), an optimized gate turn-on/turn-off

driver, Thermal Shutdown (TSD) protection, and

temperature compensated precision current sources for

loop compensation and fault protection circuitry.

Pulse-by-Pulse Current Limiting and Auto-Restart

Mode

Over-Voltage Protection (OVP), Overload Protection

(OLP), Internal Thermal Shutdown Function (TSD)

Under-Voltage Lockout (UVLO)

Low Operating Current (3mA)

Adjustable Peak Current Limit

Compared to a discrete MOSFET and controller or RCC

switching converter solution, the FSQ0170RNA,

FSQ0270RNA, FSQ0370RNA reduces total component

count, design size, and weight while increasing

efficiency, productivity, and system reliability. These

devices provide a basic platform that is well suited for the

design of cost-effective flyback converters, as in PC

auxiliary power supplies.

Applications

Auxiliary Power Supply for PC and Server

SMPS for VCR, SVR, STB, DVD & DVCD Player,

Printer, Facsimile & Scanner

Adapter for Camcorder

Related Application Notes

AN-4134: Design Guidelines for Off-line Forward

8-DIP

Converters Using Fairchild Power Switch (FPS™)

AN-4137: Design Guidelines for Off-line Flyback

Converters Using Fairchild Power Switch (FPS™)

AN-4141: Troubleshooting and Design Tips for

Fairchild Power Switch (FPS™) Flyback Applications

AN-4147: Design Guidelines for RCD Snubber of

Flyback

AN-4148: Audible Noise Reduction Techniques for

FPS™ Applications

Ordering Information

Product Number

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

Package

8DIP

Marking Code

Q0170R

BV

f

R

DS(ON) (MAX.)

DSS

OSC

700V

100kHz

11Ω

8DIP

Q0270R

700V

7.2Ω

8DIP

Q0370R

4.75Ω

FPS^TMis a trademark of Fairchild Semiconductor Corporation.

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

Application Diagram

AC

IN

DC

OUT

V_str

PWM

Drain

I_PK

V_CC

FB

GND

FSQ0x70RNA Rev. 1.01

Figure 1. Typical Flyback Application

(1)

Output Power Table

(2)

230V ±15%

85–265V

AC

Product

(3)

(4)

(3)

(4)

Adapter

14W

Open Frame

20W

Adapter

9W

Open Frame

13W

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

17W

24W

11W

16W

20W

27W

13W

19W

Notes:

1. The maximum output power can be limited by junction temperature.

2. 230 V_ACor 100/115 V_ACwith doubler.

3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink, at 50°C

ambient.

4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink, at 50°C

ambient.

Internal Block Diagram

V_str

5

V_CC

2

Drain

6,7,8

I_CH

8V/12V

V_CCgood

Internal

Bias

V_ref

V_BURL/V_BURH

V_CC

OSC

PWM

I_DELAY

I_FB

Normal

FB 3

S

R

Q

Gate

Driver

2.5R

Burst

R

Q

I_PK

4

LEB

V_SD

V_CC

V_ovp

1

GND

S

R

Q

V_CCgood

TSD

Soft-Start

FSQ0x70RNA Rev. 1.00

Figure 2. Internal Block Diagram

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

www.fairchildsemi.com

2

Pin Configuration

GND

V_CC

FB

D

8-DIP

D

I_PK

V_str

FSQ0x70RNA Rev. 1.00

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

Ground. SenseFET source terminal on primary side and internal control

ground.

1

GND

Power Supply. Positive supply voltage input. Although connected to an aux-

iliary transformer winding, current is supplied from pin 5 (V_str) via an internal

switch during start-up, see Figure 2. It is not until V_CCreaches the UVLO upper

threshold (12V) that the internal start-up switch opens and device power is

supplied via the auxiliary transformer winding.

2

3

V_CC

Feedback. The feedback voltage pin is the non-inverting input to the PWM

comparator. It has a 0.9mA current source connected internally while a capac-

itor and opto-coupler are typically connected externally. A feedback voltage of

6V triggers overload protection (OLP). There is a time delay while charging ex-

ternal capacitor C_FBfrom 3V to 6V using an internal 5µA current source. This

time delay prevents false triggering under transient conditions, but still allows

the protection mechanism to operate under true overload conditions.

FB

Peak Current Limit. This pin adjusts the peak current limit of the SenseFET.

The 0.9mA feedback current source is diverted to the parallel combination of

an internal 2.8kΩ resistor and any external resistor to GND on this pin. This

determines the peak current limit. If this pin is tied to V_CCor left floating, the

typical peak current limit is 0.8A (FSQ0170RNA), 0.9A (FSQ0270RNA), or

1.1A (FSQ0370RNA).

4

5

I_PK

Start-up. This pin connects to the rectified AC line voltage source. At start-up,

the internal switch supplies internal bias and charges an external storage ca-

pacitor placed between the V_CCpin and ground. Once the V_CCreaches 12V,

the internal switch is opened.

V_str

6

7

8

Drain

SenseFET drain. High-voltage power SenseFET drain connection.

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

3

Absolute Maximum Ratings

The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The

device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables

are not guaranteed at the absolute maximum ratings. T_A= 25°C, unless otherwise specified.

Symbol

V_DRAIN

V_STR

Characteristic

Value

Unit

V

Drain Pin Voltage

Vstr Pin Voltage

700

V

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

4

A

I_DM

Drain Current Pulsed⁽⁵⁾

8

A

12

50

A

mJ

V

E_AS

Single Pulsed Avalanche Energy⁽⁶⁾

140

230

V_CC

V_FB

P_D

Supply Voltage

20

Feedback Voltage Range

Total Power Dissipation

Operating Junction Temperature

Operating Ambient Temperature

Storage Temperature

-0.3 to V_CC

1.5

V

W

°C

T_J

Internally limited

-25 to +85

-55 to +150

T_A

T_STG

Thermal Impedance

T_A= 25°C, unless otherwise specified. All items are tested with the standards JESD 51-2 and 51-10 (DIP).

Symbol

θ_JA

Parameter

Value

80

Unit

°C/W

Junction-to-Ambient Thermal Resistance⁽⁷⁾

Junction-to-Case Thermal Resistance⁽⁸⁾

Junction-to-Top Thermal Resistance⁽⁹⁾

θ_JC

20

ψ_JT

35

Notes:

5. Non-repetitive rating: Pulse width is limited by maximum junction temperature.

6. L = 51mH, starting T_J= 25°C.

7. Free standing with no heatsink; without copper clad.

(Measurement Condition - Just before junction temperature T_Jenters into OTP.)

8. Measured on the DRAIN pin close to plastic interface.

9. Measured on the PKG top surface.

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

4

Electrical Characteristics

T_A= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

SenseFET Section⁽¹⁰⁾

V_DS= 700V, V_GS= 0V

50

I_DSS

Zero-Gate-Voltage Drain Current

μA

V_DS= 560V, V_GS= 0V,

T_C= 125°C

200

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

FSQ0170RNA

FSQ0270RNA

FSQ0370RNA

8.8

6.0

4.0

250

550

315

25

11

7.2

Drain-Source

On-State

R_DS(ON)

V_GS= 10V, I_D= 0.5A

W

Resistance⁽¹¹⁾

4.75

C_ISS

C_OSS

C_RSS

t_d(on)

t_r

Input Capacitance

Output Capacitance

V_GS= 0V, V_DS= 25V,

38

pF

f = 1MHz

47

10

Reverse Transfer

Capacitance

17

9

12

Turn-On Delay Time

Rise Time

20

11.2

4

15

34

V_DS= 350V, I_D= 1.0A

ns

30

t_d(off)

Turn-Off Delay Time

Fall Time

55

28.2

10

t_f

25

32

Control Section

f_OSC

Δf_OSC

D_MAX

D_MIN

V_START

V_STOP

I_FB

Switching Frequency

Switching Frequency Variation⁽¹⁰⁾

92

100

±5

60

0

108

±10

65

0

KHz

%

-25°C ≤ T_A≤ 85°C

Maximum Duty Cycle

Minimum Duty Cycle

Measured at 0.1 x V_DS

55

0

%

V_FB= GND

V_FB= 4V

11

7

12

8

13

9

UVLO Threshold Voltage

V

Feedback Source Current

Internal Soft-Start Time⁽¹⁰⁾

0.7

0.9

10

1.1

mA

ms

t_S/S

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

5

Electrical Characteristics (Continued)

T_A= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

Burst-Mode Section

V_BURH

0.5

0.3

0.6

0.4

0.7

0.5

300

V

V_BURL

Burst-Mode Voltage

T_J= 25°C

V_BUR(HYS)

100

200

mV

Protection Section

FSQ0170RNA

di/dt = 170mA/µs

di/dt = 200mA/µs

di/dt = 240mA/µs

0.70

0.79

0.97

0.80

0.90

1.10

500

140

6.0

0.90

1.01

1.23

I_LIM

Peak Current Limit

FSQ0270RNA

A

FSQ0370RNA

Current Limit Delay Time⁽¹⁰⁾

Thermal Shutdown Temperature⁽¹⁰⁾

Shutdown Feedback Voltage

Over-Voltage Protection

t_CLD

T_SD

ns

°C

V

125

5.5

18

V_SD

6.5

V_OVP

I_DELAY

t_LEB

19

V

Shutdown Delay Current

V_FB= 4V

3.5

200

5.0

μA

ns

Leading Edge Blanking Time⁽¹⁰⁾

Total Device Section

Operating Supply Current

(control part only)

I_OP

V_CC= 14V

1

3

5

mA

I_CH

Start-Up Charging Current

V_strSupply Voltage

V_CC= 0V

0.70

0.85

24

1.00

mA

V

V_STR

Notes:

10. These parameters, although guaranteed, are not 100% tested in production.

11. Pulse test: Pulse width ≤ 300µs, duty ≤ 2%.

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

6

Typical Performance Characteristics (Control Part)

These characteristic graphs are normalized at T_A= 25°C.

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100 125 150

-25

0

25

50

75

100 125 150

Temperature [°C]

Figure 4. Operating Frequency (f_OSC) vs. T_A

Figure 5. Over-Voltage Protection (V_OVP) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100 125 150

-25

0

25

50

75

100 125 150

Temperature [°C]

Figure 6. Maximum Duty Cycle (D_MAX) vs. T_A

Figure 7. Operating Supply Current (I_OP) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100 125 150

-25

0

25

50

75

100 125 150

Temperature [°C]

Figure 8. Start Threshold Voltage (V_START) vs. T_A

Figure 9. Stop Threshold Voltage (V_STOP) vs. T_A

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

7

Typical Performance Characteristics (Continued)

These characteristic graphs are normalized at T_A= 25°C.

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100 125 150

-25

0

25

50

75

100 125 150

Temperature [°C]

Figure 10. Feedback Source Current (I_FB) vs. T_A

Figure 11. Start-Up Charging Current (I_CH) vs. T_A

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-25

0

25

50

75

100 125 150

Temperature [°C]

Figure 12. Peak Current Limit (I_LIM) vs. T_A

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

www.fairchildsemi.com

8

circuit inhibits the PWM comparator for a short time

(t_LEB) after the Sense FET is turned on.

Functional Description

1. Startup: In previous generations of Fairchild Power

4. Protection Circuits: The FPS has several protective

functions, such as Overload Protection (OLP), Over-

Voltage Protection (OVP), Under-Voltage Lockout

(UVLO), and Thermal Shutdown (TSD). Because these

protection circuits are fully integrated in the IC without

external components, reliability is improved without

increasing cost. Once a fault condition occurs, switching

is terminated and the SenseFET remains off. This

causes V_CCto fall. When V_CCreaches the UVLO stop

Switches (FPS™), the V_strpin required an external

resistor to the DC input voltage line. In this generation,

the startup resistor is replaced by an internal high-

voltage current source and a switch that shuts off 10ms

after the supply voltage, V_CC, goes above 12V. The

source turns back on if V_CCdrops below 8V.

V_IN,dc

I_STR

voltage, V_STOP(typically 8V), the protection is reset and

the internal high-voltage current source charges the V_CC

capacitor via the V_strpin. When V_CCreaches the UVLO

start voltage, V_START(typically 12V), the FPS resumes

V_str

V

_cc<8V

V_cc

UVLO on

J-FET

its normal operation. In this manner, the auto-restart can

alternately enable and disable the switching of the power

SenseFET until the fault condition is eliminated.

I_CH

10ms after

V_cc≥12V

UVLO off

FSQ0x70RNA Rev. 1.00

4.1 Overload Protection (OLP): Overload is defined as

the load current exceeding a pre-set level due to an

unexpected event. In this situation, the protection circuit

should be activated to protect the SMPS. However, even

when the SMPS is operating normally, the OLP circuit

can be activated during the load transition. To avoid this

undesired operation, the OLP circuit is designed to be

activated after a specified time to determine whether it is

a transient situation or a true overload situation. In

conjunction with the I_PKcurrent limit pin (if used), the

Figure 13. High-Voltage Current Source

2. Feedback Control: The 700V FPS series employs

current-mode control, as shown in Figure 14. An opto-

coupler (such as the H11A817A) and shunt regulator

(such as the KA431) are typically used to implement the

feedback network. Comparing the feedback voltage with

the voltage across the R_senseresistor of SenseFET, plus

an offset voltage, makes it possible to control the

switching duty cycle. When the shunt regulator reference

pin voltage exceeds the internal reference voltage of

2.5V, the opto-coupler LED current increases, the

feedback voltage V_FBis pulled down and thereby

current mode feedback path limits the current in the

SenseFET when the maximum PWM duty cycle is

attained. If the output consumes more than this

maximum power, the output voltage (V_O) decreases

below nominal voltage. This reduces the current through

the opto-coupler LED, which also reduces the opto-

coupler transistor current, thus increasing the feedback

voltage (V_FB). If V_FBexceeds 3V, the feedback input

reduces the duty cycle. This typically happens when the

input voltage increases or the output load decreases.

V_CC

5μA

diode is blocked and the 5µA current source (I_DELAY

)

900μA

starts to slowly charge C_FBup to V_CC. In this condition,

V_FBincreases until it reaches 6V, when the switching

FB

V_O

3

OSC

2.5R

D1

D2

+

C_FB

operation is terminated, as shown in Figure 15. The

shutdown delay time is the time required to charge C_FB

V_FB

V_FB,in

Gate

driver

R

-

from 3V to 6V with 5µA current source.

431

V_FB

FSQ0x70RNA Rev.00

Overload Protection

OLP

6V

V_SD

FSQ0x70RNA Rev. 1.00

Figure 14. Pulse Width Modulation Circuit

3V

3. Leading Edge Blanking (LEB): When the internal

SenseFET is turned on, the primary-side capacitance

and secondary-side rectifier diode reverse recovery

t₁₂= C_FB×(V(t₂)-V(t₁)) / I_DELAY

typically cause

SenseFET. Excessive voltage across the R_senseresistor

a high-current spike through the

t₁

t₂

t

V (t₂) −V (t₁)

I_DELAY

t₁₂= C_FB

;

I_DELAY= 5μ A,V (t₁) = 3V,V (t₂) = 6V

leads to incorrect feedback operation in the current-

mode PWM control. To counter this effect, the FPS

employs a Leading Edge Blanking (LEB) circuit. This

Figure 15. Overload Protection (OLP)

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

9

4.2 Thermal Shutdown (TSD): The SenseFET and the

control IC are integrated, making it easier for the control

IC to detect the temperature of the SenseFET. When the

temperature exceeds approximately 140°C, thermal

shutdown is activated.

V_BURH(typically 600mV). Switching continues until the

feedback voltage drops below V_BURL(typically 400mV).

At this point, switching stops and the output voltage

starts to drop at a rate dependent on the standby current

load. This causes the feedback voltage to rise. Once it

passes V_BURH

, switching resumes. The feedback

4.3 Over-Voltage Protection (OVP): In the event of a

malfunction in the secondary-side feedback circuit, or an

open feedback loop caused by a soldering defect, the

current through the opto-coupler transistor becomes

almost zero (see Figure 14). V_FBclimbs up in a similar

voltage then falls and the process is repeated. Burst-

mode operation alternately enables and disables

switching of the SenseFET and reduces switching loss in

standby mode.

manner to the overload situation, forcing the preset

maximum current to be supplied to the SMPS until the

overload protection is activated. Because excess energy

is provided to the output, the output voltage may exceed

the rated voltage before the overload protection is

activated, resulting in the breakdown of the devices in

the secondary side. To prevent this situation, an Over-

Voltage Protection (OVP) circuit is employed. In general,

V_CCis proportional to the output voltage and the FPS

Burst Operation

Normal

Operation

V_FB

V_BURH

V_BURL

Current

Waveform

Switching

OFF

FSQ0x70RNA Rev.00

Switching OFF

uses V_CCinstead of directly monitoring the output

voltage. If V_CCexceeds 19V, the OVP circuit is activated,

resulting in termination of the switching operation. To

avoid undesired activation of OVP during normal

operation, V_CCshould be designed to be below 19V.

Figure 17. Burst Operation Function

7. Adjusting Peak Current Limit: As shown in Figure

18, a combined 2.8kΩ internal resistance is connected to

the non-inverting lead on the PWM comparator. An

external resistance of Rx on the current limit pin forms a

parallel resistance with the 2.8kΩ when the internal

diodes are biased by the main current source of 900µA.

5. Soft-Start: The FPS has an internal soft-start circuit

that slowly increases the SenseFET current after start-

up, as shown in Figure 16. The typical soft-start time is

10ms, where progressive increments of the SenseFET

current are allowed during the start-up phase. The pulse

width to the power switching device is progressively

increased to establish the correct working conditions for

transformers, inductors, and capacitors. The voltage on

the output capacitors is progressively increased to

smoothly establish the required output voltage. This also

helps prevent transformer saturation and reduces the

stress on the secondary diode during startup.

V_CC

PWM

Comparator

5μA

900μA

I_DELAY

I_FB

V_FB

2kΩ

3

4

0.8kΩ

#6,7,8

5V

I_PK

SenseFET

Current

Sense

DRAIN

Rx

FSQ0x70RNA Rev. 1.00

#1

GND

Figure 18. Peak Current Limit Adjustment

I_LIM

R_sense

For example, FSQ0270RNA has a typical SenseFET

peak current limit (I_LIM) of 0.9A. I_LIMcan be adjusted to

FSQ0x70RNA Rev. 1.00

0.6A by inserting Rx between the I_PKpin and the ground.

The value of the Rx can be estimated by the following

equations:

Figure 16. Soft-Start Function

0.9A: 0.6A = 2.8kΩ : XkΩ,

6. Burst Operation: To minimize power dissipation in

standby mode, the FPS enters burst-mode operation.

Feedback voltage decreases as the load decreases, as

shown in Figure 17, and the device automatically enters

burst-mode when the feedback voltage drops below

X = Rx || 2.8kΩ

where X represents the resistance of the parallel network.

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

10

Application Information

Methods of Reducing Audible Noise

Switching-mode power converters have electronic and

magnetic components, which generate audible noise

when the operating frequency is in the range of

20~20,000Hz. Even though they operate above 20KHz,

they can make noise, depending on the load condition.

The following sections discuss methods to reduce noise.

Glue or Varnish

The most common method of reducing noise involves

using glue or varnish to tighten magnetic components.

The motion of core, bobbin, and coil and the chattering

or magnetostriction of core can cause the transformer to

produce audible noise. The use of rigid glue and varnish

helps reduce the transformer noise. Glue or varnish can

also can crack the core because sudden changes in the

ambient temperature cause the core and the glue to

expand or shrink in a different ratio.

Figure 19. Equal Loudness Curves

Ceramic Capacitor

Using a film capacitor instead of a ceramic capacitor as a

snubber capacitor is another noise reduction solution.

Some dielectric materials show a piezoelectric effect,

depending on the electric field intensity. Hence, a

snubber capacitor becomes one of the most significant

sources of audible noise. Another possibility is to use a

Zener clamp circuit instead of an RCD snubber for

higher efficiency as well as lower audible noise.

Adjusting Sound Frequency

Moving the fundamental frequency of noise out of the

2~4kHz range is the third method. Generally, humans

are more sensitive to noise in the range of 2~4kHz.

When the fundamental frequency of noise is located in

this range, the noise sounds louder although the noise

intensity level is identical (see Figure 19).

Figure 20. Typical Feedback Network of FPS

Other Reference Materials

AN-4134: Design Guidelines for Off-line Forward

Converters Using Fairchild Power Switch (FPS™)

When the FPS acts in burst mode and the burst

operation is suspected to be a source of noise, this

method may be helpful. If the frequency of burst mode

operation lies in the range of 2~4kHz, adjusting the

feedback loop can shift the burst operation frequency. To

AN-4137: Design Guidelines for Off-line Flyback

Converters Using Fairchild Power Switch (FPS™)

AN-4140: Transformer Design Consideration for Off-line

Flyback Converters using Fairchild Power Switch (FPS™)

reduce the burst operation frequency, increase

a

feedback gain capacitor (C_F), opto-coupler supply

resistor (R_D); and feedback capacitor (C_B), and decrease

a feedback gain resistor (R_F), as shown in Figure 20.

AN-4141: Troubleshooting and Design Tips for Fairchild

Power Switch (FPS™) Flyback Applications

AN-4147: Design Guidelines for RCD Snubber of

Flyback

AN-4148: Audible Noise Reduction Techniques for

FPS™ Applications

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

11

Typical Application Circuit

Application

Output power

15W

Input Voltage

Output Voltage (Max. Current)

PC Auxiliary Power Supply

(Using FSQ0270RNA)

Universal input

5V (3A)

(85-265 V_AC

)

Features

High efficiency (> 78% at 115 V_ACand 230 V_ACinput)

Low standby mode power consumption (< 0.8W at 230 V_ACinput and 0.5W load)

Enhanced system reliability through various protection functions

Internal soft-start (10ms)

Line UVLO function can be achieved using external component

Key Design Notes

The delay time for overload protection is designed to be about 30ms with C8 of 47nF. If faster/slower triggering of

OLP is required, C8 can be changed to a smaller/larger value (e.g. 100nF for about 60ms).

ZP1, DL1, RL1, RL2, RL3, RL4, RL5, RL7, QL1, QL2, and CL9 build a Line Under-Voltage Lockout block (UVLO).

The Zener voltage of ZP1 determines the input voltage that makes FPS turn on. RL5 and DL1 provide a reference

voltage from V_CC. If the input voltage divided by RL1, RL2, and RL4 is lower than the Zener voltage of DL1, QL1 and

QL2 turn on and pull down V_FBto ground.

An evaluation board and corresponding test report can be provided.

1. Schematic

C1

2.2nF

AC250V

RS1

9

CS1

1.5nF

L1

330μH

L2

1μH

ZDS1

P6KE180A

T1

CON2

1

EE2229

1

6,7

D1

SB540

2

D2

D3

C10

1nF

250V

ZP1

Output

R3

R4

J4

0

R2

R6

2.4 1W

3

9, 10

1N4007 1N4007

CON1

560

100

4.7k

1

2

3

C2

22μF

400V

C3

22μF

400V

R14

30

1N4762

1

R5

1.25k

1%

U1A

FOD817A

Input

R8

C5

470μF

10V

D4

D5

C4

1000μF 1000μF

16V

C9

open

DS1

1N4007

1N4007 1N4007

2

3

L3

0

J1

R9

10k

C6

47nF

FB

R11

1.2k

1%

4

U2

TL431A

RL1 1M

1

U3

D6

1N4007 2

R10

2

FSQ0270RNA

RL5

30k

DL1

1N5233B

8

1

7

6

3

5

4

5

RL2

1M

QL1

KSP2907A

J3

open

C7

47μF

25V

ZR1

80

2

R12

RL4

120k

open

J2

0

RL3

1k

4

ZD1

1N4745

CL9

10μF

50V

ZD2 C8

open

RL7

40k

3

47nF

U1B

QL2

R13

open

FSQ0x70RNA Rev. 1.12

KSP2222A FOD817A

Figure 21. Demo Circuit

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

www.fairchildsemi.com

12

2. Transformer

EE2229

1

9, 10

6, 7

2

3

4

5

Np/2

N_5V

N_a

FSQ0x70RNA Rev. 1.00

Figure 22. Transformer Schematic Diagram

3. Winding Specification

Pin (S → F)

3 → 2

Insulation: Polyester Tape t = 0.025mm, 1 Layers

N_a4 → 5

Insulation: Polyester Tape t = 0.025mm, 2 Layers

N_5V6, 7 → 9, 10

Insulation: Polyester Tape t = 0.025mm, 2 Layers

N_p/2 2 → 1

Wire

Turns

Winding Method

N_p/2

0.3ϕ × 1

72

22

8

Solenoid winding

0.25ϕ × 2

0.65ϕ × 2

0.3ϕ × 1

Solenoid winding

72

Insulation: Polyester Tape t = 0.025mm, 2 Layers

4. Electrical Characteristics

Specification

1.20mH ± 5%

< 30µH Max

Remark

100kHz, 1V

Inductance

Leakage

1–3

Short all other pins

5. Core & Bobbin

Core: EE2229 (Material: PL-7, Ae = 35.7 mm²)

Bobbin: BE2229

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

13

6. Demo Circuit Part List

Part Number

Value

47nF

Quantity

Description (Manufacturer)

Ceramic Capacitor

C6, C8

2

1

2

1

4

1

2

1

6

1

C1

2.2nF (1KV)

1nF (200V)

1.5nF (50V)

22µF (400V)

1000µF (16V)

470µF (10V)

47µF (25V)

10µF (50V)

330µH

AC Ceramic Capacitor(X1 & Y1)

C10

Mylar Capacitor

CS1

Ceramic Capacitor

C2, C3

Low Impedance Electrolytic Capacitor KMX series

C4, C9

Low ESR Electrolytic Capacitor NXC series

C5

Low ESR Electrolytic Capacitor NXC series

C7

General Electrolytic Capacitor

CL9

General Electrolytic Capacitor

L1

Inductor

L2

1µH

Inductor

R6

2.4 (1W)

0

Fusible Resistor

J1, J2, J4, L3

Jumper

R2

4.7kΩ

Resistor

R3

560Ω

Resistor

R4

100Ω

Resistor

R5

1.25kΩ

1.2kΩ

Resistor

R11

Resistor

R9

10kΩ

Resistor

R10

2Ω

Resistor

R14

30Ω

Resistor

RL3

1kΩ

Resistor

RL1, RL2

1MΩ

Resistor

RL4

120kΩ

Resistor

RL5

30kΩ

Resistor

RL7

40kΩ

Resistor

RS1

9Ω

Resistor

ZR1

80Ω

Resistor

U1

FOD817A

TL431

IC (Fairchild Semiconductor)

Diode (Fairchild Semiconductor)

Schottky Diode (Fairchild Semiconductor)

Zener Diode (Fairchild Semiconductor)

TVS (Fairchild Semiconductor)

U2

U3

FSQ0270RNA

2N2907

2N2222

1N4007

SB540

QL1

QL2

D2, D3, D4, D5, D6, DS1

D1

ZD1

DL1

ZP1

ZDS1

1N4745

1N5233

82V (1W)

P6KE180A

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

14

7. Layout

Figure 23. Top Image of PCB

Figure 24. Bottom Image of PCB

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

15

Package Dimensions

8-DIP

Dimensions are in millimeters unless otherwise noted.

6.40 0.20

0.252 0.008

#1

#4

#8

#5

3.30 0.30

0.130 0.012

5.08

0.200

MAX

7.62

3.40 0.20

0.134 0.008

0.300

0.33

0.013

MIN

September 1999, Rev B

8dip_dim.pdf

Figure 25. 8-Lead Dual In-Line Package (DIP)

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

www.fairchildsemi.com

16

FAIRCHILD SEMICONDUCTOR TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

ACEx™

FACT Quiet Series™

GlobalOptoisolator™

GTO™

OCX™

SILENT SWITCHER^®

SMART START™

SPM™

UniFET™

VCX™

Wire™

ActiveArray™

Bottomless™

Build it Now™

CoolFET™

CROSSVOLT™

DOME™

OCXPro™

OPTOLOGIC^®

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerEdge™

PowerSaver™

PowerTrench^®

QFET^®

HiSeC™

Stealth™

I²C™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TCM™

TinyBoost™

TinyBuck™

i-Lo™

ImpliedDisconnect™

IntelliMAX™

ISOPLANAR™

LittleFET™

MICROCOUPLER™

MicroFET™

MicroPak™

EcoSPARK™

E²CMOS™

EnSigna™

FACT^®

FAST^®

FASTr™

QS™

QT Optoelectronics™ TinyPWM™

FPS™

FRFET™

MICROWIRE™

MSX™

MSXPro™

Quiet Series™

RapidConfigure™

RapidConnect™

µSerDes™

TinyPower™

TinyLogic^®

TINYOPTO™

TruTranslation™

UHC^®

Across the board. Around the world.™

The Power Franchise^®

ScalarPump™

Programmable Active Droop™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER

ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain

life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably

expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Advance Information

Product Status

Definition

Formative or In Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. I22

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1

17

型号:	FSQ0270RNA
Brand Name：	ON Semiconductor
是否无铅：	不含铅
生命周期：	Active
包装说明：	DIP, DIP8,.3
制造商包装代码：	626-05
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8541.29.00.95
Factory Lead Time：	1 week
风险等级：	2
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	18 V
最小输入电压：	9 V
标称输入电压：	14 V
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e3
长度：	9.2 mm
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-25 °C
最大输出电流：	1.01 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	5.08 mm
子类别：	Switching Regulator or Controllers
表面贴装：	NO
切换器配置：	SINGLE
最大切换频率：	108 kHz
温度等级：	COMMERCIAL EXTENDED
端子面层：	Tin (Sn)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

电子百科

产品导航

产品型号FSQ0270RNA的概述

产品型号FSQ0270RNA的Datasheet PDF文件预览

FSQ0270RNA相关产品

FSQ0270RNA相关文章

IC37:专业IC行业平台