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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • GAL16V8D-25LPN
  • 数量-
  • 厂家-
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  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • GAL16V8D-25LPNI图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • GAL16V8D-25LPNI 现货库存
  • 数量3000 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
  • QQ:2881498351QQ:2881498351 复制
  • 0755-22968581 QQ:2881498351
  • GAL16V8D-25LPN图
  • 集好芯城

     该会员已使用本站13年以上
  • GAL16V8D-25LPN 现货库存
  • 数量15250 
  • 厂家Lattice(莱迪斯) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • GAL16V8D-25LPN图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GAL16V8D-25LPN 现货库存
  • 数量18428 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP20 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • GAL16V8D-25LPN图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • GAL16V8D-25LPN 现货库存
  • 数量3685 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • GAL16V8D-25LPN图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN 现货库存
  • 数量5000 
  • 厂家GAL 
  • 封装DIP 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • GAL16V8D-25LPN图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • GAL16V8D-25LPN 现货库存
  • 数量8000 
  • 厂家Lattice(莱迪斯) 
  • 封装STOCK 
  • 批号22+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • GAL16V8D-25LPN图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • GAL16V8D-25LPN 现货库存
  • 数量3783 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • GAL16V8D-25LPN图
  • 北京罗彻斯特电子科技有限公司

     该会员已使用本站18年以上
  • GAL16V8D-25LPN 现货库存
  • 数量10402 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号1212+ 
  • ▊真实原装现货▊可出售样品及配套服务
  • QQ:674627925QQ:674627925 复制
    QQ:372787046QQ:372787046 复制
  • 13261827936军工芯片优势 QQ:674627925QQ:372787046
  • GAL16V8D-25LPN图
  • 深圳市欧昇科技有限公司

     该会员已使用本站2年以上
  • GAL16V8D-25LPN 现货库存
  • 数量198 
  • 厂家LATTICE 
  • 封装DIP-20L 
  • 批号10+ 
  • 只做原装现货实单可谈
  • QQ:2885528234QQ:2885528234 复制
  • -0755-83220848 QQ:2885528234
  • GAL16V8D-25LPN图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN 热卖库存
  • 数量15000 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP 
  • 批号23+ 
  • 全新原装,现货热卖。
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • GAL16V8D-25LPN图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • GAL16V8D-25LPN
  • 数量5300 
  • 厂家Lattice(莱迪斯) 
  • 封装20-DIP(0.300,7.62mm) 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • GAL16V8D-25LPN图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GAL16V8D-25LPN
  • 数量85000 
  • 厂家LATTICE/莱迪斯 
  • 封装19 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • GAL16V8D-25LPN图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GAL16V8D-25LPN
  • 数量36000 
  • 厂家1000 
  • 封装能供更多数量 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • GAL16V8D-25LPN图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • GAL16V8D-25LPN
  • 数量17560 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号24+ 
  • 原装原厂 现货现卖
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • GAL16V8D-25LPN图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • GAL16V8D-25LPN
  • 数量5000 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号2019+ 
  • 原装进口现货假一赔十
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • GAL16V8D-25LPN图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量6000 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号23+ 
  • 全新原装现货,欢迎询购!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • GAL16V8D-25LPN图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • GAL16V8D-25LPN
  • 数量8800 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • GAL16V8D-25LPNI图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • GAL16V8D-25LPNI
  • 数量5000 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
  • QQ:2881498351QQ:2881498351 复制
  • 0755-22968581 QQ:2881498351
  • GAL16V8D-25LPN图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量5500 
  • 厂家LATTIC 
  • 封装DIP20 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
  • QQ:1437347957QQ:1437347957 复制
    QQ:1205045963QQ:1205045963 复制
  • 0755-82343089 QQ:1437347957QQ:1205045963
  • GAL16V8D-25LPN IC图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • GAL16V8D-25LPN IC
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • GAL16V8D-25LPN图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • GAL16V8D-25LPN
  • 数量15280 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号23+ 
  • 原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • GAL16V8D-25LPN图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • GAL16V8D-25LPN
  • 数量7800 
  • 厂家LATTE/莱迪斯 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • GAL16V8D-25LPN图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • GAL16V8D-25LPN
  • 数量28000 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP20 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • GAL16V8D-25LPN图
  • 集好芯城

     该会员已使用本站13年以上
  • GAL16V8D-25LPN
  • 数量17560 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • GAL16V8D-25LPN图
  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量
  • 厂家860 
  • 封装DIP20 
  • 批号 
  • 正品原装 支持最低价
  • QQ:864187665QQ:864187665 复制
    QQ:1807086236QQ:1807086236 复制
  • 755-82533156 QQ:864187665QQ:1807086236
  • GAL16V8D-25LPN图
  • 深圳市雅维特电子有限公司

     该会员已使用本站15年以上
  • GAL16V8D-25LPN
  • 数量8000 
  • 厂家LATTICE 
  • 封装深圳原装现货0755-83975781 
  • 批号A/N 
  • QQ:767621813QQ:767621813 复制
    QQ:1152937841QQ:1152937841 复制
  • 0755-83975781 QQ:767621813QQ:1152937841
  • GAL16V8D-25LPN图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • GAL16V8D-25LPN
  • 数量15372 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • GAL16V8D-25LPN图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量30000 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP20 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • GAL16V8D-25LPN图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • GAL16V8D-25LPN
  • 数量10548 
  • 厂家LATTICE莱迪思 
  • 封装DIP20 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • GAL16V8D-25LPN图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GAL16V8D-25LPN
  • 数量33265 
  • 厂家LATTICE 
  • 封装DIP 
  • 批号2023+ 
  • 绝对原装正品现货,全新深圳原装进口现货
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • GAL16V8D-25LPN图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GAL16V8D-25LPN
  • 数量18428 
  • 厂家LATTICE/莱迪斯 
  • 封装DIP20 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • GAL16V8D-25LPN图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量8460 
  • 厂家LT代理 
  • 封装DIP20 
  • 批号NEW 
  • 实力全新原装热卖
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • GAL16V8D-25LPN图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • GAL16V8D-25LPN
  • 数量12245 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • GAL16V8D-25LPN图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • GAL16V8D-25LPN
  • 数量865000 
  • 厂家LATTICE/莱迪斯 
  • 封装19 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • GAL16V8D-25LPN图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • GAL16V8D-25LPN
  • 数量5000 
  • 厂家
  • 封装LATTICE 
  • 批号16+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62106431 QQ:857273081QQ:1594462451
  • GAL16V8D-25LPN图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • GAL16V8D-25LPN
  • 数量28620 
  • 厂家Lattice 
  • 封装20-DIP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • GAL16V8D-25LPN图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GAL16V8D-25LPN
  • 数量12800 
  • 厂家Lattice 
  • 封装DIP 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • GAL16V8D-25LPN图
  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • GAL16V8D-25LPN
  • 数量3850 
  • 厂家Lattice(莱迪斯) 
  • 封装20-DIP(0.300,7.62mm) 
  • 批号23+ 
  • ▉原装现货▉可含税可订货
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • GAL16V8D-25LPN图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • GAL16V8D-25LPN
  • 数量2800 
  • 厂家LATTICE 
  • 封装DIP20 
  • 批号20+ 
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  • GAL16V8D-25LPN
  • 数量38200 
  • 厂家Lattice(莱迪斯) 
  • 封装20-DIP(0.300,7.62mm) 
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产品型号GAL16V8D-25LPN的概述

芯片GAL16V8D-25LPN的概述 GAL16V8D-25LPN是一款由Lattice Semiconductor Corporation(莱迪思半导体公司)所生产的可编程逻辑器件,属于GAL(General Array Logic)系列。该芯片是一种高性能的可编程逻辑器件,能够实现复杂的逻辑功能,广泛应用于数字电路设计中。它的主要特点是可重编程性、高速度和低功耗,因而在许多现代电子产品中得到了广泛应用。 GAL16V8D-25LPN的代码中,"16"表示它有16个输入;"V8"说明它具有8个可编程输出;而"25"则指其工作频率为25ns。该芯片的可编程性使得设计者可以根据具体需求灵活地定义其逻辑功能,从而提高设计效率。此外,GAL16V8D-25LPN还支持多种编程模式,适应不同的设计需求。 芯片GAL16V8D-25LPN的详细参数 以下是GAL16V8D-25LPN主要参数的...

产品型号GAL16V8D-25LPN的Datasheet PDF文件预览

GAL16V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
I/CLK  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 3.5 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
CLK  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
8
8
OLMC  
— 3.0 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
I
I
I
I
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc on Low Power Device  
— 45mA Typ Icc on Quarter Power Device  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
8
8
8
8
8
8
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
— Also Emulates 20-pin PAL® Devices with Full  
Function/Fuse Map/Parametric Compatibility  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I/O/Q  
I/OE  
OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
• LEAD-FREE PACKAGE OPTIONS  
Pin Configuration  
PLCC  
Description  
I
I
I/CLK Vcc I/O/Q  
2
20  
DIP  
18  
16  
I/O/Q  
4
6
I
The GAL16V8, at 3.5 ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
I/O/Q  
I/O/Q  
I
1
20  
Vcc  
I/CLK  
GAL16V8  
Top View  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I/O/Q  
I/O/Q  
I
I
I
GAL  
14  
I
8
9
I
11  
13  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL16V8 are the PAL architectures listed  
in the table of the macrocell description section. GAL16V8 devices  
are capable of emulating any of these PAL architectures with full  
function/fuse map/parametric compatibility.  
16V8  
GND I/OE I/O/Q I/O/Q  
5
I
I
SOIC  
15  
I/CLK  
I
1
20  
Vcc  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I
GAL  
16V8  
Top  
5
I
I
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
15  
11  
10  
11  
GND  
I
I
View  
I
10  
GND  
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
1
16v8_11  
Specifications GAL16V8  
GAL16V8 Ordering Information  
Conventional Packaging  
Commercial Grade Specifications  
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)  
Ordering #  
Package  
3.5  
5
2.5  
3
3.0  
4
115  
GAL16V8D-3LJ1  
20-Lead PLCC  
GAL16V8C-5LP1  
GAL16V8D-5LJ  
GAL16V8D-7LP  
GAL16V8C-7LP1  
GAL16V8D-7LJ  
GAL16V8D-7LS1  
GAL16V8D-10QP  
GAL16V8D-10QJ  
20-Pin Plastic DIP  
20-Lead PLCC  
115  
115  
7.5  
7
5
20-Pin Plastic DIP  
20-Pin Plastic DIP  
20-Lead PLCC  
115  
115  
115  
115  
55  
20-Pin SOIC  
10  
10  
7
20-Pin Plastic DIP  
20-Lead PLCC  
20-Pin Plastic DIP  
20-Lead PLCC  
55  
115  
115  
115  
55  
GAL16V8D-10LP  
GAL16V8D-10LJ  
GAL16V8D-10LS1  
GAL16V8D-15QP  
GAL16V8D-15QJ  
GAL16V8D-15LP  
20-Pin SOIC  
15  
25  
12  
15  
10  
12  
20-Pin Plastic DIP  
20-Lead PLCC  
20-Pin Plastic DIP  
55  
90  
90  
GAL16V8D-15LJ  
GAL16V8D-15LS1  
GAL16V8D-25QP  
GAL16V8D-25QJ  
GAL16V8D-25LP  
20-Lead PLCC  
20-Pin SOIC  
90  
55  
20-Pin Plastic DIP  
20-Lead PLCC  
20-Pin Plastic DIP  
20-Lead PLCC  
55  
90  
90  
GAL16V8D-25LJ  
GAL16V8D-25LS1  
90  
20-Pin SOIC  
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.  
Industrial Grade Specifications  
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)  
Ordering #  
Package  
7.5  
10  
15  
20  
25  
7
5
130  
130  
130  
130  
130  
130  
65  
20-Pin Plastic DIP  
GAL16V8D-7LPI  
20-Lead PLCC  
GAL16V8D-7LJI  
GAL16V8D-10LPI  
GAL16V8D-10LJI  
GAL16V8D-15LPI  
GAL16V8D-15LJI  
GAL16V8D-20QPI  
GAL16V8D-20QJI  
GAL16V8D-25QPI  
GAL16V8D-25QJI  
GAL16V8D-25LPI  
GAL16V8D-25LJI  
10  
12  
13  
15  
7
20-Pin Plastic DIP  
20-Lead PLCC  
10  
11  
12  
20-Pin Plastic DIP  
20-Lead PLCC  
20-Pin Plastic DIP  
20-Lead PLCC  
65  
65  
20-Pin Plastic DIP  
20-Lead PLCC  
65  
130  
130  
20-Pin Plastic DIP  
20-Lead PLCC  
2
Specifications GAL16V8  
Lead-Free Packaging  
Commercial Grade Specifications  
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)  
Ordering #  
GAL16V8D-3LJN1  
Package  
3.5  
2.5  
3.0  
115  
115  
Lead-Free 20-Lead PLCC  
5
3
7
4
5
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
GAL16V8D-5LJN  
GAL16V8D-7LPN  
GAL16V8D-7LJN  
GAL16V8D-10QPN  
GAL16V8D-10QJN  
7.5  
115  
115  
55  
10  
15  
25  
10  
12  
15  
7
55  
115  
115  
55  
GAL16V8D-10LPN  
GAL16V8D-10LJN  
GAL16V8D-15QPN  
GAL16V8D-15QJN  
GAL16V8D-15LPN  
10  
12  
55  
90  
90  
GAL16V8D-15LJN  
GAL16V8D-25QPN  
GAL16V8D-25QJN  
GAL16V8D-25LPN  
55  
55  
90  
90  
GAL16V8D-25LJN  
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.  
Industrial Grade Specifications  
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)  
Ordering #  
GAL16V8D-7LJNI  
Package  
7.5  
7
5
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
Lead-Free 20-Lead PLCC  
Lead-Free 20-Pin Plastic DIP  
130  
130  
130  
130  
130  
130  
65  
GAL16V8D-7LPNI  
GAL16V8D-10LJNI  
GAL16V8D-10LPNI  
10  
10  
7
15  
20  
25  
12  
13  
15  
10  
11  
12  
GAL16V8D-15LJNI  
GAL16V8D-15LPNI  
GAL16V8D-20QJNI  
GAL16V8D-20QPNI  
GAL16V8D-25QJNI  
GAL16V8D-25QPNI  
GAL16V8D-25LJNI  
GAL16V8D-25LPNI  
65  
65  
65  
130  
130  
Part Number Description  
_
XXXXXXXX XX X XX X  
GAL16V8D Device Name  
Grade  
Blank = Commercial  
I = Industrial  
Speed (ns)  
L = Low Power  
Q = Quarter Power  
Power  
Package P = Plastic DIP  
PN = Lead-free Plastic DIP  
J = PLCC  
JN = Lead-free PLCC  
S = SOIC  
3
Specifications GAL16V8  
Output Logic Macrocell (OLMC)  
The following discussion pertains to configuring the output logic  
macrocell. It should be noted that actual implementation is accom-  
plished by development software/hardware and is completely trans-  
parent to the user.  
PAL Architectures  
Emulated by GAL16V8  
GAL16V8  
Global OLMC Mode  
16R8  
16R6  
16R4  
16RP8  
16RP6  
16RP4  
Registered  
Registered  
Registered  
Registered  
Registered  
Registered  
There are three global OLMC configuration modes possible:  
simple, complex, and registered. Details of each of these modes  
are illustrated in the following pages. Two global bits, SYN and  
AC0, control the mode configuration for all macrocells. The XOR  
bit of each macrocell controls the polarity of the output in any of the  
three modes, while the AC1 bit of each of the macrocells controls  
the input/output configuration. These two global and 16 individ-  
ual architecture bits define all possible configurations in a GAL16V8  
. The information given on these architecture bits is only to give  
a better understanding of the device. Compiler software will trans-  
parently set these architecture bits from the pin definitions, so the  
user should not need to directly manipulate these architecture bits.  
16L8  
16H8  
16P8  
Complex  
Complex  
Complex  
10L8  
12L6  
14L4  
16L2  
10H8  
12H6  
14H4  
16H2  
10P8  
12P6  
14P4  
16P2  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
Simple  
The following is a list of the PAL architectures that the GAL16V8  
can emulate. It also shows the OLMC mode under which the  
GAL16V8 emulates the PAL architecture.  
Compiler Support for OLMC  
Software compilers support the three different global OLMC modes as clock and output enable, respectively. These pins cannot be con-  
as different device types. These device types are listed in the table figured as dedicated inputs in the registered mode.  
below. Most compilers have the ability to automatically select the  
device type, generally based on the register usage and output In complex mode pin 1 and pin 11 become dedicated inputs and  
enable (OE) usage. Register usage on the device forces the soft- use the feedback paths of pin 19 and pin 12 respectively. Because  
ware to choose the registered mode. All combinatorial outputs with of this feedback path usage, pin 19 and pin 12 do not have the  
OE controlled by the product term will force the software to choose feedback option in this mode.  
the complex mode. The software will choose the simple mode only  
when all outputs are dedicated combinatorial without OE control. In simple mode all feedback paths of the output pins are routed  
The different device types listed in the table can be used to override via the adjacent pins. In doing so, the two inner most pins ( pins  
the automatic device selection by the software. For further details, 15 and 16) will not have the feedback option as these pins are  
refer to the compiler software manuals.  
always configured as dedicated combinatorial output.  
When using compiler software to configure the device, the user  
must pay special attention to the following restrictions in each mode.  
In registered mode pin 1 and pin 11 are permanently configured  
Registered  
Complex  
Simple  
Auto Mode Select  
ABEL  
P16V8R  
G16V8MS  
GAL16V8_R  
"Registered"1  
P16V8R2  
P16V8C  
G16V8MA  
GAL16V8_C7  
"Complex"1  
P16V8C2  
P16V8AS  
G16V8AS  
GAL16V8_C8  
"Simple"1  
P16V8C2  
G16V8AS3  
P16V8  
G16V8  
CUPL  
LOG/iC  
GAL16V8  
GAL16V8A  
P16V8A  
G16V8  
OrCAD-PLD  
PLDesigner  
TANGO-PLD  
G16V8R  
G16V8C  
1) Used with Configuration keyword.  
2) Prior to Version 2.0 support.  
3) Supported on Version 1.20 or later.  
4
Specifications GAL16V8  
Registered Mode  
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-  
registered outputs or as I/O functions. sets of the I/O function.  
Architecture configurations available in this mode are similar to the Registered outputs have eight product terms per output. I/O's have  
common 16R8 and 16RP4 devices with various permutations of seven product terms per output.  
polarity, I/O and register placement.  
The JEDEC fuse numbers, including the User Electronic Signature  
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown  
control pins. Any macrocell can be configured as registered or I/ on the logic diagram on the following page.  
O. Up to eight registers or up to eight I/O's are possible in this mode.  
CLK  
Registered Configuration for Registered Mode  
- SYN=0.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=0 defines this output configuration.  
D
Q
Q
- Pin 1 controls common CLK for the registered outputs.  
XOR  
- Pin 11 controls common OE for the registered outputs.  
- Pin 1 & Pin 11 are permanently configured as CLK &  
OE for registered output configuration.  
OE  
Combinatorial Configuration for Registered Mode  
- SYN=0.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1 defines this output configuration.  
- Pin 1 & Pin 11 are permanently configured as CLK &  
XOR  
OE for registered output configuration.  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
5
Specifications GAL16V8  
Registered Mode Logic Diagram  
DIP & PLCC Package Pinouts  
1
2128  
28  
PTD  
0
4
8
12  
16  
20  
24  
0000  
0224  
OLMC  
19  
18  
17  
16  
15  
14  
13  
XOR-2048  
AC1-2120  
2
3
4
5
6
7
8
9
0256  
0480  
OLMC  
XOR-2049  
AC1-2121  
0512  
0736  
OLMC  
XOR-2050  
AC1-2122  
0768  
0992  
OLMC  
XOR-2051  
AC1-2123  
1024  
1248  
OLMC  
XOR-2052  
AC1-2124  
1280  
1504  
OLMC  
XOR-2053  
AC1-2125  
1536  
1760  
OLMC  
XOR-2054  
AC1-2126  
1792  
2016  
OLMC  
12  
11  
XOR-2055  
AC1-2127  
OE  
2191  
SYN-2192  
AC0-2193  
6
Specifications GAL16V8  
Complex Mode  
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the  
I/O functions. Registered mode.  
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product  
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and  
each macrocell.  
11 are always available as data inputs into the AND array.  
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses  
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.  
two outer most macrocells (pins 12 & 19) do not have input capa-  
Combinatorial I/O Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 13 through Pin 18 are configured to this function.  
Combinatorial Output Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 12 and Pin 19 are configured to this function.  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
7
Specifications GAL16V8  
Complex Mode Logic Diagram  
DIP & PLCC Package Pinouts  
1
2128  
PTD  
0
4
8
12  
16  
20  
24  
28  
0000  
0224  
OLMC  
19  
XOR-2048  
AC1-2120  
2
3
4
0256  
0480  
OLMC  
18  
XOR-2049  
AC1-2121  
0512  
0736  
OLMC  
17  
XOR-2050  
AC1-2122  
0768  
0992  
OLMC  
16  
XOR-2051  
AC1-2123  
5
6
7
8
1024  
1248  
OLMC  
15  
XOR-2052  
AC1-2124  
1280  
1504  
OLMC  
14  
XOR-2053  
AC1-2125  
1536  
1760  
OLMC  
13  
XOR-2054  
AC1-2126  
1792  
2016  
OLMC  
12  
XOR-2055  
AC1-2127  
9
11  
2191  
SYN-2192  
AC0-2193  
8
Specifications GAL16V8  
Simple Mode  
Pins 1 and 11 are always available as data inputs into the AND  
array. The center two macrocells (pins 15 & 16) cannot be used  
as input or I/O pins, and are only available as dedicated outputs.  
In the Simple mode, macrocells are configured as dedicated inputs  
or as dedicated, always active, combinatorial outputs.  
Architecture configurations available in this mode are similar to the  
common 10L8 and 12P6 devices with many permutations of ge-  
neric output polarity or input choices.  
The JEDEC fuse numbers including the UES fuses and PTD fuses  
are shown on the logic diagram.  
All outputs in the simple mode have a maximum of eight product  
terms that can control the logic. In addition, each output has pro-  
grammable polarity.  
Combinatorial Output with Feedback Configuration  
for Simple Mode  
Vcc  
- SYN=1.  
- AC0=0.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=0 defines this configuration.  
- All OLMC except pins 15 & 16 can be configured to  
this function.  
XOR  
Combinatorial Output Configuration for Simple Mode  
Vcc  
- SYN=1.  
- AC0=0.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=0 defines this configuration.  
- Pins 15 & 16 are permanently configured to this  
function.  
XOR  
Dedicated Input Configuration for Simple Mode  
- SYN=1.  
- AC0=0.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1 defines this configuration.  
- All OLMC except pins 15 & 16 can be configured to  
this function.  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
9
Specifications GAL16V8  
Simple Mode Logic Diagram  
DIP & PLCC Package Pinouts  
1
2128  
0
4
8
12  
16  
20  
24  
28  
PTD  
0000  
OLMC  
19  
18  
17  
16  
15  
14  
13  
XOR-2048  
AC1-2120  
0224  
2
0256  
OLMC  
XOR-2049  
AC1-2121  
0480  
3
0512  
OLMC  
XOR-2050  
AC1-2122  
0736  
4
0768  
OLMC  
XOR-2051  
AC1-2123  
0992  
5
1024  
OLMC  
XOR-2052  
AC1-2124  
1248  
6
1280  
OLMC  
XOR-2053  
AC1-2125  
1504  
7
1536  
OLMC  
XOR-2054  
AC1-2126  
1760  
8
1792  
OLMC  
12  
11  
XOR-2055  
AC1-2127  
2016  
9
2191  
SYN-2192  
AC0-2193  
10  
Specifications GAL16V8D  
(1)  
Absolute Maximum Ratings  
Recommended Operating Conditions  
Supply voltage VCC ...................................... –0.5 to +7V  
Input voltage applied .......................... –2.5 to VCC +1.0V  
Off-state output voltage applied ......... –2.5 to VCC +1.0V  
Storage Temperature ................................ –65 to 150°C  
Ambient Temperature with  
Commercial Devices:  
Ambient Temperature (TA) ............................... 0 to 75°C  
Supply voltage (VCC)  
with Respect to Ground ..................... +4.75 to +5.25V  
Power Applied ........................................ –55 to 125°C  
Industrial Devices:  
1.Stresses above those listed under the “Absolute Maximum  
Ratings” may cause permanent damage to the device. These  
are stress only ratings and functional operation of the device at  
these or at any other conditions above those indicated in the  
operational sections of this specification is not implied (while  
programming, follow the programming specifications).  
Ambient Temperature (TA) ........................... –40 to 85°C  
Supply voltage (VCC)  
with Respect to Ground ..................... +4.50 to +5.50V  
DC Electrical Characteristics  
Over Recommended Operating Conditions (Unless Otherwise Specified)  
SYMBOL  
PARAMETER  
CONDITION  
MIN.  
TYP.3  
MAX. UNITS  
VIL  
VIH  
IIL1  
Input Low Voltage  
Vss – 0.5  
2.0  
0.8  
Vcc+1  
–100  
10  
V
V
Input High Voltage  
Input or I/O Low Leakage Current  
Input or I/O High Leakage Current  
Output Low Voltage  
0V VIN VIL (MAX.)  
3.5V VIN VCC  
μA  
μA  
V
IIH  
VOL  
VOH  
IOL  
IOL = MAX. Vin = VIL or VIH  
IOH = MAX. Vin = VIL or VIH  
L-3/-5 & -7 (Ind. PLCC)  
0.5  
Output High Voltage  
2.4  
V
Low Level Output Current  
16  
mA  
mA  
L-7 (Except Ind. PLCC)/-10/-15/-25  
Q-10/-15/-20/-25  
24  
IOH  
IOS2  
High Level Output Current  
Output Short Circuit Current  
–3.2  
mA  
mA  
VCC = 5V VOUT = 0.5V TA= 25°C  
–30  
–150  
COMMERCIAL  
ICC  
Operating Power  
Supply Current  
VIL = 0.5V VIH = 3.0V  
L -3/-5/-7/-10  
L-15/-25  
75  
75  
115  
90  
mA  
mA  
ftoggle = 15MHz Outputs Open  
Q-10/-15/-25  
45  
55  
mA  
INDUSTRIAL  
ICC  
Operating Power  
Supply Current  
VIL = 0.5V VIH = 3.0V  
L -7/-10/-15/-25  
Q -20/-25  
75  
45  
130  
65  
mA  
mA  
ftoggle = 15MHz Outputs Open  
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.  
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester  
ground degradation. Characterized but not 100% tested.  
3) Typical values are at Vcc = 5V and TA = 25 °C  
11  
Specifications GAL16V8D  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-5  
COM / IND  
-7  
COM  
-3  
TEST  
COND1.  
DESCRIPTION  
PARAMETER  
UNITS  
MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
A
A
Input or I/O to Comb. Output  
Clock to Output Delay  
1
1
3.5  
3
1
1
5
4
3
1
1
7.5  
5
ns  
ns  
ns  
Clock to Feedback Delay  
2.5  
3
tsu  
th  
A
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
2.5  
0
3
0
5
0
ns  
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
182  
142.8 — 100  
MHz  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
200  
250  
166  
166  
125  
125  
MHz  
MHz  
fmax3  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
24  
24  
34  
34  
4
4
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
4.5  
4.5  
1
1
6
6
1
1
9
6
ns  
ns  
OE to Output Enabled  
tdis  
C
C
Input or I/O to Output Disabled  
4.5  
4.5  
1
1
5
5
1
1
9
6
ns  
ns  
OE to Output Disabled  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section. Characterized but not 100% tested.  
4) Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
CI/O  
pF  
*Characterized but not 100% tested.  
12  
SpecificationsGAL16V8D
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM / IND COM / IND  
IND  
-20  
COM / IND  
-25  
-10  
-15  
TEST  
COND1.  
DESCRIPTION  
PARAM.  
UNITS  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Comb. Output  
Clock to Output Delay  
3
2
10  
7
3
2
15  
10  
8
3
2
20  
11  
9
3
2
25  
12  
10  
ns  
ns  
ns  
ns  
Clock to Feedback Delay  
7.5  
6
12  
13  
15  
Setup Time, Input or Fdbk before Clk↑  
Hold Time, Input or Fdbk after Clk↑  
A
0
0
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
66.7  
45.5  
41.6  
37  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
71.4  
83.3  
50  
45.4  
50  
40  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
62.5  
41.6  
twh  
twl  
ten  
t
B
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
Input or I/O to Output Enabled  
OE to Output Enabled  
6
6
1
1
1
1
10  
10  
10  
10  
8
15  
15  
15  
15  
10  
10  
18  
18  
18  
18  
12  
12  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
8
B
tdis  
t
C
Input or I/O to Output Disabled  
OE to Output Disabled  
C
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section. Characterized but not 100% tested.  
Capacitance (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
pF  
pF  
CI/O  
*Characterized but not 100% tested.  
13  
Specifications GAL16V8  
Switching Waveforms  
INPUT or  
I/O FEEDBACK  
VALID INPUT  
su  
h
t
t
CLK  
INPUT or  
I/O FEEDBACK  
VALID INPUT  
t
co  
REGISTERED  
OUTPUT  
tpd  
COMBINATIONAL  
OUTPUT  
1/  
fmax  
(external fdbk)  
Combinatorial Output  
Registered Output  
INPUT or  
I/O FEEDBACK  
OE  
dis  
en  
t
t
dis  
t
en  
t
COMBINATIONAL  
OUTPUT  
REGISTERED  
OUTPUT  
Input or I/O to Output Enable/Disable  
OE to Output Enable/Disable  
wh  
wl  
t
t
CLK  
1/ max (internal fdbk)  
f
CLK  
cf  
t
su  
t
1/ max  
(w/o fb)  
f
REGISTERED  
FEEDBACK  
Clock Width  
fmax with Feedback  
14  
Specifications GAL16V8  
fmax Descriptions  
CLK  
CLK  
LOGIC  
ARRAY  
REGISTER  
LOGIC  
ARRAY  
t
su  
tco  
REGISTER  
fmax with External Feedback 1/(tsu+tco)  
Note: fmax with external feedback is calculated from measured  
t
cf  
pd  
tsu and tco.  
t
CLK  
fmax with Internal Feedback 1/(tsu+tcf)  
LOGIC  
REGISTER  
ARRAY  
Note: tcf is a calculated value, derived by subtracting tsu from  
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The  
value of tcf is used primarily when calculating the delay from  
clocking a register to a combinatorial output (through registered  
feedback), as shown above. For example, the timing from clock  
to a combinatorial output is equal to tcf + tpd.  
t
su + th  
fmax with No Feedback  
Note: fmax with no feedback may be less than 1/(twh + twl). This  
is to allow for a clock duty cycle of other than 50%.  
Switching Test Conditions  
Input Pulse Levels  
GAL16V8D-10  
GND to 3.0V  
2 – 3ns 10% – 90%  
(and slower)  
+5V  
Input Rise  
and Fall Times  
GAL16V8D-3/-5/-7  
1.5ns 10% – 90%  
R
1
Input Timing Reference Levels  
1.5V  
1.5V  
Output Timing Reference Levels  
Output Load  
FROM OUTPUT (O/Q)  
UNDER TEST  
See figure at right  
TEST POINT  
Table 2-0003/16V8  
3-state levels are measured 0.5V from  
steady-state active level.  
C L*  
R
2
GAL16V8D (except -3) Output Load Conditions (see figure  
above)  
Test Condition  
R1  
R2  
CL  
*CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE  
A
200Ω  
390Ω  
390Ω  
390Ω  
390Ω  
390Ω  
50pF  
50pF  
50pF  
5pF  
B
Active High  
Active Low  
Active High  
Active Low  
200Ω  
C
200Ω  
5pF  
15  
Specifications GAL16V8  
Switching Test Conditions (Continued)  
GAL16V8D-3 Output Load Conditions (see figure at right)  
+1.45V  
Test Condition  
R1  
CL  
TEST POINT  
A
50Ω  
50Ω  
50Ω  
50Ω  
50Ω  
35pF  
35pF  
35pF  
35pF  
35pF  
R
1
B
High Z to Active High at 1.9V  
High Z to Active Low at 1.0V  
Active High to High Z at 1.9V  
Active Low to High Z at 1.0V  
FROM OUTPUT (O/Q)  
UNDER TEST  
Z0 = 50Ω, CL = 35pF*  
C
*CL includes test fixture and probe capacitance.  
Electronic Signature  
Output Register Preload  
An electronic signature is provided in every GAL16V8 device. It  
contains 64 bits of reprogrammable memory that can contain user  
defined data. Some uses include user ID codes, revision numbers,  
or inventory control. The signature data is always available to the  
user independent of the state of the security cell.  
When testing state machine designs, all possible states and state  
transitions must be verified in the design, not just those required  
in the normal machine operations. This is because, in system  
operation, certain events occur that may throw the logic into an  
illegal state (power-up, line voltage glitches, brown-outs, etc.). To  
test a design for proper treatment of these conditions, a way must  
be provided to break the feedback paths, and force any desired (i.e.,  
illegal) state into the registers. Then the machine can be sequenced  
and the outputs tested for correct next state conditions.  
NOTE: The electronic signature is included in checksum calcula-  
tions. Changing the electronic signature will alter the checksum.  
Security Cell  
GAL16V8 devices include circuitry that allows each registered  
output to be synchronously set either high or low. Thus, any present  
state condition can be forced for test sequencing. If necessary,  
approved GAL programmers capable of executing text vectors  
perform output register preload automatically.  
A security cell is provided in the GAL16V8 devices to prevent un-  
authorized copying of the array patterns. Once programmed, this  
cell prevents further read access to the functional bits in the device.  
This cell can only be erased by re-programming the device, so the  
original configuration can never be examined once this cell is pro-  
grammed. The Electronic Signature is always available to the user,  
regardless of the state of this control cell.  
Input Buffers  
GAL16V8 devices are designed with TTL level compatible input  
buffers. These buffers have a characteristically high impedance,  
and present a much lighter load to the driving logic than bipolar TTL  
devices.  
Latch-Up Protection  
GAL16V8 devices are designed with an on-board charge pump  
to negatively bias the substrate. The negative bias minimizes the  
potential of latch-up caused by negative input undershoots. Ad-  
ditionally, outputs are designed with n-channel pull-ups instead of  
the traditional p-channel pull-ups in order to eliminate latch-up due  
to output overshoots.  
The GAL16V8 input and I/O pins have built-in active pull-ups. As  
a result, unused inputs and I/O's will float to a TTL "high" (logical  
"1"). Lattice Semiconductor recommends that all unused inputs  
and tri-stated I/O pins be connected to another active input, VCC  
,
or Ground. Doing this will tend to improve noise immunity and re-  
duce ICC for the device.  
Device Programming  
GAL devices are programmed using a Lattice Semiconductor-  
approved Logic Programmer, available from a number of manu-  
facturers. Complete programming of the device takes only a few  
seconds. Erasing of the device is transparent to the user, and is  
done automatically as part of the programming cycle.  
Typical Input Pull-up Characteristic  
0
- 2 0  
- 4 0  
- 6 0  
0
1 . 0  
2 . 0  
3 . 0  
4 . 0  
5 . 0  
Input Voltage (Volts)  
16  
Specifications GAL16V8  
Power-Up Reset  
Vcc (min.)  
Vcc  
t
su  
t
wl  
CLK  
t
pr  
Internal Register  
Reset to Logic "0"  
INTERNAL REGISTER  
Q - OUTPUT  
FEEDBACK/EXTERNAL  
OUTPUT REGISTER  
Device Pin  
Reset to Logic "1"  
Circuitry within the GAL16V8 provides a reset signal to all reg-  
isters during power-up. All internal registers will have their Q  
outputs set low after a specified time (tpr, 1μs MAX). As a result,  
the state on the registered output pins (if they are enabled) will  
always be high on power-up, regardless of the programmed  
polarity of the output pins. This feature can greatly simplify state  
machine design by providing a known state on power-up. Be-  
cause of the asynchronous nature of system power-up, some  
conditions must be met to provide a valid power-up reset of the  
device. First, the VCC rise must be monotonic. Second, the clock  
input must be at static TTL level as shown in the diagram during  
power up. The registers will reset within a maximum of tpr time.  
As in normal system operation, avoid clocking the device until all  
input and feedback path setup times have been met. The clock  
must also meet the minimum pulse width requirements.  
Input/Output Equivalent Schematics  
INPUT/OUTPUT EQUIVALENT SCHEMATICS  
PIN  
PIN  
Feedback  
Vcc  
Active Pull-up  
Circuit  
Active Pull-up  
Circuit  
Vcc  
Tri-State  
Control  
Vref  
Vcc  
Vcc  
Vref  
ESD  
Protection  
Circuit  
Data  
Output  
PIN  
PIN  
ESD  
Protection  
Circuit  
Feedback  
(To Input Buffer)  
Typ. Vref = 3.2V  
Typ. Vref = 3.2V  
Typical Input  
Typical Output  
17  
Specifications GAL16V8  
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams  
Normalized Tco vs Vcc  
N
ormalized Tpd vs Vcc  
Normalized Tsu vs Vcc  
1.2  
1.1  
1
1.2  
1.1  
1.2  
1.1  
1
PT H->L  
PT L->H  
RISE  
FALL  
PT H->L  
PT L->H  
1
0.9  
0.8  
0.9  
0.9  
0.8  
0.8  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
Supply Voltage (V)  
Supply Voltage (V)  
Supply Voltage (V)  
Normalized Tpd vs Temp  
Normalized Tco vs Temp  
Normalized Tsu vs Temp  
1.3  
1.2  
1.1  
1.3  
1.3  
1.2  
1.1  
1
1.2  
1.1  
PT H->L  
PT L->H  
PTH->L  
PT L->H  
RISE  
FALL  
1
1
0.9  
0.9  
0.9  
0.8  
0.7  
0.8  
0.7  
0.8  
0.7  
-55  
-25  
0
25  
50  
75  
100  
125  
-55  
-25  
0
25  
50  
75  
100  
125  
-55  
-25  
0
25  
50  
75  
100 125  
Temperature (deg. C)  
Temperature (deg. C)  
Temperature (deg. C)  
Delta Tco vs # of Outputs  
Switching  
Delta Tpd vs # of Outputs  
Switching  
0
0
-0.1  
-0.1  
-0.2  
-0.3  
-0.2  
-0.3  
RISE  
FALL  
RISE  
FALL  
-0.4  
1
-0.4  
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching  
Number of Outputs Switching  
Delta Tpd vs Output Loading  
Delta Tco vs Output Loading  
14  
12  
10  
14  
12  
10  
RISE  
FALL  
RISE  
FALL  
8
6
4
8
6
4
2
0
2
0
-2  
-2  
0
0
50  
100  
150  
200  
250  
300  
50  
100  
150  
200  
250  
300  
Output Loading (pF)  
Output Loading (pF)  
18  
Specifications GAL16V8  
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams  
Vol vs Iol  
Voh vs Ioh  
Voh vs Ioh  
3.25  
1
0.75  
0.5  
5
4
3
2
1
0
3
2.75  
2.5  
0.25  
0
0
10  
20  
30  
40  
50  
0
1
2
3
4
0
10  
20  
30  
40  
Ioh (mA)  
Ioh (mA)  
Iol (mA)  
Normalized Icc vs Vcc  
Normalized Icc vs Temp  
Normalized Icc vs Freq.  
1.2  
1.15  
1.1  
1.3  
1.2  
1.1  
1
1.2  
1.1  
1
1.05  
1
0.9  
0.9  
0.95  
0.9  
0.8  
0.8  
4.50  
4.75  
5.00  
5.25  
5.50  
-55  
-25  
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
Supply Voltage (V)  
Temperature (deg. C)  
Frequency (MHz)  
Input Clamp (Vik)  
Delta Icc vs Vin (1 input)  
10  
0
10  
20  
30  
40  
8
6
50  
60  
70  
80  
4
2
0
90  
-2  
-1.5  
-1  
-0.5  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
Vik (V)  
Vin (V)  
19  
Specifications GAL16V8  
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams  
Normalized Tpd vs Vcc  
Normalized Tsu vs Vcc  
Normalized Tco vs Vcc  
1.15  
1.1  
1.05  
1
1.2  
1.1  
1
1.15  
1.1  
RISE  
FALL  
RISE  
FALL  
RISE  
FALL  
1.05  
1
0.9  
0.8  
0.95  
0.95  
0.9  
0.9  
4.5  
4.75  
5
5.25  
5.5  
4.5  
4.75  
5
5.25  
5.5  
4.5  
4.75  
5
5.25  
5.5  
Supply Voltage (V)  
Supply Voltage (V)  
Supply Voltage (V)  
Normalized Tsu vs Temp  
Normalized Tpd vs Temp  
Normalized Tco vs Temp  
1.3  
1.2  
1.1  
1
1.3  
1.3  
1.2  
1.1  
1
RISE  
FALL  
RISE  
FALL  
RISE  
FALL  
1.2  
1.1  
1
0.9  
0.8  
0.9  
0.9  
0.8  
0.8  
-55 -25  
0
25  
50  
75  
100 125  
-55  
-25  
0
25  
50  
75  
100 125  
-55  
-25  
0
25  
50  
75  
100 125  
Temperature (deg. C)  
Temperature (deg. C)  
Temperature (deg. C)  
Delta Tpd vs # of Outputs Switching  
Delta Tco vs # of Outputs Switching  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.6  
RISE  
FALL  
RISE  
FALL  
-0.7  
-0.7  
-0.8  
-0.9  
-1  
-0.8  
-0.9  
-1  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching  
Number of Outputs Switching  
Delta Tpd vs Output Loading  
Delta Tco vs Output Loading  
12  
8
12  
8
RISE  
FALL  
RISE  
FALL  
4
4
0
0
-4  
-4  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Output Loading (pF)  
Output Loading (pF)  
20  
Specifications GAL16V8  
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams  
Voh vs Ioh  
Vol vs Iol  
Voh vs Ioh  
4
3
2
1
0
0.5  
0.4  
0.3  
0.2  
0.1  
0
4
3.5  
3
2.5  
0
5
10  
15  
20  
25  
1
6
11  
16  
21  
26  
0.00  
1.00  
2.00  
3.00  
4.00  
5.00  
Ioh (mA)  
Iol (mA)  
Ioh (mA)  
Normalized Icc vs Vcc  
Normalized Icc vs Temp  
Normalized Icc vs Freq  
1.1  
1.2  
1.1  
1
1.15  
1.1  
1
1.05  
1
0.9  
0.8  
0.9  
0.8  
0.95  
3
3.15  
3.3  
3.45  
3.6  
-55  
-25  
0
25  
50  
88  
100 125  
1
15  
25  
50  
75  
100  
Supply Voltage (V)  
Temperature (deg. C)  
Frequency (MHz)  
Input Clamp (Vik)  
Delta Icc vs Vin (1 input)  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
9
8
7
6
5
4
3
2
1
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
-3  
-2.5  
-2  
-1.5  
-1  
-0.5  
0
Vin (V)  
Vik (V)  
21  
Specifications GAL16V8  
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams  
Normalized Tpd vs Vcc  
Normalized Tsu vs Vcc  
Normalized Tco vs Vcc  
1.2  
1.1  
1
1.2  
1.1  
1
1.2  
1.1  
1
RISE  
FALL  
PT H->L  
PT L->H  
PT H->L  
PT L->H  
0.9  
0.9  
0.9  
0.8  
0.8  
0.8  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
Supply Voltage (V)  
Supply Voltage (V)  
Supply Voltage (V)  
Normalized Tco vs Temp  
Normalized Tpd vs Temp  
Normalized Tsu vs Temp  
1.3  
1.2  
1.1  
1
1.3  
1.2  
1.1  
1
1.3  
1.2  
1.1  
1
RISE  
FALL  
PT H->L  
PT L->H  
PT H->L  
PT L->H  
0.9  
0.8  
0.7  
0.9  
0.8  
0.7  
0.9  
0.8  
0.7  
-55  
-25  
0
25  
50  
75  
100 125  
-55  
-25  
0
25  
50  
75  
100 125  
-55  
-25  
0
25  
50  
75  
100 125  
Temperature (deg. C)  
Temperature (deg. C)  
Temperature (deg. C)  
Delta Tpd vs # of Outputs  
Switching  
Delta Tco vs # of Outputs  
Switching  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
RISE  
FALL  
RISE  
FALL  
-1.2  
1
-1.2  
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching  
Number of Outputs Switching  
Delta Tpd vs Output Loading  
Delta Tco vs Output Loading  
12  
10  
8
12  
10  
8
RISE  
FALL  
RISE  
FALL  
6
6
4
4
2
2
0
0
-2  
-4  
-6  
-2  
-4  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Output Loading (pF)  
Output Loading (pF)  
22  
Specifications GAL16V8  
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams  
Voh vs Ioh  
Voh vs Ioh  
Vol vs Iol  
5
4
3
2
1
0
4
3.8  
3.6  
3.4  
3.2  
3
0.6  
0.4  
0.2  
0
0
10  
20  
30  
40  
50  
0
1
2
3
4
0
10  
20  
30  
40  
Ioh (mA)  
Normalized Icc vs Temp  
Ioh (mA)  
Iol (mA)  
Normalized Icc vs Vcc  
Normalized Icc vs Freq.  
1.2  
1.3  
1.2  
1.1  
1
1.4  
1.3  
1.2  
1.1  
1
1.1  
1
0.9  
0.8  
0.7  
0.9  
0.8  
0.9  
0.8  
4.50  
4.75  
5.00  
5.25  
5.50  
-55  
-25  
0
25  
50  
75  
100 125  
0
25  
50  
75  
100  
Supply Voltage (V)  
Temperature (deg. C)  
Frequency (MHz)  
Delta Icc vs Vin (1 input)  
Input Clamp (Vik)  
8
6
4
2
0
0
10  
20  
30  
40  
50  
60  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
-2  
-1.5  
-1  
-0.5  
0
Vin (V)  
Vik (V)  
23  
Specifications GAL16V8  
Revision History  
Date  
Version  
16v8_10  
16v8_11  
Change Summary  
-
Previous Lattice release.  
August 2006  
Updated for lead-free package options.  
24  
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