GAL22V10D-15LPN中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

GAL^®22V10 Device Datasheet

September 2010

All Devices Discontinued!

Product Change Notifications (PCNs) have been issued to discontinue all devices in this

data sheet.

The original datasheet pages have not been modified and do not reflect those changes.

Please refer to the table below for reference PCN and current product status.

Product Line

Ordering Part Number

GAL22V10D-7LP

Product Status

Reference PCN

PCN#09-10

GAL22V10D-7LPN

GAL22V10D-10LP

GAL22V10D-10LPN

GAL22V10D-15LP

GAL22V10D-15LPN

GAL22V10D-25LP

GAL22V10D-25LPN

GAL22V10D-7LPI

GAL22V10D-7LPNI

GAL22V10D-10LPI

GAL22V10D-10LPNI

GAL22V10D-15LPI

GAL22V10D-15LPNI

GAL22V10D-20LPI

GAL22V10D-20LPNI

GAL22V10D-25LPI

GAL22V10D-25LPNI

GAL22V10D-10QP

GAL22V10D-10QPN

GAL22V10D-15QP

GAL22V10D-15QPN

GAL22V10D-25QP

GAL22V10D-25QPN

GAL22V10D-10LS

GAL22V10D-15LS

GAL22V10D-25LS

GAL22V10D-4LJ

PCN#13-10

PCN#09-10

GAL22V10D

Discontinued

PCN#13-10

PCN#06-07

PCN#09-10

PCN#13-10

GAL22V10D-4LJN

GAL22V10D-5LJ

GAL22V10D-5LJN

5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347

Internet: http://www.latticesemi.com

Product Line

Ordering Part Number

GAL22V10D-7LJ

Product Status

Reference PCN

GAL22V10D-7LJN

GAL22V10D-10LJ

GAL22V10D-10LJN

GAL22V10D-15LJ

GAL22V10D-15LJN

GAL22V10D-25LJ

GAL22V10D-25LJN

GAL22V10D-7LJI

PCN#13-10

GAL22V10D-7LJNI

GAL22V10D-10LJI

GAL22V10D-10LJNI

GAL22V10D-15LJI

GAL22V10D-15LJNI

GAL22V10D-20LJI

GAL22V10D-20LJNI

GAL22V10D-25LJI

GAL22V10D-25LJNI

GAL22V10D-10QJ

GAL22V10D-10QJN

GAL22V10D-15QJ

GAL22V10D-15QJN

GAL22V10D-25QJ

GAL22V10D-25QJN

PCN#09-10

PCN#13-10

GAL22V10D

Discontinued

(Cont’d)

5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347

Internet: http://www.latticesemi.com

Specifications GAL22V10

GAL22V10

High Performance E²CMOS PLD

Generic Array Logic™

Functional Block Diagram

Features

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

RESET

I/CLK

8

OLMC

I/O/Q

I

— 3.5 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

10

12

• ACTIVE PULL-UPS ON ALL PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and UVCMOS 22V10 Devices

I/O/Q

14

16

14

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR

— 90mA Typical Icc on Low Power Device

— 45mA Typical Icc on Quarter Power Device

• E²CELL TECHNOLOGY

— Reconfigurable Logic

I/O/Q

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

I

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

12

10

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

I

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

8

PRESET

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Pin Configuration

• LEAD-FREE PACKAGE OPTIONS

ESCRIPTION

PLCC

Description

DIP

4

2

28

26

5

7

25

23

I

I/O/Q

The GAL22V10, at 4ns maximum propagation delay time, combines

a high performance CMOS process with Electrically Erasable (E²)

floating gate technology to provide the highest performance avail-

able of any 22V10 device on the market. CMOS circuitry allows

the GAL22V10 to consume much less power when compared to

bipolar 22V10 devices. E²technology offers high speed (<100ms)

erase times, providing the ability to reprogram or reconfigure the

device quickly and efficiently.

1

Vcc

24

I/CLK

I/O/Q

I

GAL22V10

Top View

NC

I/O/Q

I

9

21

I/O/Q

GAL

11

19

18

22V10

12

14

16

6

18

I

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL22V10 is fully function/fuse map/parametric com-

patible with standard bipolar and CMOS 22V10 devices.

SOIC

I

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

GAL22V10

Top View

GND

12

13

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 2006

22v10_12

1

Specifications GAL22V10

GAL22V10 Ordering Information

Conventional Packaging

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

4

5

7.5

2.5

3

4.5

7

3.5

4

4.5

7

140

55

GAL22V10D-4LJ

GAL22V10D-5LJ

GAL22V10D-7LP

GAL22V10D-7LJ

GAL22V10D-10QP

GAL22V10D-10QJ

GAL22V10D-10LP

GAL22V10D-10LJ

GAL22V10D-10LS

GAL22V10D-15QP

GAL22V10D-15QJ

GAL22V10D-15LP

GAL22V10D-15LJ

28-Lead PLCC

24-Pin Plastic DIP

28-Lead PLCC

24-Pin Plastic DIP

28-Lead PLCC

24-Pin Plastic DIP

28-Lead PLCC

24-Pin SOIC

24-Pin Plastic DIP

28-Lead PLCC

24-Pin Plastic DIP

28-Lead PLCC

24-Pin SOIC

10

15

25

55

130

30

55

90

55

90

1

10

15

8

1

GAL22V10D-15LS

GAL22V10D-25QP

GAL22V10D-25QJ

GAL22V10D-25LP

GAL22V10D-25LJ

15

24-Pin Plastic DIP

28-Lead PLCC

24-Pin Plastic Dip

28-Lead PLCC

24-Pin SOIC

1

GAL22V10D-25LS

1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

7.5

10

15

20

25

5

4.5

7

4.5

7

160

130

24-Pin Plastic DIP

28-Lead PLCC

GAL22V10D-7LPI

GAL22V10D-7LJI

GAL22V10D-10LPI

GAL22V10D-10LJI

GAL22V10D-15LPI

GAL22V10D-15LJI

GAL22V10D-20LPI

GAL22V10D-20LJI

GAL22V10D-25LPI

GAL22V10D-25LJI

24-Pin Plastic DIP

28-Lead PLCC

10

14

15

8

24-Pin Plastic DIP

28-Lead PLCC

10

15

24-Pin Plastic DIP

28-Lead PLCC

24-Pin Plastic DIP

28-Lead PLCC

2

Specifications GAL22V10

Lead-Free Packaging

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

4

5

2.5

3

3.5

4

140

55

GAL22V10D-4LJN

GAL22V10D-5LJN

GAL22V10D-7LPN

GAL22V10D-7LJN

GAL22V10D-10QPN

GAL22V10D-10QJN

GAL22V10D-10LPN

GAL22V10D-10LJN

GAL22V10D-15QPN

GAL22V10D-15QJN

GAL22V10D-15LPN

GAL22V10D-15LJN

GAL22V10D-25QPN

GAL22V10D-25QJN

GAL22V10D-25LPN

GAL22V10D-25LJN

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic Dip

Lead-Free 28-Lead PLCC

7.5

4.5

7

4.5

7

10

15

25

55

130

55

10

15

8

55

90

15

55

90

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

7.5

10

15

20

25

5

4.5

7

4.5

7

160

130

GAL22V10D-7LPNI

GAL22V10D-7LJNI

GAL22V10D-10LPNI

GAL22V10D-10LJNI

GAL22V10D-15LPNI

GAL22V10D-15LJNI

GAL22V10D-20LPNI

GAL22V10D-20LJNI

GAL22V10D-25LPNI

GAL22V10D-25LJNI

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic DIP

Lead-Free 28-Lead PLCC

Lead-Free 24-Pin Plastic Dip

Lead-Free 28-Lead PLCC

10

14

15

8

10

15

Part Number Description

_

XXXXXXXX XX X XX X

GAL22V10D Device Name

Grade

Blank = Commercial

I = Industrial

Speed (ns)

L = Low Power

Q = Quarter Power

Power

Package P = Plastic DIP

PN = Lead-Free Plastic DIP

J = PLCC

JN = Lead-Free PLCC

S = SOIC

3

Specifications GAL22V10

Output Logic Macrocell (OLMC)

The GAL22V10 has a variable number of product terms per OLMC.

Of the ten available OLMCs, two OLMCs have access to eight

product terms (pins 14 and 23, DIP pinout), two have ten product

terms (pins 15 and 22), two have twelve product terms (pins 16 and

21), two have fourteen product terms (pins 17 and 20), and two

OLMCs have sixteen product terms (pins 18 and 19). In addition

to the product terms available for logic, each OLMC has an addi-

tional product-term dedicated to output enable control.

The GAL22V10 has a product term for Asynchronous Reset (AR)

and a product term for Synchronous Preset (SP). These two prod-

uct terms are common to all registered OLMCs. TheAsynchronous

Reset sets all registers to zero any time this dedicated product term

is asserted. The Synchronous Preset sets all registers to a logic

one on the rising edge of the next clock pulse after this product term

is asserted.

NOTE: TheAR and SP product terms will force the Q output of the

flip-flop into the same state regardless of the polarity of the output.

Therefore, a reset operation, which sets the register output to a zero,

may result in either a high or low at the output pin, depending on

the pin polarity chosen.

The output polarity of each OLMC can be individually programmed

to be true or inverting, in either combinatorial or registered mode.

This allows each output to be individually configured as either active

high or active low.

A R

D

4 T O 1

M U X

Q

C L K

Q

S P

2 T O 1

M U X

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

Output Logic Macrocell Configurations

Each of the Macrocells of the GAL22V10 has two primary functional NOTE: In registered mode, the feedback is from the /Q output of

modes: registered, and combinatorial I/O. The modes and the the register, and not from the pin; therefore, a pin defined as reg-

output polarity are set by two bits (SO and S1), which are normally istered is an output only, and cannot be used for dynamic

controlled by the logic compiler. Each of these two primary modes, I/O, as can the combinatorial pins.

and the bit settings required to enable them, are described below

and on the following page.

COMBINATORIAL I/O

In combinatorial mode the pin associated with an individual OLMC

is driven by the output of the sum term gate. Logic polarity of the

REGISTERED

In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the output

OLMC is driven by the Q output of that OLMC’s D-type flip-flop. buffer drive either true (active high) or inverted (active low). Out-

Logic polarity of the output signal at the pin may be selected by put tri-state control is available as an individual product-term for

specifying that the output buffer drive either true (active high) or each output, and may be individually set by the compiler as either

inverted (active low). Output tri-state control is available as an in- “on” (dedicated output), “off” (dedicated input), or “product-term

dividual product-term for each OLMC, and can therefore be defined driven” (dynamic I/O). Feedback into the AND array is from the pin

by a logic equation. The D flip-flop’s /Q output is fed back into the side of the output enable buffer. Both polarities (true and inverted)

AND array, with both the true and complement of the feedback of the pin are fed back into the AND array.

available as inputs to the AND array.

4

Specifications GAL22V10

Registered Mode

A R

D

Q

D

Q

C L K

S P

ACTIVE LOW

ACTIVE HIGH

S₀= 0

S₁= 0

S₀= 1

S₁= 0

Combinatorial Mode

ACTIVE LOW

ACTIVE HIGH

S₀= 0

S₁= 1

S₀= 1

S₁= 1

5

Specifications GAL22V10

GAL22V10 Logic Diagram / JEDEC Fuse Map

DIP (PLCC) Package Pinouts

1 (2)

0

4

8

12

16

20

24

28

32

36

40

ASYNCHRONOUS RESET

(TO ALL REGISTERS)

0000

0044

.

8

OLMC

23 (27)

S0

0396

5808

S1

5809

0440

.

10

OLMC

22 (26)

S0

5810

S1

5811

0880

2 (3)

3 (4)

0924

.

12

OLMC

21 (25)

20 (24)

S0

5812

S1

1452

5813

1496

.

14

16

OLMC

S0

5814

S1

2112

5815

4 (5)

5 (6)

2156

.

19 (23)

18 (21)

17 (20)

OLMC

S0

5816

S1

2860

5817

2904

.

16

OLMC

S0

5818

S1

3608

5819

6 (7)

7 (9)

3652

.

14

12

OLMC

S0

5820

S1

4268

5821

4312

.

OLMC

16 (19)

15 (18)

S0

5822

S1

4840

5823

8 (10)

9 (11)

4884

.

10

8

OLMC

S0

5824

S1

5324

5825

5368

.

OLMC

14 (17)

13 (16)

S0

5826

S1

5720

5827

10 (12)

11 (13)

5764

SYNCHRONOUS PRESET

(TO ALL REGISTERS)

5828, 5829 ... Electronic Signature ... 5890, 5891

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

M

S

B

L

S

B

6

Specifications GAL22V10D

Specifications GAL22V10

1

Absolute Maximum Ratings

Recommended Operating Conditions

Commercial Devices:

Supply voltage V_CC....................................... -0.5 to +7V

Ambient Temperature (T_A) ............................. 0 to +75°C

Supply voltage (V_CC)

Input voltage applied ........................... -2.5 to V_CC+1.0V

Off-state output voltage applied........... -2.5 to V_CC+1.0V

Storage Temperature..................................-65 to 150°C

Ambient Temperature with

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

Ambient Temperature (T_A) ............................-40 to 85°C

Supply voltage (V_CC)

Power Applied .........................................-55 to 125°C

1. Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress only ratings and functional operation of the device

at these or at any other conditions above those indicated in

the operational sections of this specification is not implied

(while programming, follow the programming specifications).

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL

PARAMETER CONDITION MIN.

TYP.³

MAX. UNITS

VIL

VIH

IIL¹

Input Low Voltage

Vss – 0.5

2.0

—

0.8

Vcc+1

–100

10

V

Input High Voltage

Input or I/O Low Leakage Current

0V ≤ VIN ≤ VIL (MAX.)

μA

V

IIH

Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC

—

VOL

VOH

IOL

Output Low Voltage

IOL = MAX. Vin = VIL or VIH

—

0.4

Output High Voltage

IOH = MAX. Vin = VIL or VIH

2.4

—

V

Low Level Output Current

High Level Output Current

Output Short Circuit Current

16

mA

IOH

IOS²

—

–3.2

–130

VCC = 5V VOUT = 0.5V T_A= 25°C

–30

COMMERCIAL

ICC

Operating Power

VIL = 0.5V VIH = 3.0V

L-4/-5/-7

—

90

75

45

140

130

90

mA

Supply Current

f^toggle= 15MHz Outputs Open L-10

L-15/-25

Q-10/-15/-25

55

INDUSTRIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V

L-7/-10

—

90

75

160

130

mA

f^toggle= 15MHz Outputs Open L-15/-20/-25

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C

7

Specifications GAL22V10D

Specifications GAL22V10

AC Switching Characteristics

Over Recommended Operating Conditions

COM

-4

COM

-5

COM/IND

-7

TEST

DESCRIPTION

Input or I/O to Combinatorial Output

PARAM

COND.¹

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

tpd

tco

tcf²

tsu

th

A

1

4

1

5

1

7.5

4.5

3

ns

Clock to Output Delay

1

3.5

2.5

—

1

4

1

—

Clock to Feedback Delay

—

2.5

—

3

—

4.5

Setup Time, Input or Fdbk before Clk↑

Hold Time, Input or Fdbk after Clk↑

—

A

0

—

0

—

0

—

ns

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

167

142.8

111

MHz

fmax³

A

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

200

250

—

166

200

—

133

166

—

MHz

Maximum Clock Frequency with

No Feedback

twh

twl

—

B

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

2

1

—

5

2.5

1

—

6

3

1

—

ns

ten

7.5

tdis

tar

C

A

Input or I/O to Output Disabled

1

5

1

5.5

1

7.5

9

ns

Input or I/O to Asynch. Reset of Reg.

4.5

tarw

tarr

—

Asynch. Reset Pulse Duration

4.5

3

—

4.5

4

—

7

5

—

ns

Asynch. Reset to Clk↑ Recovery Time

Synch. Preset to Clk↑ Recovery Time

tspr

3

4

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these

parameters.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

pF

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

8

C_I/O

pF

*Characterized but not 100% tested.

8

SpSepceifcicifaictaiotinosnsGGALA2L22V21V01D0

AC Switching Characteristics

Over Recommended Operating Conditions

COM / IND COM / IND

IND

-20

COM / IND

-25

-10

-15

TEST

COND.¹

DESCRIPTION

PARAM.

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

MIN. MAX.

tpd

tco

tcf²

A

Input or I/O to Comb. Output

Clock to Output Delay

1

10

7

3

2

15

8

3

2

20

10

8

3

25

15

13

ns

2

—

Clock to Feedback Delay

—

2.5

—

2.5

—

tsu

th

—

A

Setup Time, Input or Fdbk before Clk↑

Hold Time, Input or Fdbk after Clk↑

6

0

—

10

0

—

12

0

—

15

0

—

ns

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

83.3

55.5

41.6

33.3

MHz

fmax³

A

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

110

125

—

80

—

45.4

50

—

35.7

38.5

—

MHz

Maximum Clock Frequency with

No Feedback

83.3

twh

twl

—

B

Clock Pulse Duration, High

4

1

8

—

10

9

6

—

15

20

—

10

3

—

20

25

—

13

3

—

25

—

ns

Clock Pulse Duration, Low

ten

tdis

tar

Input or I/O to Output Enabled

Input or I/O to Output Disabled

Input or I/O to Asynch. Reset of Reg.

Asynch. Reset Pulse Duration

Asynch. Reset to Clk↑ Recovery Time

Synch. Preset to Clk↑ Recovery Time

3

C

3

A

13

—

3

tarw

tarr

tspr

—

15

10

20

14

25

15

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

8

pF

C_I/O

*Characterized but not 100% tested.

9

Specifications GAL22V10

Switching Waveforms

INPUT or

I/O FEEDBACK

INPUT or

VALID INPUT

I/O FEEDBACK

t_su

t_h

t

pd

CLK

COMBINATORIAL

OUTPUT

t_co

REGISTERED

OUTPUT

Combinatorial Output

1/

f

max

(external fdbk)

Registered Output

INPUT or

I/O FEEDBACK

t

dis

t

en

OUTPUT

CLK

1/

f

max (internal fdbk)

Input or I/O to Output Enable/Disable

t

cf su

t

REGISTERED

FEEDBACK

fmax with Feedback

t

w l

t_{w h}

CLK

1/

fm a x

(w/o fdbk)

Clock Width

INPUT or

I/O FEEDBACK

DRIVING AR

INPUT or

I/O FEEDBACK

DRIVING SP

t

arw

t

su

t

h

t

spr

CLK

t

arr

t

co

REGISTERED

OU TPUT

REGISTERED

OUTPUT

t

ar

Synchronous Preset

Asynchronous Reset

10

Specifications GAL22V10

fmax Descriptions

CL K

CLK

LOGIC

ARRAY

LOGIC

ARR AY

REGI STER

REGISTER

t

su

tco

fmax with External Feedback 1/(tsu+tco)

t

cf

pd

t

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

fmax with Internal Feedback 1/(tsu+tcf)

CLK

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal

feedback (tcf = 1/fmax - tsu). The value of tcf is

used primarily when calculating the delay from

clocking a register to a combinatorial output

(through registered feedback), as shown above.

For example, the timing from clock to a combi-

natorial output is equal to tcf + tpd.

LOGIC

REGISTER

ARRAY

tsu + th

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a

clock duty cycle of other than 50%.

11

Specifications GAL22V10

Switching Test Conditions

GAL22V10D-4 Output Load Conditions (see figure below)

Input Pulse Levels

GND to 3.0V

1.5ns 10% – 90%

2.0ns 10% – 90%

1.5V

Input Rise and D-4/-5/-7

Test Condition

R¹

CL

Fall Times

D-10/-15/-20/-25

A

50Ω

50pF

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

B

Z to Active High at 1.9V

1.5V

Z to Active Low at 1.0V

Active High to Z at 1.9V

Active Low to Z at 1.0V

See Figure

C

3-state levels are measured 0.5V from steady-state active

level.

+1.45V

Output Load Conditions (except D-4) (see figure below)

TEST POINT

R

1

Test Condition

R¹

R2

CL

FROM OUTPUT (O/Q)

UNDER TEST

A

300Ω

∞

390Ω

50pF

5pF

Z₀= 50Ω, CL*

B

Active High

Active Low

Active High

Active Low

300Ω

∞

C

300Ω

5pF

+5V

R

1

FROM OUTPUT (O/Q)

UNDER TEST

TEST POINT

C _L*

R

2

*C_LINCLUDES TEST FIXTURE AND PROBE CAPACITANCE

12

Specifications GAL22V10

Electronic Signature

Output Register Preload

An electronic signature (ES) is provided in every GAL22V10

device. It contains 64 bits of reprogrammable memory that can

contain user-defined data. Some uses include user ID codes,

revision numbers, or inventory control. The signature data is

always available to the user independent of the state of the se-

curity cell.

When testing state machine designs, all possible states and state

transitions must be verified in the design, not just those required

in the normal machine operations. This is because certain events

may occur during system operation that throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired

(i.e., illegal) state into the registers. Then the machine can be

sequenced and the outputs tested for correct next state condi-

tions.

The electronic signature is an additional feature not present in

other manufacturers' 22V10 devices. To use the extra feature of

the user-programmable electronic signature it is necessary to

choose a Lattice Semiconductor 22V10 device type when com-

piling a set of logic equations. In addition, many device program-

mers have two separate selections for the device, typically a

GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-

nature) or GAL22V10-ES. This allows users to maintain compat-

ibility with existing 22V10 designs, while still having the option to

use the GAL device's extra feature.

The GAL22V10 device includes circuitry that allows each regis-

tered output to be synchronously set either high or low. Thus, any

present state condition can be forced for test sequencing. If

necessary, approved GALprogrammers capable of executing test

vectors perform output register preload automatically.

Input Buffers

The JEDEC map for the GAL22V10 contains the 64 extra fuses

for the electronic signature, for a total of 5892 fuses. However,

the GAL22V10 device can still be programmed with a standard

22V10 JEDEC map (5828 fuses) with any qualified device pro-

grammer.

GAL22V10 devices are designed with TTL level compatible in-

put buffers. These buffers have a characteristically high imped-

ance, and present a much lighter load to the driving logic than bi-

polar TTL devices.

The input and I/O pins also have built-in active pull-ups. As a re-

sult, floating inputs will float to a TTL high (logic 1). However,

Lattice Semiconductor recommends that all unused inputs and

tri-stated I/O pins be connected to an adjacent active input, Vcc,

or ground. Doing so will tend to improve noise immunity and

reduce Icc for the device. (See equivalent input and I/O schemat-

ics on the following page.)

Security Cell

A security cell is provided in every GAL22V10 device to prevent

unauthorized copying of the array patterns. Once programmed,

this cell prevents further read access to the functional bits in the

device. This cell can only be erased by re-programming the

device, so the original configuration can never be examined once

this cell is programmed. The Electronic Signature is always avail-

able to the user, regardless of the state of this control cell.

Typical Input Current

0

Latch-Up Protection

GAL22V10 devices are designed with an on-board charge pump

to negatively bias the substrate. The negative bias is of sufficient

magnitude to prevent input undershoots from causing the circuitry

to latch. Additionally, outputs are designed with n-channel pullups

instead of the traditional p-channel pullups to eliminate any pos-

sibility of SCR induced latching.

- 2 0

- 4 0

- 6 0

0

1 . 0

2 . 0

3 . 0

4 . 0

5 . 0

Input Voltage (Volts)

Device Programming

GAL devices are programmed using a Lattice Semiconductor-

approved Logic Programmer, available from a number of manu-

facturers (see the the GAL Development Tools section). Com-

plete programming of the device takes only a few seconds. Eras-

ing of the device is transparent to the user, and is done automati-

cally as part of the programming cycle.

13

Specifications GAL22V10

Power-Up Reset

Vcc (min.)

Vcc

t

su

CLK

t

wl

t

pr

Internal Register

Reset to Logic "0"

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

Device Pin

Reset to Logic "1"

OUTPUT REGISTER

Device Pin

Reset to Logic "0"

ACTIVE HIGH

OUTPUT REGISTER

Circuitry within the GAL22V10 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q out-

puts set low after a specified time (tpr, 1μs MAX). As a result, the

state on the registered output pins (if they are enabled) will be

either high or low on power-up, depending on the programmed

polarity of the output pins. This feature can greatly simplify state

machine design by providing a known state on power-up. The

timing diagram for power-up is shown below. Because of the asyn-

chronous nature of system power-up, some conditions must be

met to guarantee a valid power-up reset of the GAL22V10. First,

the Vcc rise must be monotonic. Second, the clock input must

be at static TTL level as shown in the diagram during power up.

The registers will reset within a maximum of tpr time. As in nor-

mal system operation, avoid clocking the device until all input and

feedback path setup times have been met. The clock must also

meet the minimum pulse width requirements.

Input/Output Equivalent Schematics

Feedback

Vcc

Active Pull-up

Circuit

Active Pull-up

Circuit

(Vref Typical = 3.2V)

Vcc

Tri-State

Control

Vcc

Vref

ESD

Protection

Circuit

Data

Output

ESD

Protection

Circuit

Feedback

(To Input Buffer)

Typical Input

Typical Output

14

Specifications GAL22V10

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.1

RISE

FALL

RISE

FALL

1.05

RISE

FALL

1

0.95

0.9

1

0.95

0.9

1

0.95

0.9

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

Supply Voltage (V)

Normalized Tpd vs Temp

Normalized Tco vs Temp

Normalized Tsu vs Temp

1.3

1.2

1.1

1

1.3

1.2

1.1

1

1.2

1.1

RISE

FALL

RISE

FALL

RISE

FALL

1

0.9

0.8

0.9

-55

0.8

-25

0

25

50

75

100

125

-55

-25

0

25

50

75

100

125

-55

-25

0

25

50

75

100

125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

0

-0.1

-0.2

-0.3

-0.4

RISE

FALL

RISE

FALL

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

12

RISE

FALL

RISE

FALL

8

4

8

4

0

-4

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Loading (pF)

15

Specifications GAL22V10

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

Voh vs Ioh

Vol vs Iol

Voh vs Ioh

3.95

3.85

3.75

3.65

3.55

3.45

3.35

3.25

3.15

4

3

2

1

0

0.6

0.4

0.2

0

0.00

1.00

2.00

3.00

4.00

5.00

0

5

10 15 20 25 30 35 40 45 50 55 60

0

5

10

15

20

25

30

35

40

Ioh(mA)

Iol (mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq

1.2

1.1

1

1.3

1.2

1.1

1

1.2

1.15

1.1

1.05

1

0.9

0.8

0.7

0.9

0.8

0.95

4.5

4.75

5

5.25

5.5

-55

-25

0

25

50

88

100 125

1

15

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Delta Icc vs Vin (1 input)

Input Clamp (Vik)

6

5

0

20

4

3

2

1

0

40

60

80

100

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

-3

-2.5

-2

-1.5

-1

-0.5

1

Vin (V)

Vik (V)

16

Specifications GAL22V10

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.2

1.1

1

1.1

1.05

1

1.1

1.05

1

RISE

FALL

RISE

FALL

RISE

FALL

0.9

0.8

0.95

0.9

0.95

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

Supply Voltage (V)

Normalized Tsu vs Temp

Normalized Tpd vs Temp

Normalized Tco vs Temp

1.3

1.2

1.1

1

1.3

1.2

1.1

1

1.2

1.1

1

RISE

FALL

RISE

FALL

RISE

FALL

0.9

0.8

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

RISE

FALL

RISE

FALL

-1.1

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

12

8

12

8

RISE

FALL

RISE

FALL

4

0

-4

0

-4

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Loading (pF)

17

Specifications GAL22V10

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams

Vol vs Iol

Voh vs Ioh

0.5

0.4

0.3

0.2

0.1

0

4

3

2

1

0

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3

2.9

2.8

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

0.00

1.00

2.00

3.00

4.00

5.00

Ioh (mA)

Iol (mA)

Ioh (mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq

1.15

1.1

1.3

1.2

1.1

1

1.2

1.15

1.1

1.05

1

1.05

1

0.95

0.9

0.8

0.7

0.85

0.95

4.5

4.75

5

5.25

5.5

-55

0

25

100

1

15

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Isb vs Vin (1 input)

10

9

8

7

6

5

4

3

2

1

0

10

20

30

40

50

60

70

80

90

100

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

-2.5

-2

-1.5

-1

-0.5

0

Vin (V)

Vik (V)

18

Specifications GAL22V10

GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.1

1.05

1

1.2

1.1

1

1.15

1.1

1.05

1

RISE

FALL

RISE

FALL

RISE

FALL

0.95

0.9

0.95

0.9

0.8

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

Supply Voltage (V)

Normalized Tsu vs Temp

Normalized Tco vs Temp

Normalized Tpd vs Temp

1.3

1.2

1.1

1

1.3

1.2

1.1

1

1.45

1.35

1.25

1.15

1.05

0.95

0.85

0.75

RISE

FALL

RISE

FALL

RISE

FALL

0.9

0.8

-55 -25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

0

-0.4

-0.8

0

-0.4

-0.8

-1.2

RISE

FALL

RISE

FALL

-1.2

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

20

16

12

8

20

16

12

8

RISE

FALL

RISE

FALL

4

0

-4

-8

-4

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Loading (pF)

19

Specifications GAL22V10

GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams

Vol vs Iol

Voh vs Ioh

0.6

0.4

0.2

0

4.5

4

4.5

4

3.5

3

2.5

2

3.5

3

1.5

1

0.5

0

2.5

0

20

40

60

0.00

1.00

2.00

3.00

4.00

5.00

0

5

10

15

20

25

30

35

40

Ioh (mA)

Iol (mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq

1.2

1.1

1

1.35

1.25

1.15

1.05

0.95

0.85

0.75

1.4

1.3

1.2

1.1

1

0.9

0.8

0.9

4.5

4.75

5

5.25

5.5

-55

-25

0

25

50

88

100 125

1

15

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

0

7

6

5

4

3

2

1

0

10

20

30

40

50

60

70

80

90

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Vik (V)

Vin (V)

20

Specifications GAL2N2oVt1e0s

Revision History

Date

Version

Change Summary

-

22v10_08

22v10_09

22v10_10

22v10_11

22v10_12

Previous Lattice release.

August 2004

July 2006

August 2006

December 2006

Added lead-free package options.

Corrected SOIC pin configuration diagram. Pin 13.

Updated for lead-free package options.

Corrected Icc in the Ordering Part Number section on pages 2-3.

21

型号:	GAL22V10D-15LPN
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	LATTICE SEMICONDUCTOR CORP
零件包装代码：	DIP
包装说明：	LEAD FREE, PLASTIC, DIP-24
针数：	24
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.13
Is Samacsys：	N
架构：	PAL-TYPE
最大时钟频率：	55.5 MHz
JESD-30 代码：	R-PDIP-T24
JESD-609代码：	e3
长度：	31.75 mm
湿度敏感等级：	1
专用输入次数：	11
I/O 线路数量：	10
输入次数：	22
输出次数：	10
产品条款数：	132
端子数量：	24
最高工作温度：	75 °C
最低工作温度：
组织：	11 DEDICATED INPUTS, 10 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP24,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	260
电源：	5 V
可编程逻辑类型：	EE PLD
传播延迟：	15 ns
认证状态：	Not Qualified
座面最大高度：	5.334 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL EXTENDED
端子面层：	Matte Tin (Sn)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.62 mm
Base Number Matches：	1

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