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产品型号GAL26CV12B-15LJ的概述

芯片GAL26CV12B-15LJ的概述 GAL26CV12B-15LJ是一款由Lattice Semiconductor公司设计和制造的可编程逻辑器件（PLD）。此芯片属于GAL（Generic Array Logic）系列产品，通过其可编程的特性，为用户提供灵活的逻辑设计方案。GAL26CV12B-15LJ的主要功能是提供用户可自定义的逻辑组合，满足多种电子电路需求，广泛应用于工业、汽车、通信等领域。芯片GAL26CV12B-15LJ的详细参数 GAL26CV12B-15LJ芯片在参数方面的表现十分优秀。在逻辑性能方面，该设备支持组合逻辑和时序逻辑功能，具有12个输入与8个输出的配置。其最大工作频率为15ns，具有高速的处理能力。此外，芯片的功耗相对较低，与许多同类产品相比，节能效果明显。具体参数如下： - 逻辑门数量：12 - 输入/输出数量：12 输入、8 输出 - 最大工...

产品型号GAL26CV12B-15LJ的Datasheet PDF文件预览

GAL26CV12

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 142.8 MHz

I/CLK

INPUT

I/O/Q

RESET

— 4.5ns Maximum from Clock Input to Data Output

OLMC

— TTL Compatible 16 mA Outputs

— UltraMOS^®Advanced CMOS Technology

I/O/Q

• ACTIVE PULL-UPS ON ALL PINS

• LOW POWER CMOS

— 90 mA Typical Icc

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TWELVE OUTPUT LOGIC MACROCELLS

— Uses Standard 22V10 Macrocells

— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

PRESET

Description

The GAL26CV12, at 7.5 ns maximum propagation delay time,

combines a high performance CMOS process with Electrically

Erasable (E²) floating gate technology to provide the highest

performance 28-pin PLD available on the market. E²technology

offers high speed (<100ms) erase times, providing the ability to

reprogram or reconfigure the device quickly and efficiently.

Pin Configuration

DIP

I/CLK

PLCC

I/O/Q

Expanding upon the industry standard 22V10 architecture, the

GAL26CV12 eliminates the learning curve typically associated with

using a new device architecture. The generic architecture provides

maximum design flexibility by allowing the Output Logic Macrocell

(OLMC) to be configured by the user. The GAL26CV12 OLMC is

fully compatible with the OLMC in standard bipolar and CMOS

22V10 devices.

I/O/Q

GND

I/O/Q

GAL

26CV12

I/O/Q

GND

I/O/Q

Vcc

VCC

GAL26CV12

Top View

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers100% field programmability and functionality

of all GAL products. In addition, 100 erase/write cycles and data

retention in excess of 20 years are specified.

15 I/O/Q

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2000

26cv12_03

Specifications GAL26CV12

GAL26CV12 Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

7.5

4.5

130

GAL26CV12C-7LP

28-Pin Plastic DIP

28-Lead PLCC

GAL26CV12C-7LJ

GAL26CV12B-10LP

GAL26CV12B-10LJ

GAL26CV12B-15LP

GAL26CV12B-15LJ

GAL26CV12B-20LP

GAL26CV12B-20LJ

28-Pin Plastic DIP

28-Lead PLCC

28-Pin Plastic DIP

28-Lead PLCC

28-Pin Plastic DIP

28-Lead PLCC

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

150

GAL26CV12C-10LPI

GAL26CV12C-10LJI

GAL26CV12B-15LPI

GAL26CV12B-15LJI

GAL26CV12B-20LPI

GAL26CV12B-20LJI

28-Pin Plastic DIP

28-Lead PLCC

28-Pin Plastic DIP

28-Lead PLCC

28-Pin Plastic DIP

28-Lead PLCC

Part Number Description

XXXXXXXX XX

X X X

GAL26CV12C Device Name

GAL26CV12B

Grade

Blank = Commercial

I = Industrial

Speed (ns)

L = Low Power Power

Package P = Plastic DIP

J = PLCC

Specifications GAL26CV12

Output Logic Macrocell (OLMC)

The GAL26CV12 has a variable number of product terms per The GAL26CV12 has a product term forAsynchronous Reset (AR)

OLMC. Of the twelve available OLMCs, two OLMCs have access and a product term for Synchronous Preset (SP). These two prod-

to twelve product terms (pins 20 and 22), two have access to ten uct terms are common to all registered OLMCs. TheAsynchronous

product terms (pins 19 and 23), and the other eight OLMCs have Reset sets all registered outputs to zero any time this dedicated

eight product terms each. In addition to the product terms available product term is asserted. The Synchronous Preset sets all registers

for logic, each OLMC has an additional product term dedicated to to a logic one on the rising edge of the next clock pulse after this

output enable control.

product term is asserted.

The output polarity of each OLMC can be individually programmed NOTE: TheAR and SP product terms will force the Q output of the

to be true or inverting, in either combinatorial or registered mode. flip-flop into the same state regardless of the polarity of the output.

This allows each output to be individually configured as either active Therefore, a reset operation, which sets the register output to a zero,

high or active low.

may result in either a high or low at the output pin, depending on

the pin polarity chosen.

A R

4 T O

M U X

C L K

S P

2 T O

M U X

GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)

Output Logic Macrocell Configurations

Each of the Macrocells of the GAL26CV12 has two primary NOTE: In registered mode, the feedback is from the /Q output of

functional modes: registered, and combinatorial I/O. The modes the register, and not from the pin; therefore, a pin defined as

and the output polarity are set by two bits (SO and S1), which are registered is an output only, and cannot be used for dynamic

normally controlled by the logic compiler. Each of these two primary I/O, as can the combinatorial pins.

modes, and the bit settings required to enable them, are described

below and on the the following page.

COMBINATORIAL I/O

In combinatorial mode the pin associated with an individual OLMC

is driven by the output of the sum term gate. Logic polarity of the

REGISTERED

In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the output

OLMC is driven by the Q output of that OLMC’s D-type flip-flop. buffer drive either true (active high) or inverted (active low). Output

Logic polarity of the output signal at the pin may be selected by tri-state control is available as an individual product term for each

specifying that the output buffer drive either true (active high) or output, and may be individually set by the compiler as either “on”

inverted (active low). Output tri-state control is available as an (dedicated output), “off” (dedicated input), or “product term driven”

individual product term for each OLMC, and can therefore be (dynamic I/O). Feedback into theAND array is from the pin side of

defined by a logic equation. The D flip-flop’s /Q output is fed back the output enable buffer. Both polarities (true and inverted) of the

into the AND array, with both the true and complement of the pin are fed back into the AND array.

feedback available as inputs to the AND array.

Specifications GAL26CV12

Registered Mode

A R

C L K

S P

ACTIVE LOW

ACTIVE HIGH

S₀= 0

S₁= 0

S₀= 1

S₁= 0

Combinatorial Mode

ACTIVE LOW

ACTIVE HIGH

S₀= 0

S₁= 1

S₀= 1

S₁= 1

Specifications GAL26CV12

GAL26CV12 Logic Diagram/JEDEC Fuse Map

DIP & PLCC Package Pinouts

ASYNCHRONOUS RESET

(TO ALL REGISTERS)

0000

0052

OLMC

6344

0468

6345

0520

OLMC

0936

6346

6347

0988

OLMC

1404

6348

6349

1456

OLMC

1872

6350

6351

1924

OLMC

6352

2444

6353

2496

OLMC

6354

3120

6355

3172

OLMC

6356

3796

6357

3848

OLMC

6358

4368

6359

4420

OLMC

6360

4836

6361

4888

OLMC

6362

5304

6363

5356

OLMC

6364

5772

6365

5824

OLMC

6366

6240

6367

6292

SYNCHRONOUS PRESET

(TO ALL REGISTERS)

6368, 6369 ... Electronic Signature ... 6430, 6431

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

SpSepceifcicifaictaiotinosnsGGALA2L62C6VC1V21C2

(1)

Absolute Maximum Ratings

Recommended Operating Conditions

Supply voltage V_CC...................................... –0.5 to +7V

Input voltage applied .......................... –2.5 to V_CC+1.0V

Off-state output voltage applied ......... –2.5 to V_CC+1.0V

Storage Temperature ................................ –65 to 150°C

Ambient Temperature with

Commercial Devices:

Ambient Temperature (T_A) ............................. 0 to +75°C

Supply voltage (V_CC)

with Respect to Ground ..................... +4.75 to +5.25V

Power Applied ........................................... –55 to 125°C

Industrial Devices:

1. Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress only ratings and functional operation of the device at

these or at any other conditions above those indicated in the op-

erational sections of this specification is not implied (while pro-

gramming, follow the programming specifications).

Ambient Temperature (T_A) ........................... –40 to 85°C

Supply voltage (V_CC)

with Respect to Ground ......................... +4.5 to +5.5V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.³

MAX. UNITS

VIL

VIH

IIL¹

Input Low Voltage

Vss – 0.5

2.0

—

0.8

Vcc+1

–100

Input High Voltage

Input or I/O Low Leakage Current

0V ≤ VIN ≤ VIL (MAX.)

µA

IIH

Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC

—

VOL

VOH

IOL

Output Low Voltage

IOL = MAX. Vin = VIL or VIH

—

0.5

Output High Voltage

IOH = MAX. Vin = VIL or VIH

2.4

—

Low Level Output Current

High Level Output Current

Output Short Circuit Current

IOH

IOS²

—

–3.2

–130

VCC = 5V VOUT = 0.5V T_A= 25°C

–30

COMMERCIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V ftoggle = 15MHz

L-7

—

130

150

Outputs Open

INDUSTRIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V ftoggle = 15MHz

L-10

Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C.

SpSepceifcicifaictaiotinosnsGGALA2L62C6VC1V21C2

AC Switching Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

COM

-7

IND

-10

TEST

DESCRIPTION

PARAM

UNITS

COND.¹

MIN. MAX.

tpd

tco

tcf²

tsu₁

tsu₂

Input or I/O to Comb. Output

Clock to Output Delay

7.5

4.5

2.5

—

Clock to Feedback Delay

—

2.5

—

Setup Time, Input or Fdbk before Clk ↑

Setup Time, SP before Clock ↑

Hold Time, Input or Fdbk after Clk ↑

—

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

95.2

71.4

MHz

fmax³

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

117.6

142.8

—

105

—

MHz

Maximum Clock Frequency with

No Feedback

twh

twl

—

Clock Pulse Duration, High

3.5

—

7.5

—

Clock Pulse Duration, Low

ten

tdis

tar

Input or I/O to Output Enabled

Input or I/O to Output Disabled

Input or I/O to Asynch. Reset of Reg.

Asynchronous Reset Pulse Duration

Asynch. Reset to Clk↑ Recovery Time

Synch. Preset to Clk ↑ Recovery Time

—

tarw

tarr

tspr

—

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

C_I/O

*Characterized but not 100% tested.

SpSepceifcicifaictaiotinosnsGGALA2L62C6VC1V21B2

(1)

Absolute Maximum Ratings

Recommended Operating Conditions

Supply voltage V_CC...................................... –0.5 to +7V

Input voltage applied .......................... –2.5 to V_CC+1.0V

Off-state output voltage applied ......... –2.5 to V_CC+1.0V

Storage Temperature ................................ –65 to 150°C

Ambient Temperature with

Commercial Devices:

Ambient Temperature (T_A) ............................. 0 to +75°C

Supply voltage (V_CC)

with Respect to Ground ..................... +4.75 to +5.25V

Power Applied ........................................... –55 to 125°C

Industrial Devices:

1. Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress only ratings and functional operation of the device at

these or at any other conditions above those indicated in the op-

erational sections of this specification is not implied (while pro-

gramming, follow the programming specifications).

Ambient Temperature (T_A) ........................... –40 to 85°C

Supply voltage (V_CC)

with Respect to Ground ......................... +4.5 to +5.5V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.³

MAX. UNITS

VIL

VIH

IIL¹

Input Low Voltage

Vss – 0.5

2.0

—

0.8

Vcc+1

–100

Input High Voltage

Input or I/O Low Leakage Current

0V ≤ VIN ≤ VIL (MAX.)

µA

IIH

Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC

—

VOL

VOH

IOL

Output Low Voltage

IOL = MAX. Vin = VIL or VIH

—

0.5

Output High Voltage

IOH = MAX. Vin = VIL or VIH

2.4

—

Low Level Output Current

High Level Output Current

Output Short Circuit Current

IOH

IOS²

—

–3.2

–130

VCC = 5V VOUT = 0.5V T_A= 25°C

–30

COMMERCIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V ftoggle = 15MHz

L-10/-15/-20

L-15/-20

—

130

150

Outputs Open

INDUSTRIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V ftoggle = 15MHz

Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C.

SpSepceifcicifaictaiotinosnsGGALA2L62C6VC1V21B2

AC Switching Characteristics

Over Recommended Operating Conditions

COM / IND

-20

COM

-10

COM / IND

-15

TEST

DESCRIPTION

PARAMETER

UNITS

COND.¹

MIN. MAX.

tpd

tco

tcf²

tsu₁

tsu₂

Input or I/O to Combinatorial Output

Clock to Output Delay

—

Clock to Feedback Delay

—

2.5

—

2.5

—

Setup Time, Input or Feedback before Clock ↑

Setup Time, SP before Clock ↑

Hold Time, Input or Feedback after Clock ↑

—

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

71.4

55.5

41.6

MHz

fmax³

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

105

—

45.4

62.5

—

MHz

Maximum Clock Frequency with

No Feedback

83.3

twh

twl

—

Clock Pulse Duration, High

—

Clock Pulse Duration, Low

ten

tdis

tar

Input or I/O to Output Enabled

Input or I/O to Output Disabled

Input or I/O to Asynchronous Reset of Register

Asynchronous Reset Pulse Duration

Asynchronous Reset to Clock Recovery Time

Synchronous Preset to Clock Recovery Time

tarw

tarr

tspr

—

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

C_I/O

*Characterized but not 100% tested.

Specifications GAL26CV12

Switching Waveforms

INPUT or

I/O FEEDBACK

INPUT or

I/O FEEDBACK

VALID INPUT

s u

VALID INPUT

CLK

COMBINATORIAL

OUTPUT

c o

REGISTERED

OUTPUT

Combinatorial Output

fm a x

(external fdbk)

Registered Output

INPUT or

I/O FEEDBACK

dis

ten

OUTPUT

CLK

max (internal fdbk)

Input or I/O to Output Enable/Disable

cf su

REGISTERED

FEEDBACK

fmax with Feedback

w l

t_{w h}

CLK

fm a x

(w/o fdbk)

Clock Width

INPUT or

I/O FEEDBACK

DRIVING AR

INPUT or

I/O FEEDBACK

DRIVING SP

arw

tspr

CLK

arr

REGISTERED

OU TPUT

REGISTERED

OUTPUT

Synchronous Preset

Asynchronous Reset

Specifications GAL26CV12

fmax Definitions

C L K

CLK

LOGIC

ARRAY

LOGIC

ARR AY

tco

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

CLK

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal

feedback (tcf = 1/fmax - tsu). The value of tcf is

used primarily when calculating the delay from

clocking a register to a combinatorial output

(through registered feedback), as shown above.

For example, the timing from clock to a combi-

natorial output is equal to tcf + tpd.

LOGIC

ARRAY

su + th

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a

clock duty cycle of other than 50%.

Switching Test Conditions

Input Pulse Levels

Input Rise and

Fall Times

GND to 3.0V

1.5ns 10% – 90%

3ns 10% – 90%

+5V

C-7/-10/-15

B-10/-15/-20

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

1.5V

See Figure

FROM OUTPUT (O/Q)

UNDER TEST

TEST POINT

3-state levels are measured 0.5V from steady-state active

level.

C _L*

GAL26CV12 Output Load Conditions (see figure)

Test Condition

R¹

300Ω

∞

390Ω

50pF

5pF

Active High

Active Low

Active High

Active Low

300Ω

∞

*C _LINCLUDES TEST FIXTURE AND PROBE CAPACITANCE

300Ω

5pF

Specifications GAL26CV12

Electronic Signature

Output Register Preload

An electronic signature is provided in every GAL26CV12 device. When testing state machine designs, all possible states and state

It contains 64 bits of reprogrammable memory that can contain transitions must be verified in the design, not just those required

user-defined data. Some uses include user ID codes, revision in normal machine operation. This is because certain events may

numbers, or inventory control. The signature data is always avail- occur during system operation that throw the logic into an illegal

able to the user independent of the state of the security cell.

state (power-up, line voltage glitches, brown-outs, etc.). To test a

design for proper treatment of these conditions, a way must be

provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

Security Cell

A security cell is provided in every GAL26CV12 device to prevent

unauthorized copying of the array patterns. Once programmed,

this cell prevents further read access to the functional bits in the

device. This cell can only be erased by re-programming the de-

vice, so the original configuration can never be examined once this

cell is programmed. The Electronic Signature is always available

to the user, regardless of the state of this control cell.

The GAL26CV12 device includes circuitry that allows each regis-

tered output to be synchronously set either high or low. Thus, any

present state condition can be forced for test sequencing. If nec-

essary, approved GAL programmers capable of executing test

vectors perform output register preload automatically.

Input Buffers

Latch-Up Protection

GAL26CV12 devices are designed with TTL level compatible in-

put buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

logic.

GAL26CV12 devices are designed with an on-board charge pump

to negatively bias the substrate. The negative bias minimizes the

potential for latch-up caused by negative input undershoots. Ad-

ditionally, outputs are designed with n-channel pull-ups instead of

the traditional p-channel pull-ups in order to eliminate latch-up due

to output overshoots.

The input and I/O pins also have built-in active pull-ups. As a result,

floating inputs will float to a TTL high (logic 1). However, Lattice

Semiconductor recommends that all unused inputs and tri-stated

I/O pins be connected to an adjacent active input, Vcc, or ground.

Doing so will tend to improve noise immunity and reduce Icc for the

Device Programming

GAL devices are programmed using a Lattice Semiconductor-

approved Logic Programmer, available from a number of manu-

facturers (see the the GAL Development Tools section). Complete

programming of the device takes only a few seconds. Erasing of

the device is transparent to the user, and is done automatically as

part of the programming cycle.

device.

Typical Input Current

- 2 0

- 4 0

- 6 0

1 . 0

2 . 0

3 . 0

4 . 0

5 . 0

Input Voltage (Volts)

Specifications GAL26CV12

Power-Up Reset

Vcc (min.)

Vcc

CLK

Internal Register

Reset to Logic "0"

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

Device Pin

Reset to Logic "1"

Device Pin

Reset to Logic "0"

ACTIVE HIGH

OUTPUT REGISTER

provide a valid power-up reset of the device. First, the VCC rise must

be monotonic. Second, the clock input must be at static TTL level

as shown in the diagram during power up. The registers will reset

within a maximum of tpr time. As in normal system operation, avoid

clocking the device until all input and feedback path setup times

have been met. The clock must also meet the minimum pulse width

requirements.

Circuitry within the GAL26CV12 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q outputs

set low after a specified time (tpr, 1µs MAX). As a result, the state

on the registered output pins (if they are enabled) will be either high

or low on power-up, depending on the programmed polarity of the

output pins. This feature can greatly simplify state machine design

by providing a known state on power-up. Because of the asynchro-

nous nature of system power-up, some conditions must be met to

Input/Output Equivalent Schematics

Feedback

Vcc

Active Pull-up

Circuit

Active Pull-up

Circuit

(Vref Typical = 3.2V)

Vcc

Tri-State

Control

Vref

Vcc

Vref

ESD

Protection

Circuit

Data

Output

ESD

Protection

Circuit

Feedback

(To Input Buffer)

Typical Input

Typical Output

Specifications GAL26CV12

GAL26CV12C: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.2

1.1

1.2

1.1

1.2

1.1

0.9

0.8

0.9

0.8

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Normalized Tsu vs Temp

Normalized Tpd vs Temp

Normalized Tco vs Temp

1.4

1.3

1.2

1.1

1.3

1.2

1.1

1.3

1.2

1.1

0.9

0.8

0.7

0.9

0.8

0.7

0.9

0.8

0.7

-55

-25

100 125

-55

-25

100 125

-55

-25

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

-0.25

-0.5

-0.25

-0.5

-0.75

-1

-0.75

-1

10 11 12

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

RISE

FALL

RISE

FALL

-2

100

150

200

250

300

100

150

200

250

300

Output Loading (pF)

Specifications GAL26CV12

GAL26CV12C: Typical AC and DC Characteristic Diagrams

Vol vs Iol

Voh vs Ioh

2.5

3.75

3.5

1.5

3.25

0.5

0.00

20.00

40.00

60.00

80.00 100.00

0.00 10.00 20.00 30.00 40.00 50.00 60.00

0.00

1.00

2.00

3.00

4.00

Iol (mA)

Ioh(mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq.

1.3

1.2

1.1

1.3

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

1.2

1.1

0.9

0.8

0.7

0.9

0.8

0.7

4.50

4.75

5.00

5.25

5.50

-55

-25

100 125

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

-2.00

-1.50

-1.00

-0.50

0.00

Vin (V)

Vik (V)

Specifications GAL26CV12

GAL26CV12B: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.2

1.1

1.2

1.1

1.2

1.1

0.9

0.8

0.9

0.8

0.9

0.8

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Normalized Tsu vs Temp

Normalized Tpd vs Temp

Normalized Tco vs Temp

1.4

1.3

1.2

1.1

1.3

1.2

1.1

1.3

1.2

1.1

0.9

0.8

0.7

0.9

0.8

0.7

0.9

0.8

0.7

-55

-25

100 125

-55

-25

100 125

-55

-25

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

10 11 12

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

RISE

FALL

RISE

FALL

-2

100

150

200

250

300

100

150

200

250

300

Output Loading (pF)

Specifications GAL26CV12

GAL26CV12B: Typical AC and DC Characteristic Diagrams

Vol vs Iol

Voh vs Ioh

2.5

4.5

4.25

1.5

3.75

3.5

0.5

0.00

20.00

40.00

60.00

80.00 100.00

0.00 10.00 20.00 30.00 40.00 50.00 60.00

0.00

1.00

2.00

3.00

4.00

Iol (mA)

Ioh(mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq.

1.2

1.1

1.3

1.20

1.10

1.00

0.90

0.80

1.2

1.1

0.9

0.8

0.7

0.9

0.8

4.50

4.75

5.00

5.25

5.50

-55

-25

100 125

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

100

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

-2.00

-1.50

-1.00

-0.50

0.00

Vin (V)

Vik (V)

GAL26CV12B-15LJ相关文章

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GAL26CV12B-15LJ产品参数

型号:	GAL26CV12B-15LJ
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	LATTICE SEMICONDUCTOR CORP
零件包装代码：	QLCC
包装说明：	PLASTIC, LCC-28
针数：	28
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.72
其他特性：	REGISTER PRELOAD; POWER-UP RESET
架构：	PAL-TYPE
最大时钟频率：	55.5 MHz
JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0
长度：	11.5062 mm
湿度敏感等级：	1
专用输入次数：	13
I/O 线路数量：	12
输入次数：	26
输出次数：	12
产品条款数：	122
端子数量：	28
最高工作温度：	75 °C
最低工作温度：
组织：	13 DEDICATED INPUTS, 12 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225
电源：	5 V
可编程逻辑类型：	EE PLD
传播延迟：	15 ns
认证状态：	Not Qualified
座面最大高度：	4.572 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL EXTENDED
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	11.5062 mm
Base Number Matches：	1

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