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GC5328

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GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

Check for Samples: GC5328

1

FEATURES

•

TMS320C6727 DPD Optimization Software

•

Integrated DUC, CFR, and DPD Solution

Supports Direct Interface to TI High-Speed

Data Converters

•

20-MHz Max. Signal Bandwidth, Based on Max.

DPD Clock of 200 Mhz, Fifth-Order Correction

APPLICATIONS

•

DUC: Up to 12 CDMA2000/TDSCDMA, 4

W-CDMA, 2–10 MHz or 1–20 MHz OFDMA

Carriers

•

3 GPP (W-CDMA) Base Stations

3 GPP2 (CDMA2000) Base Stations

WiMAX, WiBRO, and LTE (OFDMA) Base

Stations

Multicarrier Power Amplifiers (MCPAs)

•

CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB

PAR, < 8.5 dB PAR for OFDMA Signals

•

DPD: Short-Term Memory Compensation,

Typical ACLR Improvement > 20 dB

•

GC5328IZER PBGA Package, 23 mm × 23 mm

1.2-V Core, 1.8-V HSTL, 3.3-V I/O

2.5-W Typical Power Consumption

Attenuator

DAC

I/Q

DAC

I/Q

HPA

Modulator

GC5328

BB Data

LPA

0–31.5 dB

LO

DUC-CFR-DPD

Attenuator

ADC

0–31.5 dB

Mixer

'C6727

DSP

Host

Control

Interface

B0278-03

Figure 1. GC5328 System Block Diagram

DESCRIPTION

The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The

GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion

(DPD) block, feedback (FB) block, and capture buffer (CB) blocks.

The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels

are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined

IQ signal. The DUC provides three stages of interpolation and a complex mixer. There are two DUC blocks. The

output from the DUC blocks is combined in the sum chain. Each of the 1 to 12 DUC channels can be summed,

and the composite signal can be scaled.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

GC5328

SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

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The CFR block has four serial stages of peak detection and cancellation. The CFR block cancellation filter can

be programmed as real or complex. The CFR peak-reduced output is routed to the Farrow resampler. The

Farrow resampler resamples the CFR output to the DPD clock rate. The Farrow resampler block also has a

complex mixer for composite carrier frequency offset.

The DPD subsystem has a circular limiter, nonlinear DPD correction, and a transmit equalizer. The DPD

correction can reduce the follow-on circuitry distortion products. The DPD output is sent to the BUC. The BUC

provides a post-DPD interpolation, and also provides a complex mixer for frequency offset. The DAC interface

converts the BUC signal output to the interleaved IQ or parallel IQ output signals for the DAC5682Z or DAC5688.

The CB block captures the selected internal reference signal, and the feedback block in two up to 4K capture

buffers. The signal capture can be based on an externally timed event (standard capture buffer), delay after a

timed event, or signal statistics (smart capture buffer). Normally the DPD input and feedback output are selected.

The capture buffers are stored and read by the microprocessor.

The FB block receives the LVDS ADC information and performs signal processing to downconvert the received

signal to 0IF. The FB block also has a feedback-path receive equalizer.

TCK

TRST

TI

TMS

RESETB SYNC SYNC INT UPDATA UPADDR OEB RDB WRB CEB

OUT

TD

16

4

3

10

GC5328

NarrowBand DUC

MPU Interface

JTAG

Medium

Band NarrowBand DUC

DUC

Pilot

Insertion

Wide

Band

DUC

NarrowBand DUC

Gain

NarrowBand DUC

Medium

Band NarrowBand DUC

BBin

DUC

Pilot

Insertion

NarrowBand DUC

16

1

+

CFR

BBFR

NarrowBand DUC

Medium

Band NarrowBand DUC

AntCal

Insertion

DUC

Wide

Band

DUC

NarrowBand DUC

Power

Meter

NarrowBand DUC

Medium

Band NarrowBand DUC

DUC

BBclk

NarrowBand DUC

BB

PLL

Fractional

Resampler

ADCin

(LVDS)

DPDclk

DPD

PLL

ADCin 16

(LVDS)

Feedback

Equalizer

ADC

Interface

Feedback Mixer

and NL Correction

Real to Complex

SYNC

2

Circular

Limiter

To Capture

Buffer

To Capture

Buffer

To Capture

Buffer

MAGout

Envelope

Interface

16

MAGclk

DACout

38

DAC

Interface

Transmit

Equalizer

Bulk Interpolation

+ Mixer

DPD

Capture Buffers

DUCs in

1-Chn Mode

DUCs in

2-Chn Mode

DUCs in

6-Chn Mode

Active Only in Dual

Antenna Mode

BB Clock Domain

DPD Clock Domain

B0279-03

Figure 2. GC5328 Functional Block Diagram

2

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AVAILABLE OPTIONS

PACKAGED DEVICE

T_C

484-Ball PBGA Package, 23 mm × 23 mm

–40°C to 85°C

GC5328IZER

REFERENCES

1. GC532x Architecture Datasheet (NDA, obtain through local TI field application engineer)

2. GC5328 EVM User Guide, Schematic Diagram (obtain through local TI field application engineer)

3. GC5325 EVM User Guide, Schematic Diagram TI Web site under GC5325

4. GC5322 DPD Host Interface Guide (obtain through local TI Field Application Engineer)

5. GC5328 configuration (obtain through local TI Field Application Engineer)

6. DSP – TMS320C672x DSP Universal Host Port Interface Reference Guide (SPRU719)

7. DSP – TMS320C672x DSP External Memory Interface (EMIF) User's Guide (SPRU711)

GC5328 INTRODUCTION

The GC5328 is a flexible transmit sector processor that includes a digital upconverter (DUC) block, a crest factor

reduction (CFR) block, and a digital predistortion (DPD) block and its associated feedback chain. The GC5328

processes composite input bandwidths of up to 20 MHz and processes DPD expansion bandwidths of up to 100

MHz. By reducing both the peak-to-average ratio (PAR) of the input signals using the CFR block and linearizing

the power amplifier (PA) using the DPD block, the GC5328 reduces the costs of multicarrier PAs (MCPA) for

wireless infrastructure applications. The GC5328 applies CFR and DPD while a separate microprocessor (a

Texas Instruments TMS320C6727 DSP) is used to optimize performance levels and maintain target PA

performance levels.

By including the GC5328 in their system architecture, manufacturers of BTS equipment can realize significant

savings on power amplifier bill of materials (BOM) and overall operational costs due to the PA efficiency

improvement. The GC5328 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at

PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB or more. The GC5328 integrates

easily into the transmit signal chain between baseband processors (such as the Texas Instruments

TMS320C64x™ DSP family) and TI high-performance data converters.

A typical GC5328 system application would include the following transmit-chain components:

•

TMS320C6727B digital signal processor (DSP)

DAC5682 16-bit, 1-Gsps DAC; DAC5688 16-bit, 800-Msps DAC (transmit path)

CDCM7005, CDCE72010 clock generator

TRF3761 integrated VCO/PLL synthesizer

TRF3703 quadrature modulator

ADS6149 14-bit, 250-Msps ADC or ADS5517 11-bit 200-Msps (feedback path)

AMC7823 analog monitoring and control circuit with GPIO and SPI

BASEBAND INTERFACE

The GC5328 baseband interface block accepts baseband signals over an interleaved parallel interface at a data

rate of up to 70 MHz. The input interface supports up to 12 separate baseband carriers. The baseband interface

sends the interleaved IQ data to the DUC, or in DUC bypass to the sum chain, with up to 35-Mhz composite BW.

The baseband interface has 18-bit data (top16) BBData[15.0], BBFrame, and two additional (bottom two data)

MFIO(18,19).

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BASEBAND CLOCK (CMOS)

LOW JITTER

Customer LOGIC

BBCLK

GC532x

BBCLK

BBFR

START of MUX-FRAME

BBDATA[17:2]

START_FRAME

TIME

DIVISON

MULTIPLEXED

BASEBAND

DATA

BBDATA[15:0]

MFIO[19:18]

BBDATA[1:0]

TX SYNC REFERENCE

TX SYNC 2 REFERENCE

TX SYNC

REFERENCE

SYNC A

SYNC B

SYNC C

TX SYNC 2

REFERENCE

DGND

B0370-01

Figure 3. Baseband and Sync Interface to GC5328

BASEBAND CLOCK INPUT

The baseband clock input is a CMOS, low-jitter clock.

GAIN/PILOT INSERTION/AntCal INSERTION/POWER METER

Baseband gain can be applied on a per-carrier basis to control the individual channel power accurately through

the system. A UMTS pilot sequence at a programmable gain can be added for antenna calibration. Each

individual baseband channel has an integrated I²+ Q²power accumulator. The baseband power meters have a

common integration counter and interval counter for all channels. The GPP block has an IPDL detection and

control section to select one of four CFR memories when IPDL autoselection is used. Normally, IPDL 0 is

manually selected.

DIGITAL UPCONVERTERS (DUCs)

The GC5328 DUC block has interpolation filters, programmable delays, and complex mixers for each channel.

There are two DUC blocks within the GC5328. The sum chain after the DUC channel combines the DUC channel

streams or the bypass stream and sends the data to the CFR block. Each DUC can operate in one wide, two

medium, or six CDMA channels. Each DUC has a PFIR for spectral shaping, a CFIR for interpolation and image

rejection, and a bulk interpolation CIC.

The 2 DUCs can support:

•

(6 channel/DUC mode) up to 12 – 1.23(8) Mhz CDMA, 1xEVDO, or TDSCDMA carriers

(2 channel/DUC mode) up to 4 – WCDMA or LTE-5 carriers

(1 channel/DUC mode) up to 2 – Wibro, Wimax, LTE 10 carriers

(1 channel/DUC mode) 1 – Wimax or LTE20 carrier

Users can specify the filter characteristics of the DUC. The filters are the programmable finite impulse response

(PFIR), compensating finite impulse response (CFIR), and cascade integrator comb (CIC) filters. Users can also

specify the center frequencies of each carrier with a resolution of 0.25 mHz. Additional controls available in the

DUCs include bulk and fractional-time delay adjustments, phase adjustments, and equalization. The maximum

DUC output bandwidth is 40 MHz.

4

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CREST FACTOR REDUCTION (CFR)

The GC5328 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals. There

are four peak detection cancellation sections in series in the CFR block. Each stage compares the estimated

peak at the stage input with the target, and subtracts a scaled cancellation peak from the signal. There are 24

cancellers pooled among the four stages. The CFR interpolation filter must have at least 1.6× bandwidth, typical

is 2× BBClock to signal bandwidth.

There are four canceller memories and an update shadow memory that can be used for the auto-IPDL UMTS

select cancellation filter. The shadow memory allows the user to update one of the four filter banks during

operation. The CFR block has a composite RMS meter that can select the CFR input or output for monitoring.

The CFR block for WCDMA reduces TM1, TM3 signals for four adjacent carriers to 6.5 db PAR within the 3GPP

limit. The Wimax 10 reduction for two adjacent carriers is to 8.5 db PAR. TDSCDMA and CDMA performance is

limited by the carrier allocations and carrier coding.The CFR processing complex BW is limited to 62.5% of the

baseband clock rate.

FRACTIONAL FARROW RESAMPLER (FR)

The fractional resampler block takes the peak-reduced composite signals from CFR and resamples this through

fractional interpolation to the DPD processing rate. The user-programmable Farrow resampler supports

upsampling rates from 1× to 64×, with 16-bit precision on the interpolation ratio. After the fractional interpolation,

a complex mixer is available to provide a composite carrier IF offset frequency. A peak I or Q monitor is

provided.

DIGITAL PREDISTORTION (DPD)

The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and

lengths of PA memory effects. The circular hard limiter provides a circular clipper that limits the

magnitude-squared value to –6 dbFS. This is optimized for hardware, and for the allowed gain expansion in the

nonlinear DPD correction.

The DPD has an RMS power meter, and a peak I or Q monitor.

The predistortion is performed for the nonlinear correction in the DPD section. The linear correction is performed

in the Tx equalizer. The predistortion correction terms are computed by an external processor (TMS320C6727

DSP) based on capture buffer information and the DPD software.

The DSP sets up the condition for collecting capture buffer data, retrieves the captured data over the EMIF bus,

and then performs calculations to compute the error and corrections to be used for the transmit path.

The host interface controls the mode of operation of the software in the TI DSP. TI provides a base delivery of

'C6727 software to GC5328 customers that achieves a typical ACLR improvement of 20 dB or more when

compared to a PA without DPD.

DPD CLOCK INPUT

The DPD clock input is an LVDS, low-jitter clock.

BULK UPCONVERTER (BUC)

The bulk upconverter block can interpolate the DPD block output by 1×, 1.5×, 2×, or 3× with a complex output.

The BUC interpolation blocks of 2 and 1.5 can provide 1×, 2×, or 3× interpolation for complex signals. The 1.5×

interpolation after DPD is performed by interpolating by 3 in the BUC and decimating by 2 in the OFMT block.

The BUC mixer can translate the composite IQ predistorted Tx output if the BUC Interpolation is > 1. Note: the

BUC interpolation of 1, 1.5, or 2 is recommended.

OUTPUT FORMATTER AND DAC INTERFACE (OFMT)

The output format and DAC interface presents the GC5328 output in the proper format for the different output

interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The two output

interfaces supported for the GC5328 are:

•

DAC5682 interleaved IQ

DAC5688 parallel IQ or interleaved IQ

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GC532x

DAC5682Z

DPD Clock

DAC Clock

ExtTerm⁽¹⁾

CLKIN, CLKINC

DataClock

TX21, TX20

DCLK, DCLKC

ExtPullup⁽²⁾

Differential Data

TX[]

(See HW Data Sheet)

D[15:0]P, D[15:0]N

SYNCP, SYNCN

ExtPullup/

PullDown

B0371-01

(1) ExtTerm – see DAC data sheet.

(2) ExtPullup, 500 Ω to 1.8 V, only required when DAC Data Clock > 337 MHz

Figure 4. GC5328 to DAC5682Z Interface

GC532x

DAC5688

DPD Clock

DataClock

DAC Clock

ExtTerm⁽¹⁾

CLKIN, CLKINC

TX21, TX20

DCLK, DCLKC

ExtTerm1⁽²⁾

Single-Ended

1.8-V CMOS

TX[] - DACI[]

(See HW Data Sheet)

DACA[15:0]

DACB[15:0]

TXENABLE

Single-Ended

1.8-V CMOS

TX[] - DACQ[]

(See HW Data Sheet)

Single-Ended

1.8-V CMOS

TX18

B0372-01

(1) ExtTerm – see DAC data sheet.

(2) ExtTerm1 – tester uses 50 Ω to 0.9 V for termination.

Figure 5. GC5328 to DAC5688 Interface

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FEEDBACK PATH (FB)

The feedback path has two LVDS input ports. The A port is preferred (it has better timing). The external ADC

Input is converted or processed to generate a complex signal. The feedback equalizer has eight complex taps as

a receive equalizer. The feedback path has a mixer to translate the complex IF to the 0IF reference. The ADC

feedback rate is at the same rate as the DPD clock (f_S). The typical feedback is f_S/4, f_S3/4 (m), or f_S5/4 IF. The

feedback equalizer can provide (m) inverted spectral output, if needed.

The FB complex mixer translates the frequency of the complex input signal to 0IF. The feedback path has the

capability for nonlinear correction with a lookup table. TI ADCs that connect to the feedback path are the SDR

type ADS5444, DDR type ADS5445 (6149, 5517), DDR with reversed data phase ADSC217. The ADC feedback

path has modified connections for shared feedback path operation (see GC5325 schematic, User's Guide, in

References ). The GC5328 simplifies timing by providing a FIFO for each ADC port.

NOTE

There are eight LVDS data lanes and 1 LVDS clock lane. If the ADC has < 8 LVDS

data lanes the MSB of the ADC is connected to LVDS lane 7 (MSB) of the A feedback

port.

ADC

GC532x

MSB ALigned

ADC DDR Data

FB[17:2]

(See HW Data Sheet)

ADC[7P, 7N, 0P, 0N]

DDR Clock

ADC_OutClkP, N

FB[1:0]

B0373-01

Figure 6. LVDS DDR ADC to GC5328 FB Interface

MICROPROCESSOR (MPU) INTERFACE

The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in

asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB,

and CEB control signals. The CEB and OEB signals to the GC5328 require additional logic outside the

TMS320C6727B; see Table 1.

Table 1. EMIF to GC5328 Microprocessor Interface

6727 DSP EMIF

EM_D[15.0]

GC5328

UPDATA[15.0]

UPADDR[9.1]

UPADDR[0]

CEB

NOTES

EM_A[8.0]

EM_BA[1]

EM_CS2

EM_RWB

EM_WEB

EM_OEB

AXRO[7]

Note: DSP HD[22.20] are used for logic for multiple chip-select, inverted outputs.

Invert RWB send to OEB

OEB

WRB

RDB

Interrupt

Note: DSP [HD22.20] can also be used with a multiplexer to select GC5328 interrupt.

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Note: One DSP is

HOST UHPI

INTERFACE

shared With

GC532xs

EMIF Addr

Cntl SDRAM

Multiplex

Address

Half Data

UHPI

SDRAM

EMIF Data

r

e

s

DSP RST

TI6727

BOOTMODE

DSP

UPDATA[]

To/From

Other GC5322

EMIF Addr

Cntl GC5322

DSP JTAG

UPADDRESS[]

and CNTL CS2-2

Inv

RDB, CS2[]

INTROUT

First GC532x

INTROUT(2)

GPIO

Ant

SelCode

UPDATA[]

INTROUT

UPADDRESS[]

and CNTL

CS2-1

B0374-01

Figure 7. 6727 DSP to GC5328 EMIF Interface

CAPTURE BUFFERS (SCB)

The GC5328 has two capture buffers of 4096 complex words. The capture buffers are normally used to capture

the Tx reference signal and the feedback output signal. Capture buffer A can capture:

•

The TX reference from the DPD after the circular hard limiter

The feedback output; this represents the waveform as seen by the PA.

The error output

Testbus(31:16)

QRD error output

Capture buffer B can capture:

•

The TX reference from the DPD after the circular hard limiter

The feedback output; this represents the waveform as seen by the PA.

The error output

Testbus(15:0)

Standard capture mode – The capture buffers can be armed to collect the 4K complex samples after a

programmable delay following a sync event.

Smart capture mode – There are two trigger conditions that combine the number of samples greater than a

threshold; these are used to find a number of peak events while the transmit signal is above a threshold. In this

case, the magnitude and magnitude-squared of the signal are compared against a threshold and counted. If the

capture buffer finds the trigger condition, the capture logic captures the programmed capture-buffer depth after

the trigger. This is a combination of DSP software and the GC5328 hardware.

NOTE

Capture buffer A has a special mode to source data for diagnostic testing.

The DSP host-interface software has a function to select and get capture-buffer data.

The complex data is then passed from the GC5328 to the EMIF bus, to the DSP, and

back to the host processor.

The DSP host software has a signal-power monitoring function. This uses the

capture-buffer data to perform special monitoring, power measurement, and error

measurements.

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There are special DSP software PA protection modes that use the capture buffer to

determine the DPD correction applied to the signal, the error between the DPD

reference input and the feedback signal. The capture buffers are also used in the

initial bulk delay and fractional delay alignment.

INPUT SYNCS AND OUTPUT SYNC

The GC5328 features multiple user-programmable input syncs. There are three syncs sampled with the BBClock,

(A, B, and C), and the Sync D,DC as an LVDS sync sampled by the DPD clock. Internally, the GC5328 can also

generate timed and software-controlled syncs. The sync A input is required for the GC5328 hardware to initialize.

It should ideally be the start of the frame or frame downlink. The output sync is a test signal used for debugging.

The input syncs can be used to trigger:

•

Power measurements

DUC channel delay, dither, and mixer-phase alignment

Initializing/loading the DUC, feedback, equalizer, LUTs, etc.

Feedback path tuner alignment

Capturing and sourcing of data through SCBs

NOTE

The sync A external synchronization should match the customer Tx frame (total Tx

period – i.e., 5 ms).

See the baseband interface figure, these synchronization signals must meet the

timing of the BBClk.

POWER METERS AND PEAK I–or–Q MONITORS

There are three integrated I²+ Q²power meters in the GC5328:

•

GPP – each baseband input channel

CFR – the CFR input or output, and which antenna stream (0, 1)

DPD – the input to the DPD nonlinear correction after the DPDL gain, and which antenna stream (0, 1)

There are several peak I or Q monitors within the GC5328.

•

FRW– The resampled combined IQ interleaved input to the DPD

DPD – The input to the DPD nonlinear correction after the DPDL gain

DPD – After the nonlinear correction in DPD, and separately after the linear correction in DPD

FDBK – There is a peak monitor at the output of the feedback path.

NOTE

The DSP host software has a HW POWER meter setup and Get(Monitor) function to

configure and get data from the integrated I²+Q²values.

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PIN ASSIGNMENT AND DESCRIPTIONS

ZER Package

(Top View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

UP

ADDR ADDR ADDR ADDR

UP

DATA0

UP UP

DATA3 DATA6

UP

DATA9 DATA12 DATA15

UP

22

VSS

RDB

VSS

VPP1

VSS1 VSS

VSS

UP

ADDR ADDR ADDR

UP

DATA1

UP

DATA7

UP

TEST

MODE

21 VSS

VSS

BB1

BB4

BB8

VSS

BB2

BB5

BB9

VSS

BB6

VSS

WRB CEB

VSS

VDD

VPP1

DATA4

VSS

DATA10 DATA13

UP UP

ADDR ADDR ADDR SHV

UP

VDD

UP

VDD

UP

MVV

DD2

MVV INTER-

20

19

18

BB0

BB3

BB7

OEB

TDO

TCK

DATA2 SHV DATA5 SHV DATA8 DATA11 DATA14

SS2

RUPT

VDD

SHV

VDD

SHV

VDD

VPP

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

TDI

VDD

SHV

VDD

SHV

BB10 VDD

VDD VDD1 VDD

VDD

TRSTB TMS

VDD

SHV

VDD

SHV

VDD

SHV

17 BB11 BB12 BB13 BB14 VDD

VDD

VSS

VDD

VSS

VDD

VSS

VDD TX37 TX36 TX35 TX34

VDD TX33 TX32 TX31 TX30

VDD TX29 TX28 TX27 TX26

VDD TX25 TX24 TX23 TX22

16 BB15 BBFR BBCLK VDD

VDD

VSS

VDD

VSS

VDD

VSS

SYNC SYNC SYNC SYNC VDD

OUT

VHST

LHV

15

C

B

A

SHV

VDD

SHV

VHST

LHV

14 VSSA1 VDDA1 VDD

VSS

VDD

SHV

VHST

LHV

DAC

13 FB34 FB35 FB32 FB33

12 FB30 FB31 FB28 FB29

VDD

TX21 TX20

REFN REFP

VDD

SHV

VHST

LHV

VSS VSS1 VSS

VSS

VSS TX19 TX18

VDD

VHST

LHV

11 FB27 FB26 VDD

VDD

VSS

VDD TX14 TX15 TX16 TX17

VDD TX10 TX11 TX12 TX13

SHV1

VDD

SHV

VHST

LHV

10 FB25 FB24 FB23 FB22

VSS VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS

VDD

SHV

VHST

LHV

9

8

7

6

5

4

3

2

1

FB21 FB20 FB19 FB18

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

TX6

TX2

TX7

TX3

TX8

TX4

TX9

TX5

ADC

VDD

VHST

LHV

FB17 FB16

IREF VREF SHV

FB15 FB14 FB13 FB12 VDD

VDD

VDD VDDA TX0

TX1

VDD

SHV

VDD

SHV

VDD

SHV

VDD

FB11

FB9

FB4

FB0

VSS

F10

FB8

FB5

FB1

VSS

VDD

FB7

FB2

VDD

FB6

FB3

VDD

VSS

VSSA

SHV

VDD

SHV

DPD

CLK CLKC

DPD SYNC SYNC

DC

VDD

D

VDD

SHV

VDD

SHV

DPD

VDD

VSS

IREF VREF

MFIO MFIO

0

MFIO VDD MFIO MFIO VDD MFIO MFIO MFIO VDD MFIO MFIO

SHV 10 13 SHV 18 21 24 SHV 29 32

RESET

B

VSS

1

5

MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO

9

VSS

3

4

7

12

15

17

20

23

26

28

31

MFIO

2

MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO

11 14 16 19 22 25 27 30 33

VSS

VPP

6

8

= Baseband Input

= Signal Interface

= Miscellaneous

= Power and Biasing

= JTAG Interface

= Microprocessor Interface

P0107-01

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PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

MICROPROCESSOR INTERFACE

OEB

K20

K21

K22

J21

I

Output enable(inv)

Chip enable(inv)

CEB

I

RDB

Read strobe (inv)

WRB

I

Write strobe(inv)

UPADDR[9:0]

UPDATA[15:10]

UPDATA[9:0]

INTERRUPT

J22 ,H20, H21, H22, G20, G21, G22, F20, F21, F22

V22, U20, U21, U22, T20, T21

I

Microprocessor address

Microprocessor data

Microprocessor interrupt

I/O

O

T22, R20, R21, P22, N20, N21, N22, L20, L21, L22

AA20

POWER AND BIASING

VDD Y19, W19, W7, V18, V17, V16, V15, V14, V13, V12,

PWR 1.2-V supply

V11, V10, V9, V8, V7, V6, V5, V4, U19, U18, U17, U16,

U7, U6, U5, U4, T19, T18, T16, T7, T5, T4, R19, R18,

R17, R16, R7, R6, R5, R4, P19, P18, P17, P16, P7, P6,

P5, P4, N19, N18, N17, N16, N7, N6, N5, N4, M19, M18,

M17, M16,M7, M6, M5, M4, L19, L16, L7, L4, K19, K18,

K17, K16, K7, K6, K5, K4, J19, J18, J17, J16, J7, J6, J5,

J4, H19, H18, H17, H16, H7, H6, H5, H4, G19, G18,

G16, G7, G5, G4, F19, F18, F17, F16, F15, F14, F13,

F12, F11, F10, F9, F8, F7, F6, F5, F4, E18, E17, E16,

E7, E6, E5, D16, D11, D6, C14, C11, C6

VSS

AB22, AB4, AB3, AB2, AB1, AA22, AA21, AA3, AA2,

AA1, Y22, Y21, Y12, Y6, Y3, Y2, Y1, W22, W21, W18,

W12, W6, W2, W1, V21, V20, V3, V2, T15, T14, T13,

T12, T11, T10, T9, T8, R15, R14, R13, R12, R11, R10,

R9, R8, P15, P14, P13, P12, P11, P10, P9, P8, N15,

N14, N13, N12, N11, N10, N9, N8, M22, M21, M15,

M14, M13, M12, M11, M10, M9, M8, L15, L14, L13, L12,

L11, L10, L9, L8, K15, K14, K13, K12, K11, K10, K9, K8,

J15, J14, J13, J12, J11, J10, J9, J8, H15, H14, H13,

H12, H11, H10, H9, H8, G15, G14, G13, G12, G11,

G10, G9, G8, E22, E21, E20, E3, E2, E1, D22, D21,

D20, D14, D2, D1, C22, C21, C2, C1, B22, B21, B2, B1,

A22, A21, A2, A1

PWR Ground

MVDD2

W20

1.2-V monitor, no connect

GND monitor, no connect

PWR 1.8-V supply

MVSS2

Y20

VHSTLHV

VDDSHV

U15, U14, U13, U12, U11, U10, U9, U8

AA6, Y18, W4, V19, T17, T6, R3, P20, M20, L18, L17,

L6, L5, L3, J20, H3, G17, G6, E19, E15, E14, E13, E12,

E11, E10, E9, E8, E4

PWR 3.3-V supply

VDDA

Y7

PWR 1.2-V supply (requires filtering)

PWR Ground (requires filtering)

PWR 1.2-V supply (requires filtering)

PWR Ground (requires filtering)

PWR 1.2-V supply

VSSA

AB6

B14

A14

G1, F3

R22, P21

Y4

VDDA1

VSSA1

VPP

VPP1

PWR 1.2-V supply

DPDIREF

DPDVREF

DACREFP

DACREFN

ADCIREF

ADCVREF

BASEBAND INPUT

BB[15:10]

PWR DPD bias, 1 kΩ to VSS

PWR DPD bias to VDD

AA4

Y13

W13

C8

PWR DAC bias, 50 Ω to VSS

PWR DAC bias, 50 Ω to VDDS

PWR ADC bias, 1 kΩ to VSS

PWR ADC bias to VDD

D8

A16, D17, C17, B17, A17, D18

I

Baseband input signal

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PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NAME

BB[9:0]

NO.

C18, B18, A18, D19, C19, B19, A19, C20, B20, A20

I

Baseband input signal

Baseband input clock

BBCLK

C16

B16

BBFR

Baseband frame for sample and channel timing

MISCELLANEOUS

RESETB

TESTMODE

SYNCA

W3

I

Chip reset (active-low)

AB21

C15

B15

A15

AA5

AB5

D15

W5

Tie to GND

I

Programmable general-purpose sync

DPD-purpose sync

SYNCB

I

SYNCC

I

SYNCD

I

SYNCDC

SYNCOUT

DPDCLK

DPDCLKC

JTAG INTERFACE

TCK

I

Complementary DPD-purpose sync

Programmable general-purpose output sync

Clock to DPD

O

I

Y5

I

Complementary clock to DPD

AB19

AA19

AB20

AA18

AB18

I

JTAG clock

TDI

JTAG data in

TDO

O

I

JTAG data out

TRSTB

JTAG reset (active-low)

JTAG mode select

TMS

I

SIGNAL INTERFACE (Tx-DAC, FB-ADC, see next section for Data Converter Connections)

TX[37:30]

TX[29:20]

W17, Y17, AA17, AB17, W16, Y16, AA16, AB16

O

Transmit to DAC(s)

W15, Y15, AA15, AB15, W14, Y14, AA14, AB14, AA13,

AB13

TX[19:10]

AA12, AB12, AB11, AA11, Y11, W11, AB10, AA10, Y10,

W10

O

Transmit to DAC(s)

TX[9:0]

AB9, AA9, Y9, W9, AB8, AA8, Y8, W8, AB7, AA7

B13, A13, D13, C13, B12, A12

O

I

Transmit to DAC(s)

FB[35:30]

FB[29:20]

FB[19:10]

FB[9:0]

Feedback from ADC(s)

D12, C12, A11, B11, A10, B10, C10, D10, A9, B9

C9, D9, A8, B8, A7, B7, C7, D7, A6, B6

A5, B5, C5, D5, B4, A4, D4, C4, B3, A3

V1, U3, U2, U1

I

Feedback from ADC(s)

I

Feedback from ADC(s)

I

Feedback from ADC(s)

MFIO[33:0]

MFIO[29:20]

MFIO[19:10]

MFIO[9:0]

I/O

Multifunction input-output interface

T3, T2 T1, R2, R1, P3, P2, P1, N3, N2

N1, M3, M2, M1, L2, L1, K3, K2, K1, J3

J2, J1, H2, H1, G3, G2, F2, F1, D3, C3

SPECIAL POWER-SUPPLY REQUIREMENTS FOR VDDA1, VSSA1, VDDA2, VSSA2

The two PLLs require an analog supply. Each pair (VDDA1, VSSA1) requires a separate filter. These can be

generated by filtering the core digital supply (VDD). A representative filter is shown in Figure 8. The filters should

be located as close as reasonable to their respective pins (especially the bypass capacitors). The ferrite beads

should be series 50R (similar to Murata P/N: BLM31P500SPT; description: IND FB BLM31P500SPT 50R 1206).

In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required

range. The series resistor assures this condition is met.

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10 W

VDD1

VSS1

VDDA or VDDA1

0.01 mF

1 mF

VSSA or VSSA1

S0315-02

Figure 8. Recommended Filter for VDDA, VDDA1 Power

TX OUTPUT TO DAC5682Z AND DAC5688

The earlier figures show the GC5328 to DAC data, sync, and clock signals. These tables list the specific GC5328

to DAC TX connections.

Table 2. GC5328 TX (Single-Channel Single-Ended HSTL – DAC5688)

PIN NAME

DACI[15:10]

DACI[9:0]

PIN NUMBER

I/O

O

DESCRIPTION

TX15, TX14, TX11, TX10, TX7, TX6

DAC-I output

TX3, TX2, TX1, TX0, TX4, TX5, TX8, TX9, TX12,

TX13

O

DACQ[15:10]

DACQ[9:0]

TX24, TX25, TX28, TX29, TX32, TX33

O

DAC-Q output

TX36, TX37, TX35, TX34, TX31, TX30, TX27,

TX26, TX23, TX22

DACCLK

TX21

TX20

TX18

O

Clock to DAC

DACCLKC

DACSYNC

Cmplementary clock to DAC

Output data sync

Table 3. GC5328 TX (Single Channel Differential HSTL – DAC5682Z)

PIN NAME

DAC[15:10]P

DAC[9:0]N

PIN NUMBER

I/O

O

DESCRIPTION

TX10, TX6, TX2, TX0, TX4, TX8

DAC positive output

DAC negative output

TX12, TX16, TX23, TX27, TX31, TX35, TX32,

TX36, TX29, TX25

O

DAC[15:10]N

DAC[9:0]N

TX11, TX7, TX3, TX1, TX5, TX9,

O

DAC negative output

TX13, TX17, TX22, TX26, TX30, TX34, TX33,

TX37, TX28, TX24

DACCLK

TX21

TX20

TX14

TX15

O

Clock to DAC

DACCLKC

DACSYNCP

DACSYNCN

Complementary clock to DAC

Positive output data sync

Negative output data sync

FB INPUT FROM LVDS ADC

Figure 6 shows the ADC data and clock signals to the GC5328. These tables list the specific ADC-to-GC5328 FB

connections. There are two feedback (FB) ports, A and B. Port A has faster timing and is preferred. There are

several ADC styles:

•

LVDS DDR – ADS5545 (ADS61x9, ADS5517)

LVDS DDR – ADS62C17 – reversed data alignment (same connections as ADS5545)

LVDS SDR – ADS5544

ADCs are typically connected to the GC5328 so the MSB of the ADC is connected to FB port A MSB. The lower

bit numbers follow until the ADC bits are all connected. Any remaining lower-order bits on the FB port should be

terminated with resistors, P connection to GND, N connection to 1.8 V as a logic 0. See the GC5325 schematic

listed under References for an example.

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NOTE

There are special connections for shared-feedback ADCs between GC5328s. See the

GC5325 schematic diagram for the shared feedback connection to (2) GC5328.

Table 4. Single LVDS SDR ADC to FB Ports A and B

PIN NAME

ADC[15:10]P FB2, FB4, FB6, FB8, FB10, FB12

DAC[9:0]P FB14, FB16, FB20, FB22, FB24, FB26, FB28, FB30,

FB32, FB34

ADC[15:10]N FB3, FB5, FB7, FB9, FB11, FB13

PIN NUMBER

I/O

DESCRIPTION

ADC positive feedback from PA output

ADC negative feedback from PA output

I

ADC negative feedback from PA output

ADC[9:0]N

FB15, FB17, FB21, FB23, FB25, FB27, FB29, FB31,

FB33, FB35

ADCCLK

FB0

I

Clock from ADC

ADCCLKC

FB1

Complementary clock from ADC

Table 5. Single LVDS DDR ADC to FB Port A (Preferred)

PIN NAME

ADCA[7:0]P

ADC[9:0]P

PIN NUMBER

I/O

DESCRIPTION

ADC-A positive feedback from PA output

ADC-A negative feedback from PA output

Clock from ADC-A

FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16

I

FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17

ADCACLK

FB0

FB1

ADCACLKC

Complementary clock from ADC-A

Table 6. Single LVDS DDR ADC to FB Port B

PIN NAME

ADCB[7:0]P

ADCB[7:0]N

ADCBCLK

PIN NUMBER

I/O

DESCRIPTION

ADC-B positive feedback from PA output

ADC-B negative feedback from PA output

Clock from ADC-B

FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34

I

FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35

FB18

FB19

ADCBCLKC

Complementary clock from ADC-B

MPU INTERFACE GUIDELINES

The following section describes the hardware interface between the recommended microprocessor, external

memory, and the GC5328. Users may select a microprocessor that meets their specific system requirements.

Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully

supported with host control and adaptation software. Figure 7 and Figure 9 illustrate the hardware interface

between the DSP, GC5328, and SDRAM. The external memory is required to accommodate the computational

efforts of the adaptation algorithm. Although the system evaluation kit suggests dual-parallel 64-Mb/PC133

(128-Mb) memory modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are

available.

The use of an external inverter with minimal propagation delay is required for OEB of the GC5328; this device is

necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in

the TMS320C672x Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP

External Memory Interface (EMIF) user's guide (SPRU711).

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Note: One DSP is

shared With

GC532xs

HOST UHPI

INTERFACE

EMIF Addr

Cntl SDRAM

Multiplex

Address

Half Data

UHPI

SDRAM

EMIF Data

r

e

s

DSP RST

BOOTMODE

TI6727

DSP

UPDATA[]

UPADDRESS[]

and CNTL CS2-2

To/From

Other GC5322

EMIF Addr

Cntl GC5322

DSP JTAG

Inv

RDB, CS2[]

INTROUT

First GC532x

INTROUT(2)

GPIO

Ant

SelCode

UPDATA[]

INTROUT

UPADDRESS[]

and CNTL

CS2-1

B0374-01

Figure 9. DSP-to-GC5328 EMIF Interface Specifications

ABSOLUTE MAXIMUM RATINGS

VALUE

UNIT

V

V_DD, V_DDA

V_DDS

Core supply voltage

–0.3 to 1.32

–0.3 to 2

Digital supply voltage for TX

Digital supply voltage

V

V_DDSHV

V_IN

–0.3 to 3.6

V

Input voltage (under/overshoot)

Clamp current for an input/output

Storage temperature

–0.5 to VDDSHV + 0.5

–20 to 20

V

mA

°C

T_stg

–65 to 150

Lead soldering temperature, 10 seconds

300

(Required 2-kV HBM, 500-V CDM)

(Passed 2.5-kV HBM, 500-V CDM, 200-V MM)

ESD classification Class 2

Moisture sensitivity Class 3 (floor life at 30°C/60% H)

Reflow conditions JEDEC standard

1

week

°C

260

±100

Latchup

JEDEC Level 2 per JEDEC 78 standard (at 90°C and 1.5 × Vmax)

mA

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

1.2

1.1

1.8

3.3

MAX

UNIT

V_DD, V_DDA2, V_PP

V_DDA1

Core supply voltages. Note V_DDA2≤ V_DD

Analog supply for DPD PLL

1.14

1

1.26

VDD

1.89

3.45

3

V

A

See⁽¹⁾

V_DDS

Digital supply voltage for TX

1.71

3.15

V_DDSHV

Digital supply voltage

I_DD, I_DDA1, I_DDA2

,

Combined supply current for Vdd, Vdda1, Vdda2, and V_PP

I_PP

I_DDS

I_DDSHV

T_C

Digital supply current for TX

Digital supply current

Case temperature

0.25

0.3

85

A

See⁽²⁾

–40

30

°C

(1) VDDA1 must be less than VDD1 when VDD1 is low. See recommended filtering circuit in Figure 1 Figure 1. Maximum observed current

on VDDA1 is 8 mA.

(2) Chip specifications in are production tested to 90°C case temperature. QA tests are performed at 85°C.

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RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

T_J

Junction temperature

See⁽³⁾

105

°C

(3) Thermal management may be required for full-rate operation. Sustained operation at elevated temperatures reduces long-term reliability.

Lifetime calculations based on maximum junction temperature of 105°C.

THERMAL CHARACTERISTICS⁽¹⁾

PARAMETER

484 BGA AT 2.5 W

UNITS

°C/W

R_θJA

Thermal resistance, junction-to-ambient (still air)

Thermal resistance, junction-to-ambient (1 m/s)

Thermal resistance, junction-to-case

18

14.3

6.8

8

R_θJMA1

R_θJC

R_θJB

Thermal resistance, junction-to-board

(1) Customer must check that heat removal is appropriate for the application to limit the junction temperature (T_J) aspecified in the

Recommended Operating Conditions. Conducting heat through the ground and power balls, or adding a heat sink and airflow, may be

needed to limit junction temperature.

ELECTRICAL CHARACTERISTICS

Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU

and JTAG interfaces over recommended operating conditions. Device is production tested at 90°C for the given specification

and characterized at –40°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS INTERFACE

V_IL

CMOS voltage input, low

CMOS voltage input, high

CMOS voltage output, low

CMOS voltage output, high

Pullup current

0.8

V_DDSHV

0.5

V

V_IH

V_OL

V_OH

2

I_OL= 2 mA

I_OH= –2 mA

V_IN= 0 V

V

2.4

40

VDDSHV

200

V

|I_PU

|

100

μA

|I_IN

|

Leakage current

V_IN= 0 or V_IN= V_DDSHV

5

DAC INTERFACE (DACP/N[15:0])

(1)

V_o(diff)

V_comm

Output differential swing

Common mode

| V_OD| = | V_OH– V_OL

(V_OH+ V_OL) / 2⁽¹⁾

|

250

mV

1000

LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C)

V_I

Input voltage range

0

2000

mV

0 < Vi < 2000 mV

1000 mV < V_I< 1400 mV, FB[35:0] only

250

Input differential voltage,

|Vpos – Vneg|

V_I(diff)

R_IN

90

Input differential impedance

80

120

1.7

Ω

POWER SUPPLY

I_dynCore current

See⁽²⁾

A

(1) HSTL output levels measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360.

(2) 400-Mbps DAC signal, 200-Mhz DPD clock, maximum filtering, 70-Mhz BBPLL clock input

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SWITCHING CHARACTERISTICS

Describes the electrical characteristics for the baseband interface, MFIO[19,18]. Sync A, B, C, and BB Clock over

recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

BASEBAND INTERFACE

f_CLK(BB)

Baseband input clock frequency

GPP is ACTIVE

25

70 MHz

GPP is BYPASSED

70

ns

t_su(BB)

Input data setup time before BBCLK↑

BB[15:0], BBFR, SYNCA, SYNCB, and SYNCC;

MFIO18/19

1.3

t_h(BB)

Input data hold time after BBCLK↑

Duty cycle

BB[15:0], BBFR, MFIO18/19

1.5

2

ns

t_{h(SYNCA, -B, -C)}

Duty_CLK(BB)

Valid for SYNCA, SYNCB, and SYNCC

30%

70%

1/f_CLK(BB)

BBCLK

I(ch = 1, t = 1)

Q(ch = 1, t = 1)

Q(ch = N, t = 1)

I(ch = 1, t = 2)

BB[15:0]

t_su(BB)

t_h(BB)

BBFR

T0284-01

Figure 10. Baseband Timing Specifications

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DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

100

30%

0.2

MAX UNIT

f_CLK(DPD)

DPD input clock frequency

DPD input clock duty cycle

Input hold time after DPDCLK↑

Input setup time after DPDCLK↑

Input hold time after DPDCLK↑

Input setup time after DPDCLK↑

Cycle-to cycle jitter

200

MHz

Duty_CLK(DPD)

t_h(SYNCD)

70%

See⁽¹⁾

ns

t_su(SYNCD)

0.4

t_{h(SYNCA, -B, -C)}

t_{su(SYNCA, -B, -C)}

2

0.4

(2)

Jitter_CLK(DPD)

–2.5%

2.5%

(1) Controlled by design and process

(2) Jitter is based on a period of (1/(DPDClk × 2)) (for BUC Interp 1 or 2); (1/( DPDClk × 3)) (for BUC Interp 1.5 or 3).

DPDCLK

DPDCLKC

SYNCDC

SYNCD

t_su(SYNCD)

t_h(SYNCD)

SYNCA

SYNCB

SYNCC

t_{su(SYNCA, -B, -C)}

t_{h(SYNCA, -B, -C)}

T0286-01

Figure 11. DPD Clock and Fast Sync Timing Specifications

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MPU SWITCHING CHARACTERISTICS (READ)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

WRB is HIGH

MIN

5

MAX UNIT

t_su(AD)

t_su(CEB)

t_su(OEB)

t_d(RD)

ADDR setup time to RDB↓

ns

CEB setup time to RDB↓

WRB is HIGH

7

OEB setup time to RDB↓

2

DATA valid time after RDB↓

14

7

ns

ADDR hold time to RDB↑

2

0

7

t_h(RD)

OEB, CEB hold time to RDB↑

Time RDB must remain HIGH between READs.

DATA goes high-impedance after OEB↑ or RDB↑

t_HIGH(RD)

t_Z(RD)

WRB is HIGH⁽¹⁾

ns

(1) Controlled by design and process and not directly tested.

RDB

t_HIGH(RD)

WRB

t_h(OEB)

t_su(OEB)

OEB

t_su(CEB)

CEB

t_su(AD)

ADDR

3-State

DATA

t_d(RD)

t_Z(RD)

t_h(RD)

T0287-01

Figure 12. MPU READ Timing Specifications

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

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MPU SWITCHING CHARACTERISTICS (WRITE)

PARAMETER

TEST CONDITIONS

OEB and RDB are HIGH

MIN

5

MAX UNIT

DATA and ADDR setup time to WRB↓

t_su(WR)

CEB setup time to WRB↓

7

ns

OEB setup time to WRB↓

2

DATA and ADDR hold time after WRB↑

OEB and CEB hold time after WRB↑

Time WRB and CEB must remain simultaneously LOW

Time CEB or WRB must remain HIGH between WRITEs

2

t_h(WR)

ns

0

t_low(WR)

t_high(WR)

OEB and RDB are HIGH

15

10

ns

RDB

t_low(WR)

t_high(WR)

WRB

OEB

t_h(WR)

t_su(WR)

CEB

ADDR

DATA

T0288-01

Figure 13. MPU WRITE Timing Specifications

20

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

JTAG SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS PARAMETER

MIN

MAX UNIT

f_TCK

JTAG clock frequency

50

MHz

ns

t_p(TCKL)

t_p(TCKH)

t_su(TDI)

t_h(TDI)

JTAG clock low period

10

1

JTAG clock high period

ns

Input data setup time before TCK↑

Input data hold time after TCK↑

Output data delay from TCK↓

Valid for TDI and TMS

ns

6

ns

t_d(TDO)

8

ns

1/f_TCK

TCK

t_p(TCKH)

t_p(TCKL)

TDI

t_su(TDI)

t_h(TDI)

TDO

t_d(TDO)

T0289-01

Figure 14. JTAG Timing Specifictions

TX SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

HSTL MODE – DDR ex. DAC5682

f_CLK(DAC)

t_SKW(DAC)

DAC output clock frequency

DACCLK to DAC data

R_L= 100 Ω⁽¹⁾

R_L= 100 Ω⁽²⁾

300 MHz

TBD

ps

(1) Because the output clock is DDR, the data rate is 2× the f_CLKrate; f_CLK(DAC)= (BUC Interp × DPDClk / 2).

(2) t_SKW(DAC)data clock-to-data is measured during characterization.

1/f_CLK(DAC)

DACCLKC

DACCLK

DAC[15:0]P

Q

I

DAC[15:0]N

t_SKW(DAC)

T0290-01

Figure 15. TX Timing Specifications (HSTL – DDR)

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UNIT

TX SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

2-mA load⁽¹⁾

2-mA load⁽²⁾

MIN

TYP

MAX

HSTL MODE – SDR ex. DAC5688

f_CLK(DAC)

DAC output clock frequency

200

1.5

MHz

ns

t_d

DACCLK-to-DACData delay time

DACCLK-to-DACData hold time

t_ho

1.5

ns

(1) Because the output clock is SDR, the positive edge of the clock is used to register the data at the DAC receiver. The clock rate is limited

to 200 MHz.

(2) t_dand t_hodata clock-to-data is measured during characterization.

DACCLKC

DACCLK

DAC[15:0]

I or Q

t_ho

t_d

T0448-01

Figure 16. TX Timing Specifications (HSTL – SDR)

ENVELOPE SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

MFIO CMOS – SDR to Envelope Modulator

f_CLK(ENV)

ENVELOPE data output clock frequency

2-mA load⁽¹⁾

DPDC

lk/2

MHz

t_d

ENVCLK-to-ENVData delay time

ENVCLK-to-ENVData hold time

2-mA load⁽²⁾

1.5

ns

t_ho

1.5

(1) Envelope output is magnitude; this is a real output at a DPDClk/2 (100-MHz) rate.

(2) t_dand t_hodata clock-to-data is measured during characterization.

ENVCLK

ENVDATA[15:0]

t_ho

t_d

T0449-01

Figure 17. Envelope Timing (MFIO – CMOS 3.3 V)

22

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

LVDS SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.

N means the number of differential pairs used to transmit data from one ADC, and M means the number of bits sent serially

down each LVDS pair. Thus, 8x2 means eight LVDS pairs, each containing 2 bits of information sent serially. NOTE: The

ADC clock rate must match the DPDClock rate for real feedback.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

16x1 SDR LVDS MODE ex. ADS5444

f_CLK(ADC)

t_su(ADC[#]P)

t_h(ADC[#]P)

ADC interface clock frequency

Input data setup time before CLK↑

Input data hold time after CLK↑

See⁽¹⁾

See^{(1) (2)}

200

MHz

ps

300

600

ps

8x2 DDR LVDS MODE ex. ADS5545, ADS6149

f_CLK(ADCA)

ADCA interface clock frequency

Input data setup time before CLK↑↓

Input data hold time after CLK↑↓

ADCB interface clock frequency

Input data setup time before CLK↑↓

Input data hold time after CLK↑↓

See⁽¹⁾

200

MHz

ps

t_{su(ADCA[#/2]P)}

t_{h(ADCA[#/2]P)}

f_CLK(ADCB)

See^{(1) (3)}. For port A

See⁽¹⁾

See^{(1) (4)}. For port B

430

260

ps

MHz

ps

t_{su(ADCB[#/2]P)}

t_{h(ADCB[#/2]P)}

800

400

ps

(1) Specifications are limited by GC5328 performance and may exceed the example ADC capabilities for the given interface.

(2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing

(VOD = 0).

(3) Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (VOD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing

(VOD = 0).

(4) Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (VOD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing

(VOD = 0).

1/f_CLK(ADC)

CLK

CLKC

ADC[15:0]P

ADC[15:0]N

t_su(ADC[#]P)

t_h(ADC[#]P)

T0291-01

Figure 18. LVDS Timing Specification (16x1 SDR LVDS)

1/f_CLK(ADCx)

CLK

CLKC

ADC[# bits/2]P

ADC[# bits/2]N

Even Bits

Odd Bits

t_{su(ADCx[#/2]P)}

t_{h(ADCx[#/2]P)}

t = N

t = N + 1

T0293-01

Figure 19. LVDS Timing Specification (8x2 DDR LVDS)

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

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GLOSSARY OF TERMS

3G

Third-generation (refers to next-generation wideband cellular systems that use CDMA)

Third-generation partnership project (W-CDMA specification, www.3gpp.org)

Third-generation partnership project 2 (cdma2000 specification, www.3gpp2.org)

Adjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier)

Adjacent channel power ratio

3GPP

3GPP2

ACLR

ACPR

ADC

BW

Analog-to-digital converter

Bandwidth

CCDF

CDMA

CEVM

CFR

CMOS

DAC

dB

Complementary cumulative distribution function

Code division multiple access (spread spectrum)

Composite error vector magnitude

Crest factor reduction

Complementary metal oxide semiconductor

Digital-to-analog converter

Decibels

dBm

DDR

DSP

DUC

EVM

FIR

Decibels relative to 1 mW (30 dBm = 1 W)

Dual data rate (ADC output format)

Digital signal processing or digital signal processor

Digital upconverter (usually provides the GC5328 input)

Error vector magnitude

Finite impulse response (type of digital filter)

In-phase and quadrature (signal representation)

Intermediate frequency

I/Q

IF

IIR

Infinite impulse response (type of digital filter)

Joint Test Action Group (chip debug and test standard 1149.1)

Local oscillator

JTAG

LO

LSB

Least-significant bit

Mb

Megabits (divide by 8 for megabytes MB)

Most-significant bit

Megasamples per second (1×10⁶samples/s)

MSB

MSPS

PA

Power amplifier

PAR

PCDE

PDC

PDF

Peak-to-average ratio

Peak code domain error

Peak detection and cancellation (stage)

Probability density function

RF

Radio frequency

RMS

SDR

SEM

SNR

UMTS

W-CDMA

WiBRO

WiMAX

Root mean square (method to quantify error)

Single data rate (ADC output format)

Spectrum emission mask

Signal-to-noise ratio (usually measured in dB or dBm)

Universal mobile telephone service

Wideband code division multiple access (synonymous with 3GPP)

Wireless broadband (Korean initiative IEEE 802.16e)

Worldwide Interoperability of Microwave Access (IEEE 802.16e)

24

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PACKAGE OPTION ADDENDUM

www.ti.com

12-Nov-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

GC5328IZER

ACTIVE

BGA

ZER

484

60

Pb-Free

(RoHS)

SNAGCU

Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	GC5328IZER
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	BGA
包装说明：	HBGA,
针数：	484
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.81
JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e1
长度：	23 mm
湿度敏感等级：	4
功能数量：	1
端子数量：	484
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HBGA
封装形状：	SQUARE
封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	2.48 mm
标称供电电压：	1.2 V
表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL
端子节距：	1 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	23 mm
Base Number Matches：	1

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