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产品型号GD82559C的概述

芯片GD82559C的概述 GD82559C是一款由古河电气(GIGABYTE)研发的网络控制器芯片,广泛应用于以太网连接。它在多种计算设备中扮演着极为重要的角色,旨在提供高效、可靠的网络连接。GD82559C支持连接速度高达100Mbps,成为了许多嵌入式应用和计算机网络设备的首选解决方案。 该芯片的设计目的是满足多样化的网络需求,尤其是在高速数据传输和低延迟的场合。GD82559C基于先进的半导体技术,结合高效的网络协议处理能力,确保在不同的应用场景下都能达到最佳性能。此芯片不仅支持传统的以太网协议,还具备对现代网络技术和协议的支持,展现出其广泛的适用性。 芯片GD82559C的详细参数 GD82559C的主要参数如下: - 接口类型: 以太网接口 - 最大数据传输速率: 100Mbps - 支持协议: 802.3、802.3u、802.1Q等 - 工作电压: 3.3V - 功耗:...

产品型号GD82559C的Datasheet PDF文件预览

Intel-Based Electronic  
Classroom Student Computing  
Station Based on the Intel®  
Celeron™ Processor and Intel®  
810 Chipset  
Reference Configuration  
August 2000  
Order Number: 273292-002  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual  
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability  
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to  
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not  
intended for use in medical, life saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for  
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.  
The Intel® Celeronand Pentium® II processors, 810 Chipset, and 82559 ethernet controller may contain design defects or errors known as errata  
which may cause the product to deviate from published specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling  
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.  
Copyright© Intel Corporation, 2000  
*Other brands and names are the property of their respective owners.  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
Contents  
1.0  
Introduction ......................................................................................................................5  
1.1  
1.2  
1.3  
Purpose .................................................................................................................5  
Terminology...........................................................................................................5  
Revision History ....................................................................................................5  
2.0  
3.0  
Intel-Based Electronic Classroom Environment Overview..........................................6  
Intel-Based Electronic Classroom Setup and Operating Environment.......................7  
3.1  
Intel-Based Electronic Classroom Configuration...................................................8  
3.1.1 Network Environment ...............................................................................8  
3.1.2 Teacher Station Management System .....................................................9  
3.1.3 Multimedia Teaching Software .................................................................9  
3.1.4 Application Software...............................................................................10  
3.1.5 Remote Booting Intel-Based Electronic Classroom Student  
Computing Stations from Server ............................................................10  
4.0  
5.0  
Recommended Motherboard Configuration for Intel-Based  
Electronic Classroom Student Computing Stations...................................................11  
Design Consideration of Intel-Based Electronic Classroom  
Student Computing Station Hardware .........................................................................13  
®
5.1  
Intel Celeron™ Processor .................................................................................13  
®
5.1.1 Design Notes for the Intel Celeron™ Processor ..................................13  
®
5.2  
Intel 810 Chipset ...............................................................................................14  
®
5.2.1 The Intel 82810 Graphics Memory Controller Hub (GMCH0) ..............15  
®
5.2.1.1 Design Notes for the Intel 82810 GMCH0...............................15  
®
5.2.2 The Intel 82801 I/O Controller Hub (ICH).............................................16  
®
5.2.2.1 Design Notes for the Intel 82801 ICH......................................16  
5.3  
5.4  
IDE Connectors...................................................................................................17  
AC’97 2.1 Compliant Components......................................................................17  
5.4.1 Design Notes for AC’97 Devices ............................................................18  
Audio/Modem Riser Card (AMR).........................................................................18  
5.5.1 Design Notes for the Audio/Modem Riser Card .....................................18  
PCI ......................................................................................................................19  
5.5  
5.6  
5.7  
®
Network Controller — Intel 82559 Fast Ethernet Controller..............................19  
®
5.7.1 Design Note for the Intel 82559 Fast Ethernet Controller ....................19  
5.7.2 Wired for Management...........................................................................21  
5.7.2.1 Instrumentation..........................................................................21  
5.7.2.2 Remote Service Boot ................................................................22  
5.7.2.3 Remote Wake-Up......................................................................22  
5.7.2.4 Power Management ..................................................................22  
Low Pin Count (LPC) Interface............................................................................22  
5.8  
6.0  
Conclusion......................................................................................................................23  
A
B
References......................................................................................................................25  
Intel-Based Electronic Classroom Schematics...........................................................27  
Application Note  
3
Intel-Based Electronic Classroom Student Computing Station  
Figures  
1
2
Typical Intel-Based Electronic Classroom Setup .................................................. 7  
Building Block of the Intel-Based Electronic Classroom Student  
Computing Station Motherboard .........................................................................12  
Topology for Single Processor Designs with Single End Termination (SET)......13  
Placement of Termination Resistor .....................................................................20  
Trace Geometry ..................................................................................................20  
Cover Sheet Schematic ......................................................................................28  
Block Diagram.....................................................................................................29  
370-Pin Socket (Part 1).......................................................................................30  
370-Pin Socket (Part 2).......................................................................................31  
GTL Terminal Schematic ....................................................................................32  
Clock Synthesizer Schematic..............................................................................33  
82810, Part 1: Host Interface Schematic ............................................................34  
82810, Part 2: System Memory and Hub Interface Schematic ...........................35  
82810, Part 3: Graphics Schematic ....................................................................36  
System Memory Schematic ................................................................................37  
82810AA, Part 1 Schematic ................................................................................38  
82810AA, Part 2 Schematic ................................................................................39  
Firmware Hub (FWH) Schematic ........................................................................40  
Super I/O Schematic ...........................................................................................41  
PCI Connector Schematic...................................................................................42  
ATA/33 IDE Connectors Schematic ....................................................................43  
USB Connectors Schematic................................................................................44  
Parallel Port Header Schematic ..........................................................................45  
Serial Port/Com Headers Schematic ..................................................................46  
Keyboard/Mouse Ports, Floppy Disk Header, Game Post Header Schematic ...47  
Video Connectors Schematic..............................................................................48  
Audio Riser Schematic........................................................................................49  
LAN Schematic ...................................................................................................50  
LAN Schematic ...................................................................................................51  
Voltage Regulators..............................................................................................52  
Processor Voltage Regulator Schematic ............................................................53  
System Schematic ..............................................................................................54  
System: Power Connector and Reset Control Schematic...................................55  
Pull-Up Resistors and Unused Gates Schematic................................................56  
730-Pin Socket Decoupling Schematic ...............................................................57  
DRAM, Chipset and Bulk Power Decoupling Schematic ....................................58  
Revision History Schematic ................................................................................59  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
Tables  
1
2
Intel-Based Electronic Classroom Hardware Descriptions and  
Recommended Configuration ............................................................................... 8  
AC’97 Configuration Combinations .....................................................................17  
4
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
1.0  
Introduction  
1.1  
Purpose  
®
This application note describes how Intel architecture processors, chipsets, and other components  
can be used in designs for Intel-based electronic classroom student computing stations. An  
Intel-based electronic classroom is an educational setting in which a network of computers is used  
as a primary teaching, learning, and assessment tool. A typical Intel-based electronic classroom  
contains an instructor’s system that broadcasts application software to, and often receives data  
from, student computing stations. The student computing stations can be configured and  
administered at the server level.  
Intel architecture components are well-suited for Intel-based electronic classroom systems. Using  
PC-based building blocks in these designs provides flexibility, upgradability, ease of  
administration, and high performance for graphic-intensive and internet applications. In addition,  
Intel architecture processors are compatible with a wide variety of operating system and  
off-the-shelf application software. This application note describes a typical Intel-based electronic  
classroom network and provides a reference design for Intel architecture-based electronic  
classroom student computing stations.  
Schematics for the reference design are provided in Appendix B of this document.  
1.2  
Terminology  
The following terms are used in this document.  
Term  
Definition  
Intel-Based  
Electronic  
Classroom  
An electronic teaching and learning environment that uses dedicated, connected student  
computing stations to implement a specific educational curriculum  
Remote boot  
TCO  
A client operating system boot up from a server in a network environment  
Total cost of ownership  
ISV  
Independent software vendor  
WfM  
Intel’s Wired for Management initiative  
1.3  
Revision History  
Revision  
Date  
Notes  
001  
October 15, 1999  
Initial version.  
Application Note  
5
Intel-Based Electronic Classroom Student Computing Station  
2.0  
Intel-Based Electronic Classroom Environment  
Overview  
An Intel-based electronic classroom is a teaching and learning environment that uses a server-client  
system in the classroom to implement the curriculum. Teaching and learning is done using a  
teacher station, student computing stations, and specific educational software applications and  
content. With this modern educational technology, educators can deliver intuitive online courses,  
training, demonstrations, and examinations. They can also incorporate access to the Internet and  
intranet to enrich the educational experience.  
An Intel-based electronic classroom LAN environment can consist of up to 60 student computing  
stations, a teacher station, and a network server. In an Intel-based electronic classroom, every  
student computing station is administered centrally. These student computing stations have high  
reliability and security, and low maintenance costs. The student computing stations have a subset  
of a PC feature set: they typically have a different motherboard configuration (described in  
Section 4.0) and are configured without a CD-ROM drive or hard disk. This solution provides a  
greater access to the necessary technology while simplifying maintenance and reducing the total  
cost of ownership.  
In schools, PCs can be used in teacher offices as productivity tools for administration and  
development of teaching materials. These materials may then be used in Intel-based electronic  
classrooms to teach subjects such as computer skills, languages, sciences, and mathematics. The  
teacher uses the teacher station in the Intel-based electronic classroom to guide students through  
the lesson, while each student follows the lesson on his/her own student computing station. The  
students can also use their student computing stations independently to practice lesson materials  
and learn other application software.  
Desirable features of Intel-based electronic classroom student computing stations include the  
following:  
Ease of management and maintenance  
Primary and secondary schools typically do not have a full time Information Technology (IT)  
staff to manage the Intel-based electronic classroom. Most IT administration is done by  
teachers and student volunteers. Hence, the student computing stations used in the Intel-based  
electronic classroom must be easy to manage.  
Intel-based electronic classroom student computing stations can be configured without  
CD-ROM and floppy drives. This further simplifies the management of these student  
computing stations by preventing students from erasing files or corrupting the operating  
system and applications.  
Low total cost of ownership (TCO)  
Schools have limited budgets for setting up Intel-based electronic classrooms. Therefore, a key  
consideration is affordability in terms of initial capital and ongoing maintenance costs,  
including the costs of off-the-shelf educational applications and teaching content.  
Software availability and compatibility  
Establishing a productive Intel-based electronic classroom depends on the availability of  
system-compatible, off-the-shelf applications and teaching materials. It is important that  
schools have tools to develop customized content to meet the particular needs of their students.  
Product life cycle support  
Schools use Intel-based electronic classroom student computing stations for several years  
before considering an upgrade. Therefore, replacement parts should be available for this  
duration.  
6
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
3.0  
Intel-Based Electronic Classroom Setup and  
Operating Environment  
A typical Intel-based electronic classroom setup is depicted in Figure 1.  
Figure 1.  
Typical Intel-Based Electronic Classroom Setup  
Internet  
Home  
PC  
School Network  
15 - 60 Student  
Computing Stations  
Server  
Teacher Station  
Intel-Based Electronic Classroom  
A7490-02  
The student and teacher stations are linked together in a LAN environment via a network hub or  
switch device. The LAN network enables the remote boot for diskless student computing stations  
and file sharing among all the student computing stations. The broadcasting capability is  
implemented through software using the existing LAN infrastructure. This solution reduces overall  
system cost, simplifies wiring and upgrade requirements, and enables the use of higher  
performance processors.  
The components of a typical Intel-based electronic classroom and their recommended  
configuration are described in Table 1.  
Application Note  
7
Intel-Based Electronic Classroom Student Computing Station  
Table 1.  
Intel-Based Electronic Classroom Hardware Descriptions and Recommended  
Configuration  
Quantity  
Item  
Teacher Station  
Recommended Configuration  
(units)  
Intel® Pentium® III processor, 64 -128 Mbyte SDRAM, Intel® 440BX AGPset, Hard-disk,  
1
Intel® Network Card, Video Capture Card  
Student Computing  
Station  
Intel® Celeronprocessor 433 MHz or better (in 370-pin PPGA) and Intel® 810 chipset,  
32 Mbyte SDRAM, Intel Network Card integrated on board, Hard-disk (optional)  
Pentium III processor, 128 Mbyte SDRAM, Intel® L440GX motherboard, SCSI Hard-disk,  
Intel Network Card  
15 - 60  
1
Server  
Switch  
Router  
1-3  
1
Intel Express 510T, 24 10/100Mbit Switching Port  
Intel Express 9500 Router for Internet connection  
Multimedia teaching  
Software  
From ISVs. Based on TCP/IP or IPX network protocol. Intel® LANSchool software site is a  
basic reference: http://www.intel.com/network/products/lanschool.htm  
1
3.1  
Intel-Based Electronic Classroom Configuration  
The configuration of the Intel-based electronic classroom depends on the size of the classroom, the  
network design, and the use of the multimedia broadcasting software. The following describes an  
example configuration that consists of five main parts:  
Network environment  
Teacher Station management system  
Multimedia broadcasting software  
Application and education software  
Intel-based electronic classroom student computing stations that remote boot from server  
The following sections describe each component of the example Intel-based electronic classroom.  
3.1.1  
Network Environment  
The network can be set-up using Windows* NT 4.0 or Novell Netware* on the server. The teacher  
station and student computing stations run on Windows 95/98 operating systems. The Intel-based  
electronic classroom student computing stations boot up remotely from a server that is connected  
in a LAN environment.  
8
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
3.1.2  
Teacher Station Management System  
The teacher station in this example can perform the following functions:  
Broadcasting the teacher station screen  
All teaching materials, including presentation, animations, and movies can be broadcast to the  
student computing stations.  
Controlling student computing stations remotely  
The teacher can control, reset, and lock the student computing stations or receive the display  
from a particular Intel-based electronic classroom student computing station.  
Providing online help  
The teacher can provide help through the network when students have difficulty with their  
assignment. The students would also be able to request assistance through the network.  
3.1.3  
Multimedia Teaching Software  
The multimedia teaching software utilizes a standard LAN network interface through TCP/IP  
protocol and typically offers the following features:  
Screen broadcasting  
— Each computing station (teacher’s and student’s) can broadcast its screen to some or all  
students. Only one screen can be broadcast at a time.  
— The teacher can lock each student’s keyboard and mouse and can broadcast any student’s  
screen to the class.  
— All graphics formats, such as MPEG and VCD can be broadcast in real time.  
Audio/voice communication  
— The teacher’s voice can be broadcast to one, several, or all students.  
— Conferencing is supported in teacher-student, student-student, or other combinations.  
— The voice can be input through MIC or Line In on the sound card.  
Remote access  
— The teacher can view any student’s screen remotely.  
Grouping  
— Student computing stations can be grouped in any combination for discussion  
(screen/audio).  
Question  
— Students can submit questions through MIC or keyboard (using a special function key).  
— Two way or multi-way online questioning is supported, as in a “chat” mode.  
Remote reset  
— The teacher can reset any or all Intel-based electronic classroom student computing  
stations if an error occurs in the system.  
Examinations can be administered and completed online.  
Application Note  
9
Intel-Based Electronic Classroom Student Computing Station  
3.1.4  
3.1.5  
Application Software  
Typically, application software, such as word processing and spreadsheet programs, and  
instructor-developed materials are taught in Intel-based electronic classrooms. In some Intel-based  
electronic classrooms, students are assessed using on-line examinations.  
Remote Booting Intel-Based Electronic Classroom Student  
Computing Stations from Server  
During the remote boot process, the Intel-based electronic classroom student computing stations  
contact the server (using Preboot Execution Environment in the boot ROM of the network  
interface), install a boot image, and boot the operating system that is pre-configured on the server.  
Various operating systems can be remote booted from the server, including Windows 95/98 or  
Linux*.  
The setup is optimized through the availability of the Preboot Execution Environment (PXE)  
compliant boot ROM. PXE allows the server to set up each student computing station with a  
specific IP address using the Dynamic Host Communication Protocol (DHCP). The boot ROM  
then downloads the boot image from the server using the Trivial File Transfer (TFT) protocol. This  
boot image program then configures the student computing stations and boots the pre-configured  
operating system. If the Intel-based electronic classroom student computing station’s operating  
system or applications are damaged, they can be recovered by downloading the new image from  
server when the system restarts. This reduces the total cost of maintenance. Refer to section  
Section 5.7.2.2, “Remote Service Boot” on page 22 for more information.  
10  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
4.0  
Recommended Motherboard Configuration for  
Intel-Based Electronic Classroom Student  
Computing Stations  
The motherboard of this reference design for Intel-based electronic classroom student computing  
stations is a highly integrated design that incorporates many features on the board. It is  
recommended that system designers use an LPX form factor or Flex ATX design. The LPX form  
factor enables the student computing stations to have a very slim casing, which is desirable for  
small Intel-based electronic classroom environments. Flex ATX helps reduce board size and cost.  
The components listed below provide an example of a motherboard design based on the Celeron  
processor and Intel 810 chipset.  
Main Components of Reference Motherboard for the Intel-Based Electronic Classroom  
Student Computing Station:  
Intel® Celeron™ processor 300A/366/433 MHz in 370-pin PPGA  
Intel® 810 Chipset  
Two DIMM sockets that support up to 512 Mbyte (128 Mbit technology) SDRAM  
Two IDE interfaces  
One floppy disk interface  
COM 1 and COM 2 serials ports and a parallel port  
PS/2 mouse and keyboard connectors  
Intel® Flash BIOS  
Super I/O* and USB ports  
1 X PCI 2.2-compliant PCI slot  
Peripherals on Intel-Based Electronic Classroom Student Computing Station:  
Integrated audio in chipset  
Audio Codec ’97 2.1 extensions compliant  
Stereo line level output  
One audio out, audio in, and MIC jack  
Integrated Graphics  
3-D graphics with texturing and visual enhancements up to 1024x768x16 @85 Hz refresh  
2-D graphics up to 1600x1200x8 @85 Hz refresh  
RGB output  
PCI-based 10/100 Mbps Network card  
Intel® 82559-based card recommended  
One RJ-45 port  
Boot ROM which contains Intel® Preboot Execution Environment (PXE)  
Application Note  
11  
Intel-Based Electronic Classroom Student Computing Station  
Figure 2.  
Building Block of the Intel-Based Electronic Classroom Student Computing Station  
Motherboard  
®
Intel Celeron  
Processor  
System Bus  
[66 MHz]  
®
Intel 810  
Chipset  
Display I/F  
SDRAM Memory  
100 MHz  
Monitor  
82810  
241 BGA  
GD82559  
2 IDE Port/  
Ultra AT A66  
Intel Network Controller  
Support 10/100 Mbit  
One RJ-45 port  
One Flash boot ROM  
SMBus  
82801AA  
241 BGA  
PCI 33  
1 PCI  
REQ/GNT  
Low Pin  
Count Interface  
82802AB  
4Mb  
COM1 & COM 2 Serial Ports  
Parallel Port  
PS/2 Mouse  
AC'97 Riser  
AC'97 2.1  
Super IO*  
Floppy Disk Interface  
Keyboard Connectors  
A7493-01  
12  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
5.0  
Design Consideration of Intel-Based Electronic  
Classroom Student Computing Station Hardware  
5.1  
Intel® CeleronProcessor  
This reference configuration supports the Intel Celeron processor at 300, 366 MHz and 433 MHz  
in a Plastic Pin Grid Array (PPGA) package.  
The Intel Celeron processor PPGA package implements a Dynamic Execution micro-architecture  
and executes MMX™ media technology instructions for enhanced media and communication  
performance. The Intel Celeron processor PPGA is based on the P6 family processor core and is  
provided in a PPGA package for use in low cost systems in the value PC and Intel-based electronic  
classroom student computing station market segments. The Intel Celeron processor PPGA utilizes  
®
the AGTL+ system bus used by the Pentium II processor with support limited to single-processor  
systems. The Intel Celeron processor PPGA includes an integrated 128 Kbyte second level cache  
with separate 16 Kbyte instruction and 16 Kbyte data level-one caches. The second level cache is  
capable of caching 4 Gbytes of system memory.  
5.1.1  
Design Notes for the Intel® CeleronProcessor  
The schematics use a Single Ended Termination (SET) network topology in which the termination  
resistors are located at only the PPGA (processor) side to reduce the system cost, solution space,  
and ringing effect. In the SET topology, the termination should be placed close to the processor  
either on the motherboard or on the processor substrate. No termination is present at the chipset end  
of the network.  
Figure 3.  
Topology for Single Processor Designs with Single End Termination (SET)  
V
TT  
††  
L2  
®
Intel 810  
Chipset  
L1  
- 1.9" <L1 <5.0"  
†† - 0.5" <L2 <2.0"  
A7494-01  
Application Note  
13  
Intel-Based Electronic Classroom Student Computing Station  
5.2  
Intel® 810 Chipset  
Intel has developed technology that enhances the performance and value of Intel Celeron  
processor-powered systems. Built on the strong foundation of Intel 440BX AGPset technology, the  
Intel 810 chipset provides next generation features and great graphics performance at a lower cost.  
The Intel 810 chipset contains three core components:  
1. Host Controller Graphics and Memory Controller Hub (GMCH0)  
The GMCH0 (82810) provides the interconnect between the SDRAM and the rest of the  
system logic:  
421 Mini BGA  
Integrated Graphics controller  
230 MHz RAMDAC  
Support for Intel Celeron processors with a 66 MHz system bus.  
100 MHz SDRAM interface supporting 64/256/512 Mbyte with 16/64/128 Mbit SDRAM  
technology  
Downstream hub interface for access to the ICH  
2. I/O Controller Hub 82810AA (ICH)  
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system:  
421 Mini BGA  
Upstream hub interface for access to the GMCH0  
PCI 2.2-compliant interface (6 PCI Req/Grant Pairs for 82801AA ICH)  
Bus Master IDE controller; supports either Ultra ATA/33 or Ultra ATA/66 (82801AA)  
USB controller  
SMBus controller  
FWH interface  
LPC interface  
AC97 2.1 interface  
Integrated System Management Controller  
Alert-on-LAN (82801AA ICH only)  
Interrupt controller  
3. 82802 Firmware Hub (FWH)  
The 82802 FWH component is a key element to enabling a new security and manageability  
infrastructure for the PC platform. The device operates under the FWH interface and protocol.  
The hardware features of this device include:  
An integrated hardware Random Number Generator (RNG)  
Register-based locking  
Hardware-based locking  
5 GPIs  
14  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
5.2.1  
The Intel® 82810 Graphics Memory Controller Hub (GMCH0)  
The Intel 810 chipset provides a rich and robust 2-D and 3-D graphics using an integrated chipset  
design that utilizes second-generation graphics technology. At the core of the 810 chipset is a  
memory controller with built-in graphics technology. The Intel 810 chip optimizes system memory  
arbitration, similar to AGP technology, resulting in a more responsive and cost-effective system.  
The 82810 Graphics Memory Controller Hub (GMCH0) features Intel graphics technology and  
software drivers and uses Direct AGP (integrated AGP) to create vivid 2-D and 3-D effects and  
images. The 82810 chip features integrated Hardware Motion Compensation to improve soft DVD  
video quality and a digital video out port that enables connection to traditional TVs or the new  
space-saving digital flat panel displays.  
Intel Dynamic Video Memory Technology (DVMT) is an architecture that offers breakthrough  
performance for the Value PC segment through efficient memory utilization and Direct AGP. The  
system OS uses the Intel software drivers and intelligent memory arbiter to support richer graphics  
applications.  
The System Manageability Bus allows networking equipment to monitor the 810-chipset platform.  
Using ACPI specifications, the system manageability function enables low-power sleep mode and  
conserves energy when the system is idle.  
5.2.1.1  
Design Notes for the Intel® 82810 GMCH0  
The GMCH ball assignment and ICH ball assignment have been optimized to simplify hub  
interface routing. It is recommended that the hub interface signals are routed directly from the  
GMCH0 to the ICH on the top signal layer. The hub interface has two signal groups:  
Data Signals: HL[10:0]  
Strobe Signals: HL_STB, HL_STB# (differential strobe pair)  
There are no pull-ups or pull-downs required on the hub interface.  
Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of  
20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for  
navigation around components or mounting holes. To break out of the GMCH0 and the ICH, the  
hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils.  
The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils within 0.3”  
of the GMCH0/ICH components. The maximum trace length for the hub interface data signals is  
7. These signals should each be matched within ±0.1of the HL_STB and HL_STB# signals.  
Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed  
20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The  
maximum length for the strobe signals is 7and the two strobes should be the same length.  
Additionally, the trace length for each data signal should be matched to the trace length of the  
strobes with ±0.1.  
HREF is the hub interface reference voltage. It is 0.5 * 1.8 V = 0.9 V ±2%. It can be generated  
locally, or a single HREF divider can be used. Each divider consists of a DC element and an AC  
element. The resistors in the DC element should be equal in value and rated at 1% tolerance. The  
value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained  
over the entire input leakage specification. The resistors in the AC element of the resistor divider  
should be no greater than 80 and the capacitors should be 500 pF. Additionally, the reference  
voltage should be bypassed to ground at each component with a 0.1 uF capacitor.  
Application Note  
15  
Intel-Based Electronic Classroom Student Computing Station  
5.2.2  
The Intel® 82801 I/O Controller Hub (ICH)  
The 82801 I/O Controller Hub (ICH) employs the Intel Accelerated Hub Architecture to make a  
direct connection from the graphics and memory to the integrated AC97 controller, the IDE  
controllers, dual USB ports, and PCI add-in cards.  
The Accelerated Hub Architecture provides twice the bandwidth of the PCI bus at 266 MB per  
second. This allows a wider flow of rich information from the I/O controller to the memory  
controller, with optimized arbitration rules allowing more functions to run concurrently, enabling  
more life-like audio and video.  
The Integrated Audio-Codec 97 controller enables software audio and modem by using the  
processor to run sound and modem software. By reusing existing system resources, this feature  
adds flexibility, improves sound quality, and lowers the system BOM cost by eliminating  
components.  
The 82802 Firmware Hub (FWH) stores system BIOS and video BIOS, eliminating a redundant  
nonvolatile memory component. In addition, the 82802 contains a hardware Random Number  
Generator (RNG). The Intel RNG provides truly random numbers to enable fundamental security  
building blocks supporting stronger encryption, digital signing, and security protocols.  
5.2.2.1  
Design Notes for the Intel® 82801 ICH  
ICH Placement: The ICH should be placed within 8of the ATA connector(s). There are no  
minimum length requirements for this spacing.  
Capacitance: The capacitance of each pin of the IDE connector on the host should be below  
25 pF when the cables are disconnected from the host.  
Series Termination: There is no need for series termination resistors on the data and control  
signals since series termination is integrated into these signal lines on the ICH.  
A 1 Kpull-up to 5 V is required on PIORDY and SIORDY.  
A 470 pull-down resistor is required on pin 28 of each connector.  
A 5.6 Kpull-down resistor is required on PDREQ and SDREQ.  
Support Cable Select (CSEL) is a PC99 requirement. The state of the cable select pin  
determines the master/slave configuration of the hard drive at the end of the cable.  
Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15.  
IRQ14 and IRQ15 each need an 8.2 Kpull-up resistor to V  
.
CC  
Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1  
of the IDE connectors as the IDE reset signal. Due to high loading, the PCI_RST# signal  
should be buffered.  
There is no internal pull up or down on PDD7 or SDD7 of the ICH. Devices should not have a  
pull-up resistor on DD7. It is recommended that a host have a 10 Kpull-down resistor on  
PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as  
required by the ATA-4 specification).  
If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be  
grounded and the output signals left as no connects.  
16  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
5.3  
IDE Connectors  
The 82801AA ICH supports Ultra ATA/66 and ATA/33 devices The ATA/66 cable is an  
80-conductor cable; however the 40-pin connectors used on motherboards for 40-conductor cables  
do not change as a result of this new cable. The wires in the cable alternate: ground, signal, ground,  
signal, etc. All the ground wires are tied together at the connectors on the cable (and they are tied to  
the ground on the motherboard through the ground pins in the 40-pin connector). This cable  
conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained  
from the Small Form Factor Committee. To determine if ATA/66 mode can be enabled, the Intel  
810 chipset using the ICH requires the system BIOS to attempt to determine the cable type used in  
the system.  
If only one IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be  
grounded and the output signals left as no connects. This can be implemented to reduce the board  
space and cost.  
5.4  
AC97 2.1 Compliant Components  
The ICH implements an Audio Codec '97 (AC97) 2.1 compliant digital controller. Any codec  
attached to the ICH AC-link should also be AC97 2.1 compliant. Contact your preferred codec  
vendor for information on AC97 2.1 compliant products. The AC97 2.1 specification is available  
on the Intel web-site:  
http://developer.intel.com/pc-supp/platform/ac97/index.htm  
The ICH supports the following combinations of codecs:  
Table 2.  
AC97 Configuration Combinations  
Primary  
Secondary  
Audio (AC)  
None  
Modem (MC)  
Audio (AC)  
None  
Modem (MC)  
None  
Audio/Modem (AMC)  
The ICH does not support two codecs of the same type on the link. For example, if an AMC is on  
the link, it must be the only codec. If an AC is on the link, another AC cannot be present.  
Application Note  
17  
Intel-Based Electronic Classroom Student Computing Station  
5.4.1  
Design Notes for AC97 Devices  
Special consideration must be given for the ground return paths for the analog signals. If  
isolated ground planes are used, pin B2 on the AMR connector should be used as an isolated  
ground pin and should be connected to an isolated ground plane to reduce noise in the analog  
circuits. The AMR designer and motherboard designer should jointly address any EMI issues  
when implementing isolated grounds.  
Digital signals routed in the vicinity of the analog audio signals must not cross the power plane  
split lines. Analog and digital signals should be located as far as possible from each other.  
Partition the board with all analog components grouped together in one area and all digital  
components in the other.  
Separate analog and digital ground planes should be provided, with the digital components  
over the digital ground plane, and the analog components, including the analog power  
regulators, over the analog ground plane. The split between the planes must be a minimum of  
0.05wide.  
Keep digital signal traces, especially the clock, as far way from analog input and voltage  
reference pins as possible.  
Do not completely isolate the analog/audio ground plane from the rest of the board ground  
plane. There should be a single point (¼” to ½ ” wide) where the analog/isolated ground plane  
connects to the main ground plane. The split between the planes must be a minimum of  
0.05wide.  
Any signals entering or leaving the analog area must cross the ground split in the area where  
the analog ground is attached to the main motherboard ground (i.e., there should not be any  
signals crossing the split/gap between the ground planes). Doing so will cause a ground loop.  
5.5  
Audio/Modem Riser Card (AMR)  
Intel is developing a common connector specification known as the Audio/Modem Riser (AMR).  
This specification defines a mechanism for allowing OEM plug-in card options. The AMR  
specification is available on the Intel developer website:  
http://developer.intel.com/pc-supp/platform/ac97/index.htm  
The AMR specification provides a mechanism for AC97 codecs to be on a riser card. This is  
important for modem codecs as it helps ease international certification of the modem.  
For the Intel-based electronic classroom student computing station, the audio codec is integrated on  
the motherboard to avoid compatibility issues and robustness. A modem codec is optional for  
electronics classroom.  
5.5.1  
Design Notes for the Audio/Modem Riser Card  
Only one primary codec can be present on the link. A maximum of two present codecs can be  
supported in an ICH platform.  
As the Intel-based electronic classroom student computing station motherboard implements an  
active primary codec (audio) on the motherboard and provides an AMR connector, it must tie  
PRI_DN# to ground. The PRI_DN# pin is provided to indicate that a primary codec is present  
on the motherboard.  
18  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
5.6  
5.7  
PCI  
The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification,  
Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH  
is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus  
interface, please refer to the PCI Local Bus Specification, Revision 2.2. The 82801AA ICH  
supports 6 PCI bus masters (excluding ICH), by providing 6 REQ#/GNT# pairs. The PCI network  
controller (GD82559) is integrated on board; therefore, an extra PCI slot is expandable for a PCI  
network broadcasting card (if implemented).  
Network Controller Intel® 82559 Fast Ethernet Controller  
The 82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer  
device is Intels leading solution for PCI board LAN designs. It is designed for use in Network  
Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems, and  
networking system products. The 82559 combines a low power and small package design which is  
ideal for power- and space-constrained environments. It is compliant with Advanced Configuration  
and Power Interface (ACPI) 1.20A-based power management and with the Wired for Management  
(WfM) 2.0 Baseline specification.  
The 82559 is an integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY. It provides  
a glueless 32-bit PCI master interface and supports a 128 Kbyte Flash interface. The package is a  
thin BGA with a small footprint (15 mm X 15 mm).  
The 82559 supports the Intel Preboot Execution Environment (PXE) driver, which allows a new or  
existing system to boot over the network and download software or an image, including the  
operating system, stored on a server. The 82559 provides for operating system independent  
network booting, automating the setting up and configuration of new systems. If the operating  
system or applications software is damaged, the system can be recovered by downloading the  
original image from server again, reducing the total cost of maintenance.  
5.7.1  
Design Note for the Intel® 82559 Fast Ethernet Controller  
The differential transmit signal pair (TDP/TDN) is terminated with a 100 W (1%) resistor, and the  
differential receive signal pair (RDP/RDN) is terminated with a 120 W (1%) resistor. These  
termination resistors should be placed as close to the PHY as possible. These resistors terminate the  
entire impedance seen at the termination source (for example, the PHY), including the wire  
impedance reflected through the transformer. Figure 4 depicts the placement of the termination  
resistors.  
Application Note  
19  
Intel-Based Electronic Classroom Student Computing Station  
Figure 4.  
Placement of Termination Resistor  
R
RJ-45  
Magnetics  
Module  
82559  
R
Place termination resistors  
as close to the 82559 as possible.  
A7495-01  
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width  
to trace-height above the ground plane. To minimize trace inductance, high-speed signals, such as  
the clock, and signal layers that are close to a ground plane or power plane should be as short and  
as wide as is practical. As shown in Figure 5, this ratio is ideally somewhere between 1:1 and 3:1.  
To maintain the impedance of a trace, the width of the trace should be modified when changing  
from one board layer to another if the two layers are not equidistant from a power or ground plane.  
Figure 5.  
Trace Geometry  
W
W
1 <  
< 3  
H
H
Ground  
A7496-01  
NOTE: W= Trace Width, H= Height Above Ground Plane  
20  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
5.7.2  
Wired for Management  
Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop,  
mobile, server and embedded systems. The goal of WfM is to reduce the total cost of ownership  
(TCO) through improved manageability in the following four technology areas:  
Instrumentation  
Remote Service Boot  
Remote Wake-Up  
Power Management  
Manageability features in each of these four technology areas combine to form the Wired for  
Management Baseline Specification. A copy of the Wired for Management Baseline Specification,  
Version 2.0 can be obtained from:  
http://developer.intel.com/ial/wfm/wfmspecs.htm  
An on-line Design Guide is available at:  
http://developer.intel.com/ial/WfM/design/index.htm  
Future versions of the specification will be available at this site.  
In the Intel-based electronic classroom reference configuration, the NIC is WfM compliant,  
particularly in the Remote Service Boot features needed to support the student computing stations’  
remote boot from the server.  
5.7.2.1  
Instrumentation  
A component's instrumentation consists of code that maintains attributes with up-to-the-minute  
values and adjusts the component's operational characteristics based on these values. By providing  
instrumentation, the platform provides accurate data to management applications, so those  
applications can make the best decisions for managing a system or product. The WfM 2.0 Baseline  
requires that compliant desktop and mobile platforms utilize the DMI Version 2.00 Management  
Interface (MI) and Component Interface (CI) application programming interfaces and host a DMI  
v2.00 Service Provider, as defined by the DMTF. Intel's DMI 2.0 Service Provider Software  
Development Kit (SDK) provides a DMI Service Provider and binaries that support DMI Version  
2.00. This kit is available at the following URL:  
http://developer.intel.com/ial/WfM/tools/sdk/index.htm  
®
Intel® LANDesk Client Manager product includes the Service Provider and component  
instrumentation. Information regarding this product can be found at:  
http://developer.intel.com/ial/WfM/tools/ldcm/index.htm  
The WfM Baseline Instrumentation specification identifies specific DMI standard groups,  
including event generation groups, that must be instrumented for a Baseline-compliant platform.  
This specification provides support for the SMBIOS revision 2.0 specification that along with  
appropriate component instrumentation will supply some of the required data in the specified  
DMI 2.0 groups.  
Application Note  
21  
Intel-Based Electronic Classroom Student Computing Station  
5.7.2.2  
Remote Service Boot  
The WfM Baseline specifies the protocols by which a client requests and downloads an executable  
image from a server and the minimum requirements on the client execution environment when the  
downloaded image is executed. The Baseline specification includes a set of APIs for the particular  
network controller used. The code supporting the Preboot eXecution Environment (PXE) and the  
network controller is provided on the EtherExpressPRO/100 WfM adapters Option ROM. Two  
implementation options are available:  
NIC with Option ROM and Wake on LAN Header  
LAN on Motherboard implementation.  
For this option, the Preboot execution environment and the network controller code must be  
incorporated into the system BIOS.  
In addition, the BIOS must provide the _SYSID_ and _UUID_ data structures. The details of the  
BIOS requirements can be obtained from the Intel web site:  
http://developer.intel.com/ial/WfM/design/pxedt/index.htm  
5.7.2.3  
5.7.2.4  
Remote Wake-Up  
If a student computing station supports a reduced power state, it is possible to bring the system to a  
fully powered state in which all power management interfaces are available. Typically, the LAN  
adapter recognizes a special packet as a signal to wake up the system. The system BIOS must  
enable the wake event and provide wake up status. The details of the BIOS requirements can be  
obtained from the Intel web site:  
http://developer.intel.com/ial/WfM/design/rwudt/index.htm  
Power Management  
WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and  
Mechanical Off. A user accessible switch that will send a soft off request to the system usually  
provides Soft Off. A second optional overrideswitch located in a less obvious place (or removal  
of the power cord) stops current flow forcing the platform into the mechanical off state without OS  
consent. Note that a second overrideswitch is required for legal reasons in some jurisdictions  
(for example, some European countries). The BIOS may support the power management  
requirement either through the APM revision 1.2 or ACPI revision 1.0 specifications. See Intel's  
web site for additional information:  
http://developer.intel.com/ial/WfM/design/pmdt/index.htm.  
5.8  
Low Pin Count (LPC) Interface  
In the Intel 810 chipset platform, the Super I/O* (SIO) component has migrated to the Low Pin  
Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.  
The LPC Super I/O component requires the same feature set as traditional Super I/O components.  
It should include a keyboard and mouse controller, a floppy disk controller, and serial and parallel  
ports. In addition to the Super I/O features, an integrated game port is recommended because the  
AC97 interface does not provide support for a game port. In systems that have ISA audio, the  
game port typically existed on the audio card. The fifteen pin game port connector provides for two  
joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a  
comprehensive list of devices offered and features supported.  
22  
Application Note  
Intel-Based Electronic Classroom Student Computing Station  
6.0  
Conclusion  
Traditional teaching media such as projector, video player, audio recorder, and black board are  
being replaced in the Intel-based electronic classroom by new computer-based teaching media.  
Audio, video and 2-D/3-D graphics can be introduced in the Intel-based electronic classroom. The  
classroom can be connected to the Internet by using modem or Intel router.  
Intel provides the building blocks for Intel-based electronic classroom systems that feature  
manageability, ease of maintenance, compatibility with operating systems and application  
software, and long life cycle support for the Intel components. The recommended motherboard  
configuration is designed to optimize the performance of the overall system, reducing board space,  
power consumption, and the total cost of ownership.  
Application Note  
23  
Intel-Based Electronic Classroom Student Computing Station  
Appendix A References  
Document  
Order Number / URL  
Intel Documents and Resources  
Order Number 290657  
http://developer.intel.com/design/chipsets/designex/290657.htm  
Intel® 810 Chipset Design Guide  
Intel® 82810 Chipset: Intel 82810/82810-DC100 Graphics  
Order Number 290656  
and Memory Controller Hub (GMCH) datasheet  
http://developer.intel.com/design/chipsets/datashts/290656.htm  
Intel® 82801AA (ICH) and Intel 82801AB (ICH0) I/O  
Order Number 290655  
Controller Hub datasheet  
http://developer.intel.com/design/chipsets/datashts/290655.htm  
Order Number 290658  
http://developer.intel.com/design/chipsets/datashts/290658.htm  
Intel® 82801 FirmWare Hub (FWH) datasheet  
Intel® Celeron™ Processor datasheet  
Order Number 243658  
http://developer.intel.com/design/celeron/datashts/243658.htm  
Order Number 243733  
VRM 8.2 DC-DC Converter Design Guidelines  
http://developer.intel.com/design/pentiumii/xeon/designgd/243773  
.htm  
Order Number 243330  
http://developer.intel.com/design/pentiumii/applnots/243330.htm  
AP-585 Pentium® II Processor GTL+ Guidelines  
AP-587: Slot 1 Processor Power Distribution Guidelines  
Pentium® II Processor Developer's Manual  
Order Number  
http://developer.intel.com/design/celeron/applnots/243332.htm  
Order Number 243341  
http://developer.intel.com/design/PentiumII/manuals/243502.htm  
Pentium® II Processor at 350 MHz, 400 MHz and 450 MHz Order Number 243657  
datasheet  
http://developer.intel.com/design/PentiumII/datashts/243657.htm  
Intel® 82559 Fast Ethernet Multifunction PCI Controller  
http://developer.intel.com/design/network/82559.htm  
Order Number 739073  
http://developer.intel.com/design/network/applnots/739073.htm  
AP-399 82559 Printed Circuit Board Design  
Order Number 718213  
http://developer.intel.com/design/network/applnots/718213.htm  
AP-392 82559 LAN on Motherboard (LOM) Design Guide  
Intel® Networking LANSchool software site  
AC97 Specifications on Intel web site  
http://www.intel.com/network/products/lanschool.htm  
http://developer.intel.com/pc-supp/platform/ac97/index.htm  
http://developer.intel.com/ial/wfm/index.htm  
Wired for Management specifications and information  
Non-Intel Documents and Resources  
PCI Local Bus Specification, Revision 2.2  
http://www.pcisig.com/  
http://www.usb.org/  
Universal Serial Bus Specification, Revision 1.0  
Application Note  
25  
Intel-Based Electronic Classroom Student Computing Station  
Appendix B Intel-Based Electronic Classroom Schematics  
Application Note  
27  
PG.  
15  
PCI CONN 1  
DATA  
CTRL  
ADDR  
DATA  
CTRL  
ADDR  
LPC Bus  
V C C 5 2  
V C C 5 1  
V C C 5 0  
V C C 4 9  
V C C 4 8  
V C C 4 7  
V C C 4 6  
V C C 4 5  
V C C 4 4  
V C C 4 3  
V C C 4 2  
V C C 4 1  
V C C 4 0  
V C C 3 9  
V C C 3 8  
V C C 3 7  
V C C 3 6  
V C C 3 5  
V C C 3 4  
V C C 3 3  
V C C 3 2  
V C C 3 1  
V C C 3 0  
V C C 2 9  
V C C 2 8  
V C C 2 7  
V C C 2 6  
V C C 2 5  
V C C 2 4  
V C C 2 3  
V C C 2 2  
V C C 2 1  
V C C 2 0  
V C C 1 9  
V C C 1 8  
V C C 1 7  
V C C 1 6  
V C C 1 5  
V C C 1 4  
V C C 1 3  
V C C 1 2  
V C C 1 1  
V C C 1 0  
V C C 9  
R 3 2  
V 3 2  
Z 3 2  
A H 3 2  
A M 3 2  
B 3 0  
F 3 0  
A K 3 4  
D 2 8  
A J 2 9  
A M 2 8  
F 2 6  
D 2 4  
A J 2 5  
A M 2 4  
F 2 2  
D 2 0  
A J 2 1  
A M 2 0  
B 1 8  
E 1 7  
A J 1 7  
A M 1 6  
B 1 4  
E 1 3  
A J 1 3  
A M 1 2  
B 1 0  
E 9  
G N D 5 0  
D 3 0  
G N D 4 9  
A M 3 0  
G N D 4 8  
B 2 8  
G N D 4 7  
F 2 8  
G N D 4 6  
D 2 6  
G N D 4 5  
A J 2 7  
G N D 4 4  
A M 2 6  
G N D 4 3  
B 2 4  
G N D 4 2  
F 2 4  
G N D 4 1  
D 2 2  
G N D 4 0  
A J 2 3  
G N D 3 9  
A M 2 2  
G N D 3 8  
B 2 0  
G N D 3 7  
F 2 0  
G N D 3 6  
E 1 9  
G N D 3 5  
A J 1 9  
G N D 3 4  
A M 1 8  
G N D 3 3  
B 1 6  
G N D 3 2  
E 1 5  
G N D 3 1  
A J 1 5  
G N D 3 0  
A M 1 4  
G N D 2 9  
B 1 2  
G N D 2 8  
E 1 1  
G N D 2 7  
A J 1 1  
G N D 2 6  
A M 1 0  
G N D 2 5  
B 8  
G N D 2 4  
E 7  
G N D 2 3  
A J 7  
G N D 2 2  
A J 9  
A M 8  
B 6  
A M 6  
G N D 2 1  
B 4  
G N D 2 0  
D 4  
G N D 1 9  
G 5  
D 6  
G N D 1 8  
A J 5  
F 2  
L 5  
G N D 1 7  
Q 5  
G N D 1 6  
J 5  
U 5  
G N D 1 5  
Y 5  
N 5  
G N D 1 4  
S 5  
A C 5  
G N D 1 3  
A G 5  
W 5  
G N D 1 2  
A A 5  
A E 5  
A M 4  
E 5  
A K 4  
G N D 1 1  
A L 3  
G N D 1 0  
D 2  
G N D 9  
H 2  
G N D 8  
F 4  
D 1 8  
V C C 8  
G N D 7  
M 2  
K 2  
V C C 7  
G N D 6  
P 2  
V 2  
V C C 6  
G N D 5  
Z 2  
T 2  
V C C 5  
G N D 4  
A B 2  
A F 2  
A K 2  
C 3  
A D 2  
V C C 4  
G N D 3  
A H 2  
V C C 3  
G N D 2  
A M 3 4  
V C C 2  
G N D 1  
A M 2  
V C C 1  
B 2 6  
V C C 7 5  
V C C 7 4  
V C C 7 3  
V C C 7 2  
V C C 7 1  
V C C 7 0  
V C C 6 9  
V C C 6 8  
V C C 6 7  
V C C 6 6  
V C C 6 5  
V C C 6 4  
V C C 6 3  
V C C 6 2  
V C C 6 1  
V C C 6 0  
V C C 5 9  
V C C 5 8  
V C C 5 7  
V C C 5 6  
V C C 5 5  
V C C 5 4  
V C C 5 3  
Y 3 5  
A A 3 7  
K 3 2  
G N D 8 0  
Y 3 3  
F 1 4  
G N D 7 9  
A J 3 1  
A H 2 4  
A D 3 2  
D 3 2  
D 3 6  
H 3 6  
R 3 6  
V 3 6  
G N D 7 8  
Y 3 7  
G N D 7 7  
A N 3  
G N D 7 6  
A L 1  
G N D 7 5  
A J 3  
G N D 7 4  
A C 3 3  
G N D 7 3  
A 3 7  
G N D 7 2  
F 3 6  
B 2 2  
G N D 7 1  
K 3 6  
A H 3 6  
B 3 4  
G N D 7 0  
P 3 6  
G N D 6 9  
T 3 6  
F 3 4  
G N D 6 8  
X 3 6  
K 3 4  
G N D 6 7  
A F 3 6  
P 3 4  
G N D 6 6  
A K 3 6  
T 3 4  
G N D 6 5  
D 3 4  
X 3 4  
G N D 6 4  
H 3 4  
A B 3 4  
A F 3 4  
H 3 2  
M 3 2  
G N D 6 3  
M 3 4  
G N D 6 2  
R 3 4  
G N D 6 1  
V 3 4  
G N D 6 0  
Z 3 4  
V R E F 7  
V R E F 6  
V R E F 5  
V R E F 4  
V R E F 3  
V R E F 2  
V R E F 1  
V R E F 0  
G N D 5 9  
A K 2 2  
A K 1 2  
A D 6  
V 6  
A D 3 4  
G N D 5 8  
A H 3 4  
G N D 5 7  
B 3 2  
G N D 5 6  
F 3 2  
F
G T L R E  
G N D 5 5  
R 6  
P 3 2  
G N D 5 4  
T 3 2  
K 4  
G N D 5 3  
F 1 8  
E 3 3  
X 3 2  
G N D 5 2  
A B 3 2  
G N D 5 1  
A F 3 2  
V 2 _ 5  
V 1 _ 5  
Z 3 6  
A D 3 6  
A B 3 6  
V _ C M O S  
V C M O S  
5
6
7
8
4
3
2
1
S
V C M O  
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
C 2 0 7 A  
C 2 0 4 A  
C 2 0 9 A  
0 . 1 U F  
C 6 A  
C 2 0 6 A  
2
1
+
1
2
+
1
2
U
L 1 E _ S P  
V D D 3 _ 3 [ 7 ]  
V D D 3 _ 3 [ 6 ]  
V D D 3 _ 3 [ 5 ]  
V D D 3 _ 3 [ 4 ]  
V D D 3 _ 3 [ 3 ]  
V D D 3 _ 3 [ 2 ]  
V D D 3 _ 3 [ 1 ]  
V D D 3 _ 3 [ 0 ]  
V S S 3 _ 3 [ 7 ]  
4 7  
4 4  
V S S 3 _ 3 [ 6 ]  
3 8  
3 3  
2 7  
2 1  
1 0  
9
4 1  
V S S 3 _ 3 [ 5 ]  
3 5  
V S S 3 _ 3 [ 4 ]  
2 4  
V S S 3 _ 3 [ 3 ]  
1 7  
V S S 3 _ 3 [ 2 ]  
1 4  
V S S 3 _ 3 [ 1 ]  
6
V S S 3 _ 3 [ 0 ]  
2
5
+
1
2
2
1
A L X T  
+
1
2
2
1
V C C _ C O R E [ 1 3 ]  
V C C _ C O R E [ 1 2 ]  
V C C _ C O R E [ 1 1 ]  
V C C _ C O R E [ 1 0 ]  
V C C _ C O R E [ 9 ]  
V C C _ C O R E [ 8 ]  
V C C _ C O R E [ 7 ]  
V C C _ C O R E [ 6 ]  
V C C _ C O R E [ 5 ]  
V C C _ C O R E [ 4 ]  
V C C _ C O R E [ 3 ]  
V C C _ C O R E [ 2 ]  
V C C _ C O R E [ 1 ]  
V C C _ C O R E [ 0 ]  
V S S [ 2 3 ]  
N 1 3  
F 7  
V S S [ 2 2 ]  
F 8  
N 1 4  
V S S [ 2 1 ]  
M 1 0  
F 1 0  
F 1 4  
F 1 6  
F 1 7  
V 7  
V S S [ 2 0 ]  
M 1 1  
V S S [ 1 9 ]  
M 1 2  
V S S [ 1 8 ]  
M 1 3  
V S S [ 1 7 ]  
M 1 4  
V S S [ 1 6 ]  
V 8  
L 1 0  
V S S [ 1 5 ]  
L 1 1  
V 9  
V S S [ 1 4 ]  
V 1 0  
V 1 4  
V 1 5  
V 1 6  
V 1 7  
L 1 2  
V S S [ 1 3 ]  
L 1 3  
V S S [ 1 2 ]  
L 1 4  
V S S [ 1 1 ]  
K 1 0  
V S S [ 1 0 ]  
K 1 1  
V S S [ 9 ]  
K 1 2  
V S S [ 8 ]  
K 1 3  
V C C 1 _ 8 [ 2 ]  
V S S [ 7 ]  
K 1 4  
U 1 8  
P 6  
V C C 1 _ 8 [ 1 ]  
V C C 1 _ 8 [ 0 ]  
V S S [ 6 ]  
E 2 2  
V S S [ 5 ]  
C 1 9  
B 2 0  
V S S [ 4 ]  
Y 1 9  
V S S [ 3 ]  
J 2 2  
V S S [ 2 ]  
N 2 2  
V S S [ 1 ]  
V 1 8  
V S S [ 0 ]  
Y 2 2  
V S S [ 4 5 ]  
J 2  
V S S [ 4 4 ]  
L 4  
V S S [ 4 3 ]  
M 1  
V C C 3 _ 3 [ 1 5 ]  
V C C 3 _ 3 [ 1 4 ]  
V C C 3 _ 3 [ 1 3 ]  
V C C 3 _ 3 [ 1 2 ]  
V C C 3 _ 3 [ 1 1 ]  
V S S [ 4 2 ]  
R 1 8  
J 1 8  
F 1 8  
G 2 1  
L 2 1  
P 3  
V S S [ 4 1 ]  
R 6  
V S S [ 4 0 ]  
V 3  
V S S [ 3 9 ]  
W 1 4  
V S S [ 3 8 ]  
W 1 0  
V S S [ 3 7 ]  
W 6  
V C C 3 _ 3 [ 1 0 ]  
V C C 3 _ 3 [ 9 ]  
V C C 3 _ 3 [ 8 ]  
V C C 3 _ 3 [ 7 ]  
V C C 3 _ 3 [ 6 ]  
V C C 3 _ 3 [ 5 ]  
V C C 3 _ 3 [ 4 ]  
V C C 3 _ 3 [ 3 ]  
V C C 3 _ 3 [ 2 ]  
V C C 3 _ 3 [ 1 ]  
V C C 3 _ 3 [ 0 ]  
V S S [ 3 6 ]  
B 2  
A A 1 6  
V S S [ 3 5 ]  
A A 1 2  
F 6  
V S S [ 3 4 ]  
K 6  
A A 8  
V S S [ 3 3 ]  
A A 4  
F 9  
V S S [ 3 2 ]  
F 1 5  
G 3  
L 3  
A C 1  
V S S [ 3 1 ]  
P 1 0  
V S S [ 3 0 ]  
P 1 1  
V S S [ 2 9 ]  
P 1 2  
C 1 5  
C 7  
C 1 1  
D 4  
V S S [ 2 8 ]  
P 1 3  
V S S [ 2 7 ]  
P 1 4  
V S S [ 2 6 ]  
N 1 0  
V S S [ 2 5 ]  
N 1 1  
V S S [ 2 4 ]  
N 1 2  
P M H C G O  
3 3 U F  
+
1
2
C 2 2 2 A  
0 . 1 U F  
C 2 1 6 A  
0 . 0 1 U F  
C 2 1 7 A  
V S S D A C A  
A B 2 2  
V S S D A  
A A 2 2  
V S S [ 6 1 ]  
A A 1 9  
V S S [ 6 0 ]  
T 1 8  
V S S [ 5 9 ]  
P 1 8  
V S S [ 5 8 ]  
K 1 8  
V S S [ 5 7 ]  
G 1 8  
V C C D A C A 2  
V C C D A C A 1  
V S S [ 5 6 ]  
A B 2 1  
B 2 1  
V S S [ 5 5 ]  
B 1 7  
A B 2 3  
A C 2 0  
E 1 9  
V S S [ 5 4 ]  
E 1 6  
V S S [ 5 3 ]  
B 1 3  
V C C D A  
V S S [ 5 2 ]  
E 1 1  
V S S [ 5 1 ]  
B 9  
V S S [ 5 0 ]  
B 5  
V C C B A  
V C C H A  
V S S [ 4 9 ]  
A 1  
V S S [ 4 8 ]  
E 2  
V S S [ 4 7 ]  
G 6  
V S S [ 4 6 ]  
U 6  
J 6  
V S S B A  
E 1 8  
V S S H A  
T 6  
5
6
7
8
4
3
2
1
0 3 U P _ S G R  
1 3 U P _ S G R  
5
6
7
8
4
3
2
1
6 2 U P _ S G R  
8 2 P U S _ R G  
E C C 7  
E C C 6  
E C C 5  
E C C 4  
E C C 3  
E C C 2  
E C C 1  
E C C 0  
D Q 6 3  
D Q 6 2  
D Q 6 1  
D Q 6 0  
D Q 5 9  
D Q 5 8  
D Q 5 7  
D Q 5 6  
D Q 5 5  
D Q 5 4  
D Q 5 3  
D Q 5 2  
D Q 5 1  
D Q 5 0  
D Q 4 9  
D Q 4 8  
D Q 4 7  
D Q 4 6  
D Q 4 5  
D Q 4 4  
D Q 4 3  
D Q 4 2  
D Q 4 1  
D Q 4 0  
D Q 3 9  
D Q 3 8  
D Q 3 7  
D Q 3 6  
D Q 3 5  
D Q 3 4  
D Q 3 3  
D Q 3 2  
D Q 3 1  
D Q 3 0  
D Q 2 9  
D Q 2 8  
D Q 2 7  
D Q 2 6  
D Q 2 5  
D Q 2 4  
D Q 2 3  
D Q 2 2  
D Q 2 1  
D Q 2 0  
D Q 1 9  
D Q 1 8  
D Q 1 7  
D Q 1 6  
D Q 1 5  
D Q 1 4  
D Q 1 3  
D Q 1 2  
D Q 1 1  
D Q 1 0  
1 3 7  
N C 1 7  
1 6 4  
1 3 6  
N C 1 6  
1 0 6  
1 4 6  
N C 1 5  
1 4 5  
1 0 5  
N C 1 4  
5 3  
1 3 5  
N C 1 3  
1 3 4  
5 2  
N C 1 2  
2 2  
2 1  
1 0 9  
N C 1 1  
1 0 8  
N C 1 0  
S M _ M D 6 1 3 6 1  
8 0  
N C 9  
N C 8  
N C 7  
N C 6  
N C 5  
N C 4  
N C 3  
N C 2  
N C 1  
S M _ M D 6 2  
1 6 0  
6 2  
6 1  
5 1  
5 0  
4 8  
4 4  
3 1  
2 5  
2 4  
S M _ M D 6 1  
1 5 9  
S M _ M D 6 1 0 5 8  
S M _ M D 5 1 9 5 6  
S M _ M D 5 1 8 5 5  
S M _ M D 5 7  
1 5 4  
S M _ M D 5 6  
1 5 3  
S M _ M D 5 1 5 5 1  
S M _ M D 5 1 4 5 0  
S M _ M D 5 1 3 4 9  
W P  
8 1  
S M _ M D 5 2  
1 4 4  
S A 2  
S A 1  
S A 0  
S M _ M D 5 1  
1 4 2  
1 6 7  
1 6 6  
1 6 5  
S M _ M D 5 1 0 4 1  
S M _ M D 4 1 9 4 0  
S M _ M D 4 1 8 3 9  
R E G E  
1 4 7  
S M _ M D 4 7  
1 0 4  
S M B C L K  
8 3  
S M _ M D 4 6  
1 0 3  
S M B D A T A  
S M _ M D 4 1 5 0 1  
S M _ M D 4 1 4 0 0  
S M _ M D 4 9 3 9  
8 2  
C K E 1  
6 3  
S M _ C K E 1  
S M _ C K E  
C K E 0  
S M _ M D 4 2  
9 8  
0
1 2 8  
S M _ M D 4 1  
9 7  
R A S #  
1 1 5  
S M _ M D 4 9 0 5  
S M _ M D 3 9 9 4  
S M _ M D 3 9 8 3  
C A S #  
1 1 1  
W E #  
2 7  
S 3 #  
S M _ M D 3 7  
9 2  
1 2 9  
S 2 #  
4 5  
S 1 #  
S M _ M D 3 6  
9 1  
S M _ M D 3 8 5 9  
S M _ M D 3 8 4 8  
S M _ M D 3 8 3 7  
1 1 4  
S M _ C S # 1  
S M _ C S # 0  
S 0 #  
3 0  
D Q M B 7  
1 3 1  
S M _ M D 3 2  
8 6  
S M _ D Q M 7  
S M _ D Q M 6  
S M _ D Q M 5  
S M _ D Q M 4  
S M _ D Q M 3  
S M _ D Q M 2  
S M _ D Q M 1  
S M _ D Q M 0  
D Q M B 6  
S M _ M D 3 1  
7 7  
1 3 0  
D Q M B 5  
1 1 3  
S M _ M D 3 7 0 6  
S M _ M D 2 7 9 5  
S M _ M D 2 7 8 4  
D Q M B 4  
1 1 2  
D Q M B 3  
4 7  
D Q M B 2  
S M _ M D 2 7  
7 2  
4 6  
D Q M B 1  
2 9  
S M _ M D 2 6  
7 1  
D Q M B 0  
S M _ M D 2 7 5 0  
S M _ M D 2 6 4 9  
S M _ M D 2 6 3 7  
2 8  
B A 1  
3 9  
S M _ B S 1  
S M _ B S  
B A 0  
S M _ M D 2 2  
6 6  
0
1 2 2  
S M _ M D 2 1  
6 5  
A 1 3  
1 3 2  
S M _ M D 2 6 0 0  
S M _ M D 1 5 9 8  
S M _ M D 1 5 8 7  
A 1 2  
1 2 6  
A 1 1  
1 2 3  
A 1 0  
S M _ M A A 1 1  
S M _ M A A 1  
S M _ M A  
S M _ M D 1 7  
5 6  
0
3 8  
A 9  
S M _ M D 1 6  
5 5  
9 A  
1 2 1  
A 8  
S M _ M D 1 2 5 0  
S M _ M D 1 1 4 9  
S M _ M D 1 1 3 7  
3 7  
S M _ M A A 8  
S M _ M A A 7  
S M _ M A A 6  
S M _ M A  
A 7  
1 2 0  
A 6  
3 6  
A 5  
S M _ M D 1 2  
1 6  
5 A  
4 A  
1 1 9  
A 4  
S M _ M D 1 1  
1 5  
S M _ M A  
3 5  
A 3  
S M _ M D 1 1 0 4  
S M _ M D 9 1 3  
S M _ M D 8 1 1  
1 1 8  
S M _ M A A 3  
S M _ M A A 2  
S M _ M A A 1  
S M _ M A  
D Q 9  
A 2  
3 4  
D Q 8  
D Q 7  
D Q 6  
D Q 5  
D Q 4  
D Q 3  
D Q 2  
D Q 1  
D Q 0  
A 1  
1 1 7  
A 0  
7
6
S M _ M D  
S M _ M D  
0 A  
1 0  
9
3 3  
C L K 3  
1 6 3  
S M _ M D 5 8  
S M _ M D 4 7  
S M _ M D 3 5  
M E M C L K 3  
M E M C L K 2  
M E M C L K 1  
M E M C L  
C L K 2  
7 9  
C L K 1  
1 2 5  
C L K 0  
2
1
S M _ M D  
S M _ M D  
0 K  
4
3
4 2  
S M _ M D 0 2  
V C C 1 _ 8 _ 7  
V C C 1 _ 8 _ 6  
V C C 1 _ 8 _ 5  
V C C 1 _ 8 _ 4  
V C C 1 _ 8 _ 3  
V C C 1 _ 8 _ 2  
V C C 1 _ 8 _ 1  
J 1 6  
H 1 6  
L 1 5  
G 1 5  
K 1 4  
H 1 4  
G 1 3  
V S S 1 3  
K 1 5  
V S S 1 2  
G 1 4  
V S S 1 1  
K 1 0  
V S S 1 0  
J 1 0  
V C C 3 _ 3 _ 1 7  
V C C 3 _ 3 _ 1 6  
V C C 3 _ 3 _ 1 5  
V C C 3 _ 3 _ 1 4  
V C C 3 _ 3 _ 1 3  
V C C 3 _ 3 _ 1 2  
V C C 3 _ 3 _ 1 1  
V C C 3 _ 3 _ 1 0  
V C C 3 _ 3 _ 9  
V C C 3 _ 3 _ 8  
V C C 3 _ 3 _ 7  
V C C 3 _ 3 _ 6  
V C C 3 _ 3 _ 5  
V C C 3 _ 3 _ 4  
V C C 3 _ 3 _ 3  
V C C 3 _ 3 _ 2  
V C C 3 _ 3 _ 1  
V S S 9  
E 1 3  
N 1 3  
N 5  
H 1 0  
V S S 8  
K 9  
V S S 7  
J 9  
V S S 6  
H 9  
D 1 6  
E 5  
V S S 5  
K 8  
V S S 4  
J 8  
E 6  
V S S 3  
A 5  
H 8  
V S S 2  
C 8  
G 3  
V S S 1  
R 2  
C 1 1  
M 1 4  
T 1 6  
R 1 3  
U 1 0  
T 7  
P 6  
G 5  
E 3  
A
C
5 V R E F  
C 1 5  
V C C S U S 1  
L 1  
V C C S U S 2  
N 1  
V C C R T C  
G 1  
SLP_S5#  
J P 1 4 _ P U  
+
1
2
C
A
V B A T  
+
1
2
3
4
8
7
6
5
F G P I 2 _ P D  
1
8
7
6
5
F G P I 3 2 _ P D  
F G P I 4 3 _ P D  
I C _ P D 4  
0 . 1 U F  
0 . 1 U F  
C 3 2 3 A  
C 2 2 9 A  
C 2 9 7 A  
0 . 1 U F  
0 . 1 U F  
C 2 4 6 A  
0 . 1 U F  
C 2 8 7 A  
2 . 2 U F  
+
1
2
C 9 9 A  
V C C 3  
V C C 2  
V C C 1  
A V S S  
4 0  
9 3  
6 5  
5 3  
G N D 4  
7 6  
G N D 3  
6 0  
V T R  
V R E F  
G N D 2  
3 1  
1 8  
4 4  
G N D 1  
7
U P _ T A S S T S U  
key  
0 . 0 4 7 U F  
C 1 8 6 A  
4 7 0  
R 1 3 2 A  
1 0 K  
R 1 3 7 A  
5 . 6 K  
R 1 3 4 A  
0 . 0 4 7 U F  
C 1 8 7 A  
4 7 0  
V C C  
G N D  
7
1 4  
R 1 0 1 A  
1 0 K  
R 1 3 8 A  
R 1 3 5 A  
5 . 6 K  
4 7 P F  
C 9 8 A  
4 7 P F  
4 7 P F  
4 7 P F  
C 8 A  
C 1 6 A  
C 1 3 A  
2
1
2
1
0 . 1 U F  
0 . 1 U F  
6 8 U F  
C 1 2 A  
C 9 A  
6 8 U F  
+
+
1
2
C 2 0 2 A  
1
2
C 2 0 1 A  
2
1
1 8 0 P F  
1 8 0 P F  
C 9 5 A  
C 9 1 A  
1 8 0 P F  
5
6
7
8
4
3
2
1
1 8 0 P F  
C 9 3 A  
1 8 0 P F  
C 8 9 A  
1 8 0 P F  
C 8 8 A  
1 8 0 P F  
C 9 0 A  
1 8 0 P F  
C 9 4 A  
5
6
7
8
4
3
2
1
C 9 2 A  
1 8 0 P F  
C 9 6 A  
1 8 0 P F  
C 9 7 A  
1 8 0 P F  
5
6
7
8
4
3
2
1
C 1 8 9 A  
1 8 0 P F  
1 8 0 P F  
C 1 9 0 A  
C 1 9 2 A  
1 8 0 P F  
C 1 9 4 A  
1 8 0 P F  
C 1 9 7 A  
1 8 0 P F  
C 1 9 3 A  
1 8 0 P F  
C 1 9 6 A  
5
6
7
8
4
3
2
1
1 0 0 P F  
C 3 1 0 A  
1 0 0 P F  
C 3 6 9 A  
1 0 0 P F  
C 3 6 8 A  
1 0 0 P F  
C 3 1 1 A  
1 0 0 P F  
C 3 3 0 A  
1 0 0 P F  
C 3 0 9 A  
1 0 0 P F  
C 3 2 9 A  
1 0 0 P F  
C 3 1 5 A  
1 0 0 P F  
C 3 2 8 A  
1 0 0 P F  
C 3 1 3 A  
1 0 0 P F  
C 3 2 7 A  
1 0 0 P F  
C 3 1 4 A  
1 0 0 P F  
C 3 2 6 A  
1 0 0 P F  
C 3 1 2 A  
1 0 0 P F  
C 3 2 5 A  
1 0 0 P F  
C 3 1 6 A  
1 . 0 U F  
C 3 7 4 A  
D
S
1
7 0 0 2 2 N L T  
0 . 0 1 U F  
0 . 0 1 U F  
C 1 9 5 A  
C 1 9 1 A  
0 . 0 1 U F  
0 . 0 1 U F  
C 1 9 8 A  
C 1 9 9 A  
5
6
7
8
4
3
2
1
4 7 P F  
4 7 P F  
4 7 P F  
C 1 8 2 A  
C 7 9 A  
C 1 7 8 A  
2
1
4 7 P F  
C 1 7 9 A  
P S / 2 K y b d  
P S / 2 M s e  
0 . 1 U F  
2 _ S P P  
C 1 A  
2
1
D
4 7 0 P F  
4 7 0 P F  
4 7 0 P F  
4 7 0 P F  
4 7 0 P F  
4 7 0 P F  
1 5  
1 3  
1 1  
9
1 6  
1 4  
1 2  
1 0  
8
C 2 A  
C 5 A  
C 1 7 6 A  
7
C 1 7 7 A  
5
6
3
4
C 4 A  
C 3 A  
1
2
5
6
7
8
4
3
2
1
1 0 P F  
1 0 P F  
C 1 0 1 A  
C 2 0 8 A  
2
1
CRT5V_F  
2
1
1 0 P F  
1 0 P F  
C 1 1 6 A  
C 1 1 2 A  
3 . 3 P F  
C 1 1 1 A  
3 . 3 P F  
C 1 0 6 A  
3 . 3 P F  
3 . 3 P F  
3 . 3 P F  
C 1 0 3 A  
3 . 3 P F  
3 . 3 P F  
C 1 1 9 A  
C 1 2 2 A  
C 1 0 0 A  
3 . 3 P F  
C 1 0 5 A  
3 . 3 P F  
C 1 0 9 A  
3 . 3 P F  
C 1 0 4 A  
C 1 0 2 A  
0 . 1 U F  
C 2 2 7 A  
5
6
7
8
4
3
2
1
V C C  
G N D  
5
8
V S S [ 3 1 ]  
L 1 1  
V S S [ 3 0 ]  
L 6  
V S S [ 2 9 ]  
H 1 1  
V S S [ 2 8 ]  
H 1 0  
V S S [ 2 7 ]  
H 9  
V C C [ 2 5 ]  
V C C [ 2 4 ]  
V C C [ 2 3 ]  
V C C [ 2 2 ]  
V C C [ 2 1 ]  
V C C [ 2 0 ]  
V C C [ 1 9 ]  
V C C [ 1 8 ]  
V C C [ 1 7 ]  
V C C [ 1 6 ]  
V C C [ 1 5 ]  
V C C [ 1 4 ]  
V C C [ 1 3 ]  
V C C [ 1 2 ]  
V C C [ 1 1 ]  
V C C [ 1 0 ]  
V C C [ 9 ]  
L 1 0  
L 9  
V S S [ 2 6 ]  
G 1 1  
V S S [ 2 5 ]  
G 1 0  
L 5  
V S S [ 2 4 ]  
G 9  
L 4  
V S S [ 2 3 ]  
G 8  
K 1 1  
K 1 0  
K 9  
K 8  
K 7  
K 6  
K 5  
K 4  
J 1 1  
J 1 0  
J 9  
V S S [ 2 2 ]  
G 7  
V S S [ 2 1 ]  
F 1 1  
V S S [ 2 0 ]  
F 1 0  
V S S [ 1 9 ]  
F 9  
V S S [ 1 8 ]  
F 8  
V S S [ 1 7 ]  
F 7  
V S S [ 1 6 ]  
F 6  
V S S [ 1 5 ]  
F 5  
V S S [ 1 4 ]  
F 4  
V S S [ 1 3 ]  
E 1 1  
V S S [ 1 2 ]  
E 1 0  
J 8  
V S S [ 1 1 ]  
E 9  
J 7  
V S S [ 1 0 ]  
E 8  
V C C [ 8 ]  
J 6  
V S S [ 9 ]  
E 7  
V C C [ 7 ]  
J 5  
V S S [ 8 ]  
E 6  
V C C [ 6 ]  
H 8  
H 7  
H 6  
H 5  
G 6  
G 5  
E 1 2  
V S S [ 7 ]  
E 5  
V C C [ 5 ]  
V S S [ 6 ]  
E 4  
V C C [ 4 ]  
V S S [ 5 ]  
D 1 1  
V C C [ 3 ]  
V S S [ 4 ]  
D 8  
V C C [ 2 ]  
V S S [ 3 ]  
D 7  
V C C [ 1 ]  
V S S [ 2 ]  
D 6  
V C C [ 0 ]  
V S S [ 1 ]  
D 5  
V S S [ 0 ]  
D 4  
V C C P P [ 5 ]  
P 2  
N 6  
K 3  
E 1  
A 7  
A 3  
V C C P P [ 4 ]  
V C C P P [ 3 ]  
V C C P P [ 2 ]  
V C C P P [ 1 ]  
V C C P P [ 0 ]  
V S S P P [ 5 ]  
N 1  
V S S P P [ 4 ]  
M 6  
V S S P P [ 3 ]  
K 2  
V S S P P [ 2 ]  
E 2  
V S S P P [ 1 ]  
B 7  
V S S P P [ 0 ]  
B 3  
V C C P T  
A 1 1  
V S S P T  
C 1 0  
V C C P L [ 3 ]  
V C C P L [ 2 ]  
V C C P L [ 1 ]  
V C C P L [ 0 ]  
P 1 2  
N 8  
V S S P L [ 3 ]  
N 1 2  
K 1 3  
G 1 3  
V S S P L [ 2 ]  
P 8  
V S S P L [ 1 ]  
K 1 2  
V S S P L [ 0 ]  
G 1 4  
0 . 1 U F  
C 2 6 5 A  
2 2 P F  
C 2 6 9 A  
2 2 P F  
C 3 3 1 A  
2
1
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
0 . 1 U F  
C 1 6 5 A  
C 1 8 4 A  
C 2 6 1 A  
C 2 5 7 A  
C 1 8 0 A  
C 3 3 4 A  
4 . 7 U F  
4 . 7 U F  
+
1
2
C 2 5 5 A  
+
1
C 6 8 A  
2
J P 1 2 _ P U  
J P 1 1 _ P U  
J P 7 _ P U  
A C T _ C R  
R D C  
8
R D C  
T D  
T D C  
1 1  
C
S H L D 2  
1 8  
S H L D 1  
1 7  
5 4 - R J  
R X C  
2
D P C _ R X  
T X C  
1
D P _ C T X  
R J 7 8 _ P D  
R J 4 5 _ P D  
0 . 1 U F  
C 2 6 8 A  
0 . 1 U F  
C 2 6 6 A  
1 0 0 U F  
2 2 U F  
+
+
1
2
1
2
C 2 2 5 A  
C 7 4 A  
1 0 0 U F  
1 . 0 U F  
+
1
2
C 2 7 0 A  
0 . 1 U F  
C 4 3 A  
C 6 5 A  
+
1
2
2
+
1
1 0 0 U F  
+
1
2
G
G
C 1 5 9 A  
+
1
2
2
1 . 0 U F  
C 5 7 A  
+
1
1 0 0 U F  
+
1
2
C 5 9 A  
1
9 0 3 4 T L B T M M  
2
3
C
E
1 0 0 U F  
+
1
2
C 7 6 A  
G N D  
1
V C C  
G N D  
7
1 4  
2 2 U F  
2
+
1
C 7 1 A  
2 7 0 0 U F  
2 7 0 0 U F  
2 7 0 0 U F  
2 7 0 0 U F  
D 1  
D 2  
D 3  
D 4  
S 1  
S 2  
S 3  
G 1  
D 1  
D 2  
D 3  
D 4  
S 1  
S 2  
S 3  
G 1  
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
+
1
2
2
C 5 4 A  
+
S I 4 4 1 0 D Y  
S I 4 4 1 0 D Y  
1
C 1 2 8 A  
+
D 1  
D 2  
D 3  
D 4  
S 1  
1
S 2  
D 1  
D 2  
D 3  
D 4  
S 1  
1
S 2  
8
7
6
5
8
7
6
5
1
2
2
2
C 2 8 A  
S 3  
3
G 1  
S 3  
3
G 1  
+
4
4
1
2
2
S I 4 4 1 0 D Y  
S I 4 4 1 0 D Y  
C 5 8 A  
2 7 0 0 U F  
+
1
C 3 1 A  
S E N S E  
6
G N D  
3
P V C C  
V C C  
S G N D  
4
2
5
2
P V 1  
S S  
9
0 . 1 U F  
C O M P  
1 0  
C 1 9 A  
C 1 7 A  
0 . 0 1 U F  
1 2 0 0 U F  
1 2 0 0 U F  
1 2 0 0 U F  
1 2 0 0 U F  
+
P M R V C O R _  
1
C 7 A  
2
2
2
2
2
1 5 0 P F  
+
1
C 2 9 A  
C 1 8 A  
+
1
C 2 6 A  
1 . 0 U H - 6 . 8 A  
+
L 8 A  
1
C 3 0 A  
1 0 U F  
+
1
C 2 7 A  
0 . 1 U F  
C 2 2 A  
3 3 0  
R 9 8 A  
3 3 0  
R 9 7 A  
1 6 V  
1 0 U F  
+
1
2
C 2 9 2 A  
0 . 1 U F  
4 . 7 K  
R 1 7 2 A  
C 2 7 9 A  
D P _ F P  
3 9 N 0 2 4  
3
2
C
E
V C C  
G N D  
7
1 4  
V C C  
G N D  
7
1 4  
2
1
E D S B V L 3  
RP62A  
8
7
6
5
1
2
3
4
V C C  
G N D  
7
1 4  
V C C  
G N D  
7
1 4  
1 4  
1 4  
7
7
V C C  
G N D  
7
1 4  
1 4  
7
1 4  
1 4  
7
7
+
1
2
1 4  
7
V C C  
G N D  
7
1 4  
V C C  
G N D  
7
V C C  
G N D  
7
1 4  
1 4  
1 4  
7
1 4  
7
1 4  
7
1 4  
7
V C C  
G N D  
V C C  
G N D  
7
V C C  
G N D  
7
1 4  
7
1 4  
1 4  
V C C  
G N D  
V C C  
G N D  
V C C  
G N D  
7
1 4  
7
1 4  
7
1 4  
1
2
C 3 1 7 A  
C 3 2 4 A  
2 U 2 F .  
2
+
1
8 0 C A  
C 3 7 2 A  
A 1 C 8  
F
2 2 U  
+
2
1
A 4 C 8  
C 3 2 1 A  
C 3 6 7 A  
1 U 0 F .  
1 U 0 F .  
3 3 A C  
6 0 3 A C  
F
2 2 U  
2
+
1
A 2 C 6  
F
2 2 U  
+
2
1
6 9 C  
A
F
2 2 U  
2
+
1
A 0 C 7  
F
2 2 U  
+
1
2
8 5 C A  
F
2 2 U  
2
+
1
1 6 C 2 A  
+
1
2
配单直通车
GD82559C产品参数
型号:GD82559C
是否无铅: 不含铅
是否Rohs认证: 不符合
生命周期:Obsolete
Reach Compliance Code:unknown
HTS代码:8542.31.00.01
风险等级:5.81
Is Samacsys:N
JESD-30 代码:S-PBGA-B196
端子数量:196
封装主体材料:PLASTIC/EPOXY
封装代码:BGA
封装等效代码:BGA196,14X14,40
封装形状:SQUARE
封装形式:GRID ARRAY
电源:3.3,3.3/5 V
认证状态:Not Qualified
子类别:Serial IO/Communication Controllers
表面贴装:YES
技术:CMOS
端子形式:BALL
端子节距:1 mm
端子位置:BOTTOM
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1
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