GM5115芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

Genesis Microchip Publication

PRELIMINARY DATA SHEET

gm5115/gm5115-H

gm5125/gm5125-H

OnPanel LCD Panel Controller

*** Genesis Microchip Confidential ***

NOTE: Sections in this data sheet that mention HDCP apply only to the HDCP-enabled chip

versions (gm5115-H and gm5125-H). All other sections apply to all chip versions (gm5115,

gm5115-H, gm5125, and gm5125-H).

Publication number: C5115-DAT-01H

Publication date: June 2002

Genesis Microchip Inc.

2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365

165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422

1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: (91)-80-526-3878, Fax: (91)-80-529-6245

4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: 886-2-2791-0118 Fax: 886-2-2791-0196

143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942

Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874

2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759

www.genesis-microchip.com

/

info@genesis-microchip.com

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Trademarks: RealColor, Real Recovery, and Ultra-Reliable DVI are trademarks of Genesis Microchip Inc.

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without

notice. It is the customer’s responsibility to obtain the most recent revision of the document. Genesis

Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or

omissions that may appear in this document.

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June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

Revision History

gm5115/25 Preliminary Data Sheet

Document

Description

Date

•

Initial release.

C5115-DAT-01A

C5115-DAT-01B

March 2001

•

In Table 18 corrected description of OSC_SEL (on pin ROM_ADDR13). It should be set to 1 to

June 2001

indicate usage of a single-ended clock oscillator.

•

Corrected image and orientation of logo in pin out diagram Figure 2.

Added section 4.11.3.

Replaced all occurrences of CVDD with CVDD_2.5, including pin numbers 26, 88, 134 and 203

to make them consistent with the names of other 2.5V voltage supply signals.

Pin number 205 name changed from GPIO16/HFS to GPIO16/HFSn and all occurrences of

HFS replaced with HFSn to reflect the fact that this signal is active low.

Added description of 2-wire serial protocol in section 4.17.2 and Table 24.

Removed “Read with Increment” operation description.

C5115-DAT-01C

C5115-DAT-01D

July 2001

•

Corrected mechanical specification in Figure 32.

Changes to Table 21 – DC Characteristics:

- Maximum voltage for 5V-tolerance inputs is 5.5V.

- Added maximum current requirements.

•

Added description of OCM Standalone configuration Figure 26.

Added Figure 22 – Panel Power Sequencing.

•

Added description of gm5125 (SXGA device).

C5115-DAT-01E

August 2001

Pin names changed to reflect alternate hard-wired functions:

- pin 50 from GPIO11 to GPIO11/ROM_WEn,

- pin 51 from GPIO12 to GPIO12/NVRAM_SDA,

- pin 52 from GPIO13 to GPIO13/NVRAM_SCL,

- pin 6 from DDC_SCL to GPIO14/DDC_SCL,

- pin 7 from DDC_SDA to GPIO15/DDC_SDA,

- pin 46 from GPIO6 to GPIO6/TCON_SHC,

- pin 47 from GPIO7 to GPIO7/TCON_TDIV.

•

Removed description of 6-wire host interface, since this is not recommended operation. Pin 1

name changed from GPIO17/HDATA0 to GPIO17, and similarly for pins 206, 207 and 208.

Corrected maximum ADC sampling frequency in Table 15 and maximum ADC_CLK frequency

in Table 22 to 162.5MHz.

•

Added section 4.5 Test Pattern Generator.

Added description of TCON_SHC and TCON_TDIV in section 4.13.1.

Clarifications to section 4.1 describing clock generation, section 4.7.2 describing sRGB support,

and section 4.15.3 describing GPIOs.

•

Removed mention of row attributes in Figure 25.

gm5115/25 OSD controller does not have row attributes.

Corrected Table 21, Note 3. Pins VDD1_ADC_2.5, VDD2_ADC_2.5, VDD_RX0_2.5,

VDD_RX1_2.5 and VDD_RX2_2.5 are digital 2.5V supplies, not analog.

Changed signal names SCL and SDA to HCLK and HFSn, respectively in Figure 29, Figure 30,

and Figure 31.

•

Added note on Front Cover regarding HDCP enabled versions.

Added section 4.12 - Energy Spectrum Management (ESM).

Added clarification in section 4.13.1 indicating that single bus configurations are supported in

XGA column drivers only.

C5115-DAT-01F

October 2001

•

In section 4.16, clarified that ROM_ADDR[15:0] have internal 60KΩ pull-down resistor.

Changes to Table 20 – Absolute Maximum Ratings:

– Renamed parameters θ_{JA_XGA}, θ_{JA_SXGA}, θ_{JC_XGA}and θ_{JC_SXGA}to θ_{JA_5115}, θ_{JA_5125}, θ_{JC_5115}and

θ_{JC_5125}and revised their values.

– Added note (4) regarding the maximum case temperature.

Changes to Table 21 – DC Characteristics:

•

– Renamed parameters P₅₁₁₅and P₅₁₂₅and revised their values.

– Revised the values of P_LPand I_LP.

– Renamed parameters I₅₁₁₅, I_{5115_2.5_VDD}, etc.

– Added note (6).

Removed the clock speed column from section 6 – Ordering Information and added the ordering

information for gm5115-H and gm5125-H.

•

Replaced occurrences of TMDS with DVI.

Changed TCON_RCLK to TCON_ROWCLK in Figure 2 and in Table 7.

• Changed RCLK to ROWCLK in 4.13.2 and in Figure 24.

iii

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

• Added section 4.15.3 - In-System-Programming (ISP) of FLASH ROM Devices.

• Added section 4.15.4 - UART Interface.

C5115-DAT-01G

March 2002

• Added section 4.15.5 - DDC2Bi Interface.

• In sections 4.3.2 - ADC Characteristics and 4.4.1 - DVI Receiver Characteristics clarified that

input formats with resolutions higher than that supported by the LCD panel are supported as

recovery modes only.

•

Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS respectively

Pins 138 ~ 141: changed xxx_DDDS or xxxx_DDDS to xxx_SDDS or xxxx_SDDS respectively

Pins 147 ~ 148: changed xxx_DPLL to xxx_RPLL

D5115-DAT-01H

June 2002

iv

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Related documents

Chip documents

C5115-PBR-01

C5125-PBR-01

C5115-APB-01

C5115-APB-02

C5115-TOP-01

C5115-DSL-01

C5115-DSR-01

C5115-DSR-02

C5115-APN-03

C5115-APN-04

C5115-APN-06

C5115-APN-07

C5115-APN-08

C5115-APN-10

Preliminary Product Brief gm5115

Preliminary Product Brief gm5125

gm5115 Product Family On-chip Microcontroller (OCM) Firmware Configurations

gm5115 Product Family Support for Standard RGB (sRGB)

gm5115 Theory of Operation

gm5115 Register Listing

gm5115 TCON Programming Guide

gm5115 Input Processing Programming Guide

gRGB Support in gm5115 Family Products

gm5115 Family OCM User Manual

Energy Spectrum Management (ESM) using gm5115 family OnPanel Controllers

gm5115 Family IBIS Models

gm5115 Monitor Standby Power Consumption

gm5115 Enhanced Auto-Clock Configuration

Reference design documents

B0124-GUD-01

B0124-SCH-01

B0124-BOM-01

B0124-DNF-01

B0106-GUD-01

B0106-SCH-01

5120RD2 Reference Design Users Guide

5120RD2 Reference Design Schematics

5120RD2 Reference Design Bill of Materials

5120RD2 Reference Design Layout Files

5115EV2 Board User Guide

5115EV2 Schematics

Firmware / tools documents

B0092-SWT-01

B0092-SUG-01

B0092-PRN-01

C5115-SUG-01

C5115-PRN-01

S0006-GUD-01

S0014-GUD-01

gm5115 Product Family Firmware Theory of Operation for Full Custom Configuration

gm5115 Product Family Firmware User Guide for Full-Custom

gm5115 Product Family Firmware Release Notes for Full-Custom

gm5115 Product Family Firmware User Guide for Standalone

gm5115 Product Family Firmware Release Notes for Standalone

G-Probe Debug Software User Guide

G-Wizard Software User Guide

v

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Table Of Contents

1. Overview ............................................................................................................................................ 1

1.1 gm5115/25 System Design Example ........................................................................................... 1

1.2 gm5115/25 Features..................................................................................................................... 2

2. gm5115/25 Pinout .............................................................................................................................. 3

3. gm5115/25 Pin List ............................................................................................................................ 4

4. Functional Description ..................................................................................................................... 10

4.1 Clock Generation ....................................................................................................................... 10

4.1.1 Using the Internal Oscillator with External Crystal............................................................ 11

4.1.2 Using an External Clock Oscillator .................................................................................... 13

4.1.3 Clock Synthesis................................................................................................................... 14

4.2 Hardware Reset.......................................................................................................................... 16

4.3 Analog to Digital Converter (ADC)........................................................................................... 16

4.3.1 ADC Pin Connection .......................................................................................................... 17

4.3.2 ADC Characteristics ........................................................................................................... 17

4.3.3 Clock Recovery Circuit ...................................................................................................... 18

4.3.4 Sampling Phase Adjustment ............................................................................................... 19

4.3.5 ADC Capture Window........................................................................................................ 19

4.4 Ultra-Reliable Digital Visual Receiver (DVI Rx)...................................................................... 20

4.4.1 DVI Receiver Characteristics ............................................................................................. 20

4.4.2 DVI Capture Window......................................................................................................... 21

4.4.3 High-Bandwidth Digital Content Protection (HDCP) ........................................................ 21

4.5 Test Pattern Generator (TPG) .................................................................................................... 21

4.6 Input Format Measurement (IFM) ............................................................................................. 22

4.6.1 HSYNC / VSYNC Delay.................................................................................................... 22

4.6.2 Horizontal and Vertical Measurement................................................................................ 23

4.6.3 Format Change Detection ................................................................................................... 23

4.6.4 Watchdog............................................................................................................................ 24

4.6.5 Internal Odd/Even Field Detection ..................................................................................... 24

4.6.6 Input Pixel Measurement.................................................................................................... 24

4.6.7 Image Phase Measurement ................................................................................................. 24

4.6.8 Image Boundary Detection ................................................................................................. 25

4.6.9 Image Auto Balance............................................................................................................ 25

4.7 RealColor^TMDigital Color Controls .......................................................................................... 25

4.7.1 RealColor™ Flesh tone Adjustment................................................................................... 25

4.7.2 Color Standardization and sRGB Support.......................................................................... 26

4.8 High-Quality Scaling ................................................................................................................. 26

4.8.1 Variable Zoom Scaling ....................................................................................................... 26

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June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

4.8.2 Horizontal and Vertical Shrink........................................................................................... 26

4.8.3 Moiré Cancellation ............................................................................................................. 26

4.9 Bypass Options .......................................................................................................................... 27

4.10 Gamma Look-Up-Table (LUT) ............................................................................................... 27

4.11 Display Output Interface.......................................................................................................... 27

4.11.1 Display Synchronization................................................................................................... 27

4.11.2 Programming the Display Timing .................................................................................... 27

4.11.3 Panel Power Sequencing (PPWR, PBIAS)....................................................................... 29

4.11.4 Output Dithering............................................................................................................... 30

4.12 Energy Spectrum Management (ESM).................................................................................... 30

4.13 Timing Controller (TCON)...................................................................................................... 31

4.13.1 Programmable Column Driver Interface .......................................................................... 31

4.13.2 Programmable Row Driver Interface................................................................................ 33

4.14 OSD.......................................................................................................................................... 35

4.14.1 On-Chip OSD SRAM ....................................................................................................... 35

4.14.2 Color Look-up Table (LUT)............................................................................................. 36

4.15 On-Chip Microcontroller (OCM)............................................................................................. 37

4.15.1 Standalone Configuration ................................................................................................. 37

4.15.2 Full-Custom Configuration............................................................................................... 38

4.15.3 In-System-Programming (ISP) of FLASH ROM Devices ............................................... 39

4.15.4 UART Interface ................................................................................................................ 39

4.15.5 DDC2Bi Interface............................................................................................................. 40

4.15.6 General Purpose Inputs and Outputs (GPIO).................................................................... 40

4.16 Bootstrap Configuration Pins................................................................................................... 41

4.17 Host Interface........................................................................................................................... 42

4.17.1 Host Interface Command Format...................................................................................... 42

4.17.2 2-wire Serial Protocol ....................................................................................................... 42

4.18 Miscellaneous Functions.......................................................................................................... 44

4.18.1 Power Down Operation .................................................................................................... 44

4.18.2 Pulse Width Modulation (PWM) Back Light Control...................................................... 44

5. Electrical Specifications................................................................................................................... 45

5.1 Preliminary DC Characteristics ................................................................................................. 45

5.2 Preliminary AC Characteristics ................................................................................................. 47

6. Ordering Information ....................................................................................................................... 48

7. Mechanical Specifications................................................................................................................ 49

vii

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

List Of Tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Analog Input Port........................................................................................................4

DVI Input Port ............................................................................................................5

RCLK PLL Pins..........................................................................................................5

System Interface and GPIO Signals............................................................................6

Display Output Port ....................................................................................................7

Parallel ROM Interface Port .......................................................................................8

TCON Output Port......................................................................................................8

Reserved Pins..............................................................................................................8

Power Pins for ADC Sampling Clock DDS................................................................9

Table 10. Power Pins for Display Clock DDS............................................................................9

Table 11. I/O Power and Ground Pins ........................................................................................9

Table 12. Core Power and Ground Pins......................................................................................9

Table 13. TCLK Specification..................................................................................................14

Table 14. Pin Connection for RGB Input with HSYNC/VSYNC ............................................17

Table 15. ADC Characteristics .................................................................................................18

Table 16. DVI Receiver Characteristics....................................................................................20

Table 17. gm5115/25 GPIOs and Alternate Functions.............................................................41

Table 18. Bootstrap Signals ......................................................................................................41

Table 19. Instruction Byte Map ................................................................................................42

Table 20. Absolute Maximum Ratings .....................................................................................45

Table 21. DC Characteristics ....................................................................................................46

Table 22. Maximum Speed of Operation..................................................................................47

Table 23. Display Timing and DCLK Adjustments .................................................................47

Table 24. 2-Wire Host Interface Port Timing...........................................................................47

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June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

List Of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

gm5115/25 System Design Example..........................................................................1

gm5115/25 Pin Out Diagram......................................................................................3

gm5115/25 Functional Block Diagram.....................................................................10

Using the Internal Oscillator with External Crystal..................................................11

Internal Oscillator Output .........................................................................................12

Sources of Parasitic Capacitance ..............................................................................13

Using an External Single-ended Clock Oscillator ....................................................14

Internally Synthesized Clocks...................................................................................15

On-chip Clock Domains ...........................................................................................16

Figure 10. Example ADC Signal Terminations .........................................................................17

Figure 11. gm5115/25 Clock Recovery .....................................................................................18

Figure 12. ADC Capture Window..............................................................................................19

Figure 13. Some of gm5115/25 built-in test patterns.................................................................21

Figure 14. Factory Calibration and Test Environment...............................................................22

Figure 15. HSYNC Delay ..........................................................................................................23

Figure 16. Active Data Crosses HSYNC Boundary...................................................................23

Figure 17. ODD/EVEN Field Detection ....................................................................................24

Figure 18. RealColor^TMDigital Color Controls .........................................................................25

Figure 19. Display Windows and Timing ..................................................................................28

Figure 20. Single Pixel Width Display Data ..............................................................................29

Figure 21. Double Pixel Wide Display Data..............................................................................29

Figure 22. Panel Power Sequencing...........................................................................................30

Figure 23. Column Driver Interface Timing ..............................................................................32

Figure 24. Row Driver Interface Timing....................................................................................34

Figure 25. OSD Cell Map...........................................................................................................36

Figure 26. OCM Full-Custom and Standalone Configurations..................................................37

Figure 27. Programming OCM in Standalone Configuration ....................................................38

Figure 28. Programming the OCM in Full-Custom Configuration............................................39

Figure 29. 2-Wire Protocol Data Transfer..................................................................................43

Figure 30. 2-Wire Write Operations (0x1x & 0x2x)..................................................................43

Figure 31. 2-Wire Read Operation (0xAx).................................................................................44

Figure 32. gm5115/25 208-pin PQFP Mechanical Drawing.....................................................49

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June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

1. OVERVIEW

The gm5115/25 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at

XGA/SXGA resolution. It provides all key IC functions required for image capture, processing

and timing control for direct interface to the row and column drivers of the LCD panel. On-chip

TM

functions include a high-speed triple-ADC and PLL, Ultra-Reliable DVI

receiver, a high

quality zoom and shrink scaling engine, an on-screen display (OSD) controller, an on-chip

microcontroller (OCM), and a programmable panel timing controller (TCON). With all these

functions integrated onto a single device, the gm5115/25 eliminates the need for a printed circuit

board (PCB) from the system along with the associated connectors and cables. Therefore, the

gm5115/25 simplifies the design and reduces the cost of LCD monitors while maintaining a high-

degree of flexibility and quality.

1.1 gm5115/25 System Design Example

Figure 1 below shows a typical dual interface LCD monitor system based on the gm5115/25.

Designs based on the gm5115/25 have reduced system cost, simplified hardware and firmware

design and increased reliability because only a minimal number of components are required in

the system.

Column

Driver

ICs

Analog

RGB

LCD

gm5115/25

Panel

Row

Driver

ICs

DVI

Back-light

ROM

(optional)

NVRAM

Figure 1.

gm5115/25 System Design Example

1

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

1.2 gm5115/25 Features

•

On-chip OSD Controller

•

On-chip RAM for downloadable menus

FEATURES

1, 2 and 4-bit per pixel character cells

Horizontal and vertical stretch of OSD menus

Blinking, transparency and blending

•

Zoom (from VGA) and shrink (from UXGA) scaling

Integrated 8-bit triple-channel ADC / PLL

Integrated Ultra-Reliable DVI 1.0-compliant receiver

High-Bandwidth Digital Content Protection (HDCP)

On-chip programmable OnPanel timing controller

Embedded microcontroller with parallel ROM interface

On-chip versatile OSD engine

All system clocks synthesized from a single external crystal

Programmable gamma correction (CLUT)

RealColor controls provide sRGB compliance

PWM back light intensity control

•

On-chip Microcontroller

•

Requires no external micro-controller

External parallel ROM interface allows firmware customization

with little additional cost

•

23 general-purpose inputs/outputs (GPIOs) available for

managing system devices (keypad, back-light, NVRAM, etc)

Industry-standard firmware embedded on-chip, requires no

external ROM (configuration settings stored in NVRAM)

•

Built-in OnPanel Timing Controller

5 Volt tolerant inputs

Low EMI and power saving features

•

Eliminates the need for an external panel timing controller

(TCON) device, thereby reducing system cost

•

High-Quality Advanced Scaling

Direct connect to commercial row/column driver ICs (supports

dual-bus / dual-port and dual-bus / single-port)

Low EMI and power saving features include frame, line and in-line

inversion, blanking, data staggering and slew rate control.

•

Fully programmable zoom ratios

High-quality shrink capability from UXGA resolution

Real Recovery function provides full color recovery

image for refresh rates higher than those supported by

the LCD panel

Programmable Output Format

•

Single / double wide up to XGA/SXGA 75Hz output

•

Moire cancellation

Pin swap, odd / even swap and red / blue group swap of

RGB outputs for flexibility in board layout

Support for 8 or 6-bit panels (with high-quality dithering)

•

Analog RGB Input Port

•

Supports up to 162.5MHz (SXGA 75Hz / UXGA 60Hz)

On-chip high-performance PLLs

(only a single reference crystal required)

•

Highly Integrated System-on-a-Chip

Reduces Component Count for Highly Cost

Effective Solution

•

Auto-Configuration / Auto-Detection

•

Input format detection

Phase and image positioning

Standalone operation requires no external

ROM and no firmware development for Fast

Time to Market

Ultra-Reliable DVI Compliant Input Port

•

Operating up to 165 MHz (up to UXGA 60Hz)

Direct connect to all DVI compliant digital transmitters

High-bandwidth Digital Content Protection (HDCP)

•

RealColor Technology

• Pin and register compatible OnPanel Family:

- gm5115/gm5125 Dual-Interface XGA/SXGA

•

Digital brightness and contrast controls

TV color controls including hue and saturation controls

Flesh-tone adjustment

- gm3115/gm3125 Digital-Interface XGA/SXGA

- gm2115/gm2125 Analog-Interface XGA/SXGA

Full color matrix allows end-users to experience the

same colors as viewed on CRTs and other displays

(e.g. sRGB compliance)

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June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

2. GM5115/25 PINOUT

The gm5115/25 is available in a 208-pin Plastic Quad Flat Pack (PQFP) package. Figure 2

provides the pin locations for all signals.

GND1_ADC

VDD1_ADC_2.5

GND2_ADC

VDD2_ADC_2.5

TCLK

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

1

GPIO17

RVDD

2

3

RVSS

4

GPIO21/IRQn

RESETn

5

XTAL

6

GPIO14/DDC_SCL

GPIO15/DDC_SDA

ROM_ADDR15

ROM_ADDR14

ROM_ADDR13

ROM_ADDR12

ROM_ADDR11

ROM_ADDR10

ROM_ADDR9

ROM_ADDR8

ROM_ADDR7

ROM_ADDR6

ROM_ADDR5

ROM_ADDR4

RVDD

AVDD_RPLL

AVSS_RPLL

VDD_RPLL

VSS_RPLL

AVDD_DDDS

AVSS_DDDS

VDD_DDDS

VSS_DDDS

N/C

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

AVDD_SDDS

AVSS_SDDS

VDD_SDDS

VSS_SDDS

HSYNC

VSYNC

RVSS

CVSS

ROM_ADDR3

ROM_ADDR2

ROM_ADDR1

ROM_ADDR0

CVDD_2.5

CVSS

Reserved

RVSS

CVSS

RVDD

ROM_DATA7

ROM_DATA6

ROM_DATA5

ROM_DATA4

ROM_DATA3

ROM_DATA2

ROM_DATA1

ROM_DATA0

ROM_Oen

TCON_ROE

TCON_ROWCLK

TCON_RSP3

TCON_RSP2

TCON_EINV

TCON_EPOL

TCON_ESP

TCON_OINV

TCON_OPOL

TCON_OSP

DCLK/TCON_OCLK

DVS/TCON_FSYNC

DHS/TCON_LP

DEN/TCON_ECLK

PBIAS

RVDD

RVSS

GPIO8/IRQINn

GPIO0/PWM0

GPIO1/PWM1

GPIO2/PWM2

GPIO3/TIMER1

GPIO4/UART_D1

GPIO5/UART_D0

GPIO6/TCON_SHC

GPIO7/TCON_TDIV

GPIO9/TCON_ROE2

GPIO10/TCON_ROE3

GPIO11/ROM_WEn

GPIO12/NVRAM_SDA

GPIO13/NVRAM_SCL

PPWR

RVSS

RVDD

PD47/OB7

PD46/OB6

PD45/OB5

PD44/OB4

PD43/OB3

PD42/OB2

Figure 2.

gm5115/25 Pin Out Diagram

3

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

3. GM5115/25 PIN LIST

I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground

Table 1. Analog Input Port

Pin Name

No. I/O Description

AVDD_RED

172

AP

Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to

AGND_RED pin on system board (as close as possible to the pin).

RED+

RED-

AGND_RED

171

170

169

AI

Positive analog input for Red channel.

AI

Negative analog input for Red channel.

AG

Analog ground for the red channel.

Must be directly connected to the analog system ground plane.

AVDD_GREEN

168

AP

Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to

AGND_GREEN pin on system board (as close as possible to the pin).

GREEN+

GREEN-

AGND_GREEN

167

166

165

AI

Positive analog input for Green channel.

AI

Negative analog input for Green channel.

AG

Analog ground for the green channel.

Must be directly connected to the analog system ground plane.

AVDD_BLUE

164

AP

Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to

AGND_BLUE pin on system board (as close as possible to the pin).

BLUE+

BLUE-

AGND_BLUE

163

162

161

AI

Positive analog input for Blue channel.

AI

Negative analog input for Blue channel.

AG

Analog ground for the blue channel.

Must be directly connected to the analog system ground plane.

AVDD_ADC

160

AP

Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes

band gap reference, master biasing and full-scale adjust. Must be bypassed with

decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).

ADC_TEST

AGND_ADC

159

158

AO

AG

Analog test output for ADC Do not connect.

Analog ground for ADC analog blocks that are shared by all three channels. Includes band

gap reference, master biasing and full-scale adjust.

Must be directly connected to analog system ground plane.

SGND_ADC

GND1_ADC

VDD1_ADC_2.5

GND2_ADC

VDD2_ADC_2.5

HSYNC

157

156

155

154

153

137

136

AG

G

P

G

P

I

Dedicated pad for substrate guard ring that protects the ADC reference system.

Must be directly connected to the analog system ground plane.

Digital GND for ADC clocking circuit.

Must be directly connected to the digital system ground plane

Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

GND1_ADC pin on system board (as close as possible to the pin).

Digital GND for ADC clocking circuit.

Must be directly connected to the digital system ground plane.

Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

GND2_ADC pin on system board (as close as possible to the pin).

ADC input horizontal sync input.

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

ADC input vertical sync input.

VSYNC

I

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

4

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Table 2. DVI Input Port

No I/O Description

Pin Name

AVDD_IMB

173

174

175

176

177

178

AP

Analog VDD (3.3V) for internal biasing circuits.

Must be bypassed with decoupling capacitors (as close as possible to the pin).

REXT

AI

External reference resistor.

An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin.

AGND_IMB

VDD_RX2_2.5

GND_RX2

AGND_RX2

AG

P

Analog GND for internal biasing circuits.

Must be connected directly to the ground plane.

VDD (2.5V) for DVI input pair 2 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX2 pin (as close as possible to the pin).

G

GND for DVI input pair 2 logic circuits.

Must be connected directly to the ground plane.

AG

Analog GND for DVI input pair 2 input buffer.

Must be connected directly to the analog ground plane.

RX2+

RX2-

AVDD_RX2

179

180

181

AI

AP

DVI input pair 2

Analog VDD (3.3V) for DVI input pair 2 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX2 pin (as close as possible to the pin).

VDD_RX1_2.5

GND_RX1

182

183

184

P

VDD (2.5V) for DVI input pair 1 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX1 pin (as close as possible to the pin).

G

GND for DVI input pair 1 input buffer.

Must be connected directly to the analog ground plane.

AGND_RX1

AG

Analog GND for DVI input pair 1 input buffer.

Must be connected directly to the analog ground plane.

RX1+

RX1-

AVDD_RX1

185

186

187

AI

AP

DVI input pair 1

Analog VDD (3.3V) for DVI input pair 1 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX1 pin (as close as possible to the pin).

VDD_RX0_2.5

GND_RX0

188

189

190

P

VDD (2.5V) for DVI input pair 0 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX0 pin (as close as possible to the pin).

G

GND for DVI input pair 0 logic circuits.

Must be connected directly to the ground plane.

AGND_RX0

AG

Analog GND for DVI input pair 0 input buffer.

Must be connected directly to the analog ground plane.

RX0+

RX0-

AVDD_RX0

191

192

193

AI

AP

DVI input pair 0

Analog VDD (3.3V) for DVI input pair 0 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX0 pin (as close as possible to the pin).

RXC+

RXC-

AVDD_RXC

194

195

196

AI

AP

DVI input clock pair

Analog VDD (3.3V) for DVI input clock pair input buffer. Must be bypassed with 100pF

capacitor to AGND_RXC pin (as close as possible to the pin).

AGND_RXC

GND_RXPLL

VDD_RXPLL_2.5

CLKOUT

197

198

199

201

AG

G

Analog GND for DVI input clock pair input buffer.

Must be connected directly to the analog ground plane.

Digital GND for the DVI receiver internal PLL.

Must be connected directly to the system ground plane.

AP

AO

Analog VDD (2.5V) for the DVI receiver internal PLL. Must be bypassed with a decoupling

capacitor to AGND_RXPLL pin (as close as possible to the pin).

For test purposes only. Do not connect.

Table 3. RCLK PLL Pins

Pin Name

AVDD_RPLL

AVSS_RPLL

TCLK

No I/O Description

150

149

152

AP

AG

AI

Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a

0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).

Analog ground for the Reference DDS PLL.

Must be directly connected to the analog system ground plane.

Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-

ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 14.

XTAL

VDD_RPLL

VSS_RPLL

151

148

147

AO

P

G

Crystal oscillator output.

Digital power for RCLK PLL. Connect to 3.3V supply.

Digital ground for RCLK PLL.

5

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Table 4. System Interface and GPIO Signals

Pin Name

RESETn

No I/O Description

5

I

Active-low hardware reset signal. The reset signal must be held low for at least 1µS.

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO0/PWM0

GPIO1/PWM1

GPIO2/PWM2

GPIO3/TIMER1

40

41

42

43

IO

General-purpose input/output signal or PWM0. Open drain option via register setting.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal or PWM1. Open drain option via register setting.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal or PWM2. Open drain option via register setting.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal. Open drain option via register setting. This pin is also

connected to Timer 1 clock input of the OCM.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO4/UART_DI

GPIO5/UART_DO

44

45

IO

General-purpose input/output signal. Open drain option via register setting. This pin is also

connected to the OCM UART data input signal by programming an OCM register.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal. Open drain option via register setting. This pin is also

connected to the OCM UART data output signal by programming an OCM register.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO6/TCON_SHC

GPIO7/TCON_TDIV

GPIO8/IRQINn

46

47

39

IO

General-purpose input/output signal.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal. This is also active-low interrupt input to OCM and is

directly wired to OCM int_0n.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO9/TCON_ROE2

GPIO10/TCON_ROE3

GPIO11/ROM_WEn

48

49

50

IO

General-purpose input/output signal. Open drain option via register setting. This pin can

also function as TCON signal ROE2.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal. Open drain option via register setting. This pin can

also function as TCON signal ROE3.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

General-purpose input/output signal, or ROM write enable if a programmable FLASH

device is used. Open drain option via register setting.

[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO12/NVRAM_SDA

GPIO13/NVRAM_SCL

51

52

IO

General-purpose input/output signals, or 2-wire master serial interface to NVRAM in

standalone mode. Open drain option via register setting.

[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO14/DDC_SCL

GPIO15/DDC_SDA

GPIO16/HFSn

6

7

205

IO

DDC Interface for DVI-HDCP communication. This is 5V-tolerant SCL pin.

General-purpose input/output signal when host port is disabled, or data signal for 2-wire

serial host interface.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V tolerant]

GPIO17

1

IO

General-purpose input/output signals.

GPIO18

208

207

206

4

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

GPIO19

GPIO20

GPIO21/IRQn

General-purpose input/output signal when host port is disabled, or active-low and open-

drain interrupt output pin.

[Bi-directional, 5V-tolerant]

GPIO22/HCLK

204

IO

General-purpose input/output signal when host port is disabled, or clock for 2-wire serial

host interface.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

6

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Table 5. Display Output Port

No I/O Description

Pin Name

DCLK/TCON_OCLK

118

117

116

115

O

Panel output clock or TCON Odd Column Driver Bus Clock.

[Tri-state output, Programmable Drive]

DVS/TCON_FSYNC

DHS/TCON_LP

Panel Vertical Sync or TCON Frame Synchronization.

[Tri-state output, Programmable Drive]

Panel Horizontal Sync or TCON Load Pulse.

[Tri-state output, Programmable Drive]

DEN/TCON_ECLK

Panel Display Enable, which frames the output background window, or TCON Even Column

Driver Bus Clock.

[Tri-state output, Programmable Drive]

PBIAS

PPWR

114

113

O

Panel Bias Control (back light enable)

[Tri-state output, Programmable Drive]

Panel Power Control

[Tri-state output, Programmable Drive]

Panel or TCON output data.

PD47

PD46

PD45

PD44

PD43

PD42

PD41

PD40

PD39

PD38

PD37

PD36

PD35

PD34

PD33

PD32

PD31

PD30

PD29

PD28

PD27

PD26

PD25

PD24

PD23

PD22

PD21

PD20

PD19

PD18

PD17

PD16

PD15

PD14

PD13

PD12

PD11

PD10

PD9

110

109

108

107

106

105

104

103

102

101

100

99

O

[Tri-state output, Programmable Drive]

96

95

94

93

92

91

90

87

86

85

84

83

80

79

78

77

76

75

74

73

72

71

70

69

66

65

64

PD8

63

PD7

62

PD6

61

PD5

60

PD4

59

PD3

58

PD2

57

PD1

56

PD0

55

7

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Table 6. Parallel ROM Interface Port

Pin Name

No I/O Description

ROM_ADDR15

ROM_ADDR14

ROM_ADDR13

ROM_ADDR12

ROM_ADDR11

ROM_ADDR10

ROM_ADDR9

ROM_ADDR8

ROM_ADDR7

ROM_ADDR6

ROM_ADDR5

ROM_ADDR4

ROM_ADDR3

ROM_ADDR2

ROM_ADDR1

ROM_ADDR0

ROM_DATA7

ROM_DATA6

ROM_DATA5

ROM_DATA4

ROM_DATA3

ROM_DATA2

ROM_DATA1

ROM_DATA0

ROM_Oen

8

IO

I

ROM address output. These pins also serve as 5V-tolerant bootstrap inputs on power up.

9

10

11

12

13

14

15

16

17

18

19

22

23

24

25

28

29

30

31

32

33

34

35

36

5V-tolerant external PROM data input

I

O

External PROM data Output Enable

Table 7. TCON Output Port

Pin Name

TCON_OSP

TCON_OPOL

TCON_OINV

TCON_ESP

TCON_EPOL

TCON_EINV

TCON_RSP2

TCON_RSP3

TCON_ROWCLK

TCON_ROE

No I/O Description

119

120

121

122

123

124

125

126

127

128

O

Odd Starting Pulse

Odd Polarity

Odd Data Transmission Inversion

Even Starting Pulse

Even Polarity

Even Data Transmission Inversion

Row Starting Pulse for 2-Voltage Row Driver

Row Starting Pulse for 3-Voltage Row Driver

Row Shift Clock

Row Output Enable

Table 8. Reserved Pins

Pin Name

No I/O Description

Reserved

N/C

131

132

142

200

I

Tie to GND.

No connect.

I

O

N/C

8

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Note that VDD pins having "_2.5" in their names should be connected to 2.5V power supplies. All

other VDD pins should be connected to 3.3V power supplies.

Table 9. Power Pins for ADC Sampling Clock DDS

Pin Name

No I/O Description

AVDD_DDDS

146

AP

Analog power for the Destination DDS. Connect to 3.3V supply.

Must be bypassed with a 0.1uF capacitor to AVSS_DDDS pin

(as close to the pin as possible).

AVSS_DDDS

145

AG

Analog ground for the Destination DDS.

Must be directly connected to the analog system ground.

Digital power for the Destination DDS. Connect to 3.3V supply.

Digital ground for the Destination DDS.

VDD_DDDS

VSS_DDDS

144

143

P

G

Table 10. Power Pins for Display Clock DDS

No I/O Description

Pin Name

AVDD_SDDS

141

AP

Analog power for Source DDS. Connect to 3.3V supply.

Must be bypassed with a 0.1uF capacitor to AVSS_SDDS pin

(as close to the pin as possible).

AVSS_SDDS

140

AG

Analog ground for Source DDS.

Must be directly connected to the analog system ground plane.

Digital power for the Source DDS. Connect to 3.3V supply.

Digital ground for the Source DDS.

VDD_SDDS

VSS_SDDS

139

138

P

G

Table 11. I/O Power and Ground Pins

Pin Name

No I/O Description

RVDD

2

20

37

53

67

81

97

111

129

3

P

G

Connect to 3.3V supply.

Must be bypassed with a 0.1uF capacitor to RVSS (as close to the pin as possible).

RVSS

Connect to digital ground.

21

38

54

68

82

98

112

130

Table 12. Core Power and Ground Pins

Pin Name

No I/O Description

CVDD_2.5

26

88

P

Connect to 2.5V supply.

Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible).

134

203

27

89

133

135

P

CVSS

G

Connect to digital ground.

Note: “AP” indicates²⁰a²power supply that is analog in nature and does not have large switching

currents. These should be isolated from other digital supplies that do have large switching currents.

9

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

4. FUNCTIONAL DESCRIPTION

A functional block diagram is illustrated below. Each of the functional units shown is described

in the following sections.

NVRAM

Serial I/F

Serial Host I/F

GPIO

Crystal

Parallel

ROM IF

Reference

Host

8051-style

Micro-

External

ROM I/F

OSD

Clock

Interface

Controller

Generation

controller

OSD

RAMs

Internal

ROM

MCU

RAM

Panel

Timing

Control

Signals

Controller

Ultra-Reliable

DVI Rx

DVI-Compliant

Input

HDCP

Panel Data

Output

Data

Brightness /

Contrast /

Hue / Sat /

RealColor /

Moire

Image

Capture /

Measure-

ment

Zoom /

Shrink /

Filter

Path

Gamma

Control

Triple ADC

and PLL

Analog RGB

Input

Test Pattern

Generator

Figure 3.

gm5115/25 Functional Block Diagram

4.1 Clock Generation

The gm5115/25 features three clock inputs. All additional clocks are internal clocks derived from

one or more of these:

1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator

and corresponding logic. A 14.3 MHz TV crystal is recommended. Other crystal frequencies

may be used, but require custom programming. This is illustrated in Figure 4 below.

Alternatively, a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin

(leave XTAL as N/C in this case). This is illustrated in Figure 7 below. This option is

selected by connecting a 10KΩ pull-up to ROM_ADDR13 (refer to Table 18). See also Table

14.

2. DVI Differential Input Clock (RC+ and RC-)

3. Host Interface Transfer Clock (HCLK)

10

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

The gm5115 TCLK oscillator circuitry is a custom designed circuit to support the use of an

external oscillator or a crystal resonator to generate a reference frequency source for the gm5115

device.

4.1.1 Using the Internal Oscillator with External Crystal

The first option for providing a clock reference is to use the internal oscillator with an external

crystal. The oscillator circuit is designed to provide a very low jitter and very low harmonic clock

to the internal circuitry of the gm5115. An Automatic Gain Control (AGC) is used to insure

startup and operation over a wide range of conditions. The oscillator circuit also minimizes the

overdrive of the crystal, which reduces the aging of the crystal.

When the gm5115/25 is in reset, the state of the ROM_ADDR13 pin (pin number 10) is sampled.

If the pin is left unconnected (internal pull-down) then internal oscillator is enabled. In this mode

a crystal resonator is connected between TCLK (pin 152) and the XTAL (pin 151) with the

appropriately sized loading capacitors C_L1and C_L2. The size of C_L1and C_L2are determined from

the crystal manufacturer’s specification and by compensating for the parasitic capacitance of the

gm5115/25 device and the printed circuit board traces. The loading capacitors are terminated to

the analog VDD power supply. This connection increases the power supply rejection ratio when

compared to terminating the loading capacitors to ground.

gm5115/25

Vdda

CL1

152

Vdd

TCLK

151

Vdda

OSC_OUT

XTAL

100 K

TCLK Distribution

CL2

180 uA

10

N/C

Reset State Logic

ROM_ADDR13

Internal Oscillator Enable

Internal Pull Down

Resistor

~ 60K

Figure 4.

Using the Internal Oscillator with External Crystal

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gm5115/25 Preliminary Data Sheet

The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit,

measured at the TCLK pin, is an approximate sine wave with a bias of about 2 volts above

ground (see Figure 5). The peak-to-peak voltage of the output can range from 250 mV to 1000

mV depending on the specific characteristics of the crystal and variation in the oscillator

characteristics. The output of the oscillator is connected to a comparator that converts the sine

wave to a square wave. The comparator requires a minimum signal level of about 50-mV peak to

peak to function correctly. The output of the comparator is buffered and then distributed to the

gm5115/25 circuits.

3.3 Volts

250 mV peak to peak

to

~ 2 Volts

1000 mV peak to peak

time

Figure 5.

Internal Oscillator Output

One of the design parameters that must be given some consideration is the value of the loading

capacitors used with the crystal as shown in Figure 6. The loading capacitance (C_load) on the

crystal is the combination of C_L1and C_L2and is calculated by C_load= ((C_L1* C_L2) / (C_L1+ C_L2)) +

C_shunt. The shunt capacitance C_shuntis the effective capacitance between the XTAL and TCLK

pins. For the gm5115/25 this is approximately 9 pF. C_L1and C_L2are a parallel combination of the

external loading capacitors (C_ex), the PCB board capacitance (C_pcb), the pin capacitance (C_pin), the

pad capacitance (C_pad), and the ESD protection capacitance (C_esd). The capacitances are

symmetrical so that C_L1= C_L2= C_ex+ C_PCB+ C_pin+ C_pad+ C_ESD. The correct value of C_exmust be

calculated based on the values of the load capacitances. Approximate values are provided in

Figure 6.

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd

Vdda

Cex1

Cpcb

Cpin

Cpad

Cesd

141

Internal Oscillator

TCLK

gm5115/25

Cshunt

Cpcb

142

Vdda

XTAL

Cex2

Cpin

Cpad

Cesd

Approximate values:

C

_PCB~ 2 pF to 10 pF (layout dependent)

_pin~ 1.1 pF

_pad~ 1 pF

_esd~ 5.3 pF

_shunt~ 9 pF

CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd

Figure 6.

Sources of Parasitic Capacitance

Some attention must be given to the details of the oscillator circuit when used with a crystal

resonator. The PCB traces should be as short as possible. The value of C_loadthat is specified by

the manufacturer should not be exceeded because of potential start up problems with the

oscillator. Additionally, the crystal should be a parallel resonate-cut and the value of the

equivalent series resistance must be less then 90 Ohms.

4.1.2 Using an External Clock Oscillator

Another option for providing the reference clock is to use a single-ended external clock

oscillator. When the gm5115/25 is in reset, the state of the ROM_ADDR13 (pin 10) is sampled.

If ROM_ADDR13 is pulled high by connecting to VDD through a pull-up resistor (15KΩ

recommended, 15KΩ maximum) then external oscillator mode is enabled. In this mode the

internal oscillator circuit is disabled and the external oscillator signal that is connected to the

TCLK pin (pin number 152) is routed to an internal clock buffer. This is illustrated in Figure 7.

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Vdd

14 to 24 MHz

gm5115/25

152

Vdd

Oscillator

GND

TCLK

OSC_OUT

TCLK Distribution

151

Internal

Disable

Vdd

Oscillator

XTAL

10 K

10

ROM_ADDR13

Reset State Logic

External Oscillator Enable

Internal Pull Down

Resistor

~ 60 K

Figure 7.

Using an External Single-ended Clock Oscillator

Frequency

Jitter Tolerance

Rise Time (10% to 90%)

Maximum Duty Cycle

14 to 24 MHz

250 ps

5 ns

40-60

Table 13. TCLK Specification

4.1.3 Clock Synthesis

The gm5115/25 synthesis all additional clocks internally as illustrated in Figure 8 below. The

synthesized clocks are as follows:

1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is

derived from the TCLK/XTAL pad input.

2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference.

3. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as the

reference.

4. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC

as the reference. The SDDS internal digital logic is driven by RCLK.

5. Display Clock (DCLK) synthesized by Destination DDS (DDDS) PLL using IP_CLK as the

reference. The DDDS internal digital logic is driven by RCLK.

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

6. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as

OCM_CLK domain driver.

7. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as

alternative clock (faster than TCLK) to drive IFM.

8. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK.

ACLK is derived from SCLK.

SDDS

HSYNC

SCLK

DCLK

DDDS

IP_CLK

RCLK

PLL

TCLK

/2

/4

RCLK/2

RCLK/4

RC+

RC-

DVI Rx

DVI_CLK

Figure 8.

Internally Synthesized Clocks

The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9 below.

These include:

1. Input Domain Clock (IP_CLK). Max = 165MHz

2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz

3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz

4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz

5. ADC Domain Clock (ACLK). Max = 165MHz.

The clock selection for each domain as shown in the figure below is controlled using the

CLOCK_CONFIG registers (index 0x03 and 0x04).

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*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

SCLK

DCLK

SENSE_ACLK

IP_CLK

DP_CLK

DVI_CLK

IP_CLK

RCLK/2

RCLK/4

IFM_CLK

TCLK

ACLK

OCM_CLK

SCLK

TCLK

Figure 9.

On-chip Clock Domains

4.2 Hardware Reset

Hardware Reset is performed by holding the RESETn pin low for a minimum of 1µs. A TCLK

input (see Clock Options above) must be applied during and after the reset. When the reset period

is complete and RESETn is de-asserted, the power-up sequence is as follows:

1. Reset all registers of all types to their default state (this is 00h unless otherwise specified in

the gm5115/25 Register Listing).

2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain

cycles following the de-assertion of RESETn.

3. Operate the OCM_CLK domain at the TCLK frequency.

4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal

frequency).

5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the

bootstrap selected clock.

6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 18), then the OCM becomes

active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset until

OCM_CONTROL register (0x22) bit 1 is enabled.

4.3 Analog to Digital Converter (ADC)

The gm5115/25 chip has three ADC’s (analog-to-digital converters), one for each color (red,

green, and blue).

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4.3.1 ADC Pin Connection

gm5115/25 Preliminary Data Sheet

The analog RGB signals are connected to the gm5115/25 as described below:

Table 14. Pin Connection for RGB Input with HSYNC/VSYNC

Pin Name

ADC Signal Name

Red+

Red

Red-

Terminate as illustrated in Figure 10

Green

Terminate as illustrated in Figure 10

Blue

Green+

Green-

Blue+

Blue-

HSYNC

VSYNC

Terminate as illustrated in Figure 10

Horizontal Sync (Terminate as illustrated in Figure 10)

Vertical Sync (Terminate as with HSYNC illustrated in Figure 10)

gm5115/25

100Ω

RED

GND

RED +

0.01uF

75Ω

DB15

100Ω

RED -

HSYNC

HS

Figure 10.

Example ADC Signal Terminations

Please note that it is very important to follow the recommended layout guidelines for the circuit

shown in Figure 10. These are described in "gm5115/25 Layout Guidelines" document number

C5115-SLG-01A.

4.3.2 ADC Characteristics

The table below summarizes the characteristics of the ADC:

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gm5115/25 Preliminary Data Sheet

Table 15. ADC Characteristics

MIN

TYP

290 MHz

MAX NOTE

Track & Hold Amp Bandwidth

Guaranteed by design. Note that the Track &

Hold Amp Bandwidth is programmable. 290

MHz is the maximum setting.

Full Scale Adjust Range at RGB Inputs

Full Scale Adjust Sensitivity

0.55 V

0.90 V

+/- 1 LSB

+/-0.5 LSB

Measured at ADC Output.

Independent of full-scale RGB input.

Measured at ADC Output.

Zero Scale Adjust Sensitivity

Sampling Frequency (Fs)

Differential Non-Linearity (DNL)

No Missing Codes

Integral Non-Linearity (INL)

Channel to Channel Matching

10 MHz

162.5 MHz

+/-0.9 LSB Fs = 135 MHz

Guaranteed by test.

Fs =135 MHz

+/- 1.5 LSB

+/- 0.5 LSB

Note that input formats with resolutions or refresh rates higher than that supported by the LCD

panel are supported as recovery modes only. This is called RealRecovery™. For example, it may

be necessary to shrink the image. This may introduce image artifacts. However, the image is

clear enough to allow the user to change the display properties.

The gm5115/25 ADC has a built-in clamp circuit for AC-coupled inputs. By inserting series

capacitors (about 10 nF), the DC offset of an external video source can be removed. The clamp

pulse position and width are programmable.

4.3.3 Clock Recovery Circuit

The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to

sample analog RGB data (IP_CLK or source clock). This circuit is locked to HSYNC of the

incoming video signal.

Patented digital clock synthesis technology makes the gm5115/25 clock circuits resistant to

temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery

circuit can generate any IP_CLK clock frequency within the range of 10MHz to 165MHz.

Image Phase

Measurement

R

Window

Capture

24

G

B

ADC

Phase

SDDS

HSYNC

(delayed)

HSYNC

IPCLK

Figure 11.

gm5115/25 Clock Recovery

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4.3.4 Sampling Phase Adjustment

gm5115/25 Preliminary Data Sheet

The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the SDDS.

The accuracy of the sampling phase is checked and the result read from a register. This feature

enables accurate auto-adjustment of the ADC sampling phase.

4.3.5 ADC Capture Window

Figure 12 below illustrates the capture window used for the ADC input. In the horizontal

direction the capture window is defined in IP_CLKs (equivalent to a pixel count). In the vertical

direction it is defined in lines.

All the parameters beginning with “Source” are programmed gm5115/25 registers values. Note

that the Input Vertical Total is solely determined by the input and is not a programmable

parameter.

Source Horizontal Total (pixels)

Reference

Point

Source

Hstart

Source Width

Capture Window

Figure 12.

ADC Capture Window

The Reference Point marks the leading edge of the first internal HSYNC following the leading

edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived

from external HSYNC and VSYNC inputs.

Horizontal parameters are defined in terms of single pixel increments relative to the internal

horizontal sync. Vertical parameters are defined in terms of single line increments relative to the

internal vertical sync.

For ADC interlaced inputs, the gm5115/25 may be programmed to automatically determine the

field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format

Measurement, Section 4.6.

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gm5115/25 Preliminary Data Sheet

4.4 Ultra-Reliable Digital Visual Receiver (DVI Rx)

The Ultra-Reliable DVI^TMreceiver block of the gm5115/25 is compliant with DVI1.0 single link

specifications. Digital Visual Interface (DVI) is a standard that uses Transition Minimized

Differential Signaling protocol (TMDS). This block supports an input clock frequency ranging

from 20 MHz to 165 MHz.

4.4.1 DVI Receiver Characteristics

Table 16 summarizes the characteristics of the four Receiver Pair inputs. Please note that it is

very important to follow the recommended layout guidelines for these signals. These are

described in "gm5115/25 Layout Guidelines" document number C5115-SLG-01A.

Table 16. DVI Receiver Characteristics

MIN

TYP

MAX

NOTE

DC Characteristics

Differential Input Voltage

Input Common Mode Voltage

150mV

AVDD

1200mV

AVDD

–300m V

AVDD

-10mV

-37mV

AVDD

+10mV

Behavior when Transmitter Disable

AC Characteristics

20 MHz

150mV

Input clock frequency

165 MHz

Input differential sensitivity (Peak-to-peak)

Max differential input (peak-to-peak)

Allowable Intra-Pair skew at Receiver

Allowable Inter-Pair skew at Receiver

1560 mV

250 ps

4.0 ns

Input clock = 160 MHz

Worst case differential input clock jitter

188 ps

tolerance

Note that input formats with resolutions or refresh rates higher than that supported by the LCD

panel are supported as recovery modes only. This is called RealRecovery™. For example, it may

be necessary to shrink the image. This may introduce image artifacts. However, the image is

clear enough to allow the user to change the display properties.

Through register programming, the receiver unit may be placed in one of three states:

•

Active: The receiver block is fully on and running.

Standby: Only the RC (clock) channel remains active. Data and other control signals are not

decoded.

•

Off: The receiver block is powered down.

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4.4.2 DVI Capture Window

gm5115/25 Preliminary Data Sheet

DE (Display Enable), HSYNC and VSYNC are synthesized internally by examining the active

regions of each line and compensating for possible source timing errors and/or embedded

HSYNC / VSYNC jitter.

There are two ways to define the DVI capture region:

CREF Capture - In this mode the usual active window parameters must be programmed as with

ADC inputs (see Section 4.3.5.).

DE Capture - In this mode the active window code embedded in the DVI signal defines the

active window automatically. Only the active width and active length parameters obtained by

performing Input Format Measurement (IFM) need be programmed.

4.4.3 High-Bandwidth Digital Content Protection (HDCP)

Note: This section applies to the HDCP-enabled chip versions gm5115-H and gm5125-H but not

the standard versions gm5115 and gm5125.

The HDCP system allows authentication of a video receiver by a video transmitter, decryption of

transmitter-encoded video data by the receiver, and periodic renew-ability of authentication

during transmission. The gm5115/25 implements circuitry to allow full support of the HDCP 1.0

protocol for DVI inputs.

For enhanced security, Genesis provides a means of storing and accessing the secret key given to

individual monitor units in an encrypted format.

Further details of the protocol and theory of the system can be found in the High-bandwidth

Digital Content Protection System specification (see www.digital-cp.com).

4.5 Test Pattern Generator (TPG)

The gm5115/25 contains hundreds of test patterns, some of which are shown in Figure 13. Once

programmed, the gm5115/25 test pattern generator can replace a video source (e.g. a PC) during

factory calibration and test. This simplifies the test procedure and eliminates the possibility of

image noise being injected into the system from the source. The foreground and background

colors are programmable. In addition, the gm5115/25 OSD controller can be used to produce

other patterns.

Figure 13.

Some of gm5115/25 built-in test patterns

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gm5115/25 Preliminary Data Sheet

The DDC2Bi port can be used for factory testing. This is illustrated in Figure 14. The factory test

station connects to the gm5115/25 through the Direct Data Channel (DDC) of the DSUB15 or

DVI connectors. Then, the PC can make gm5115/25 display test patterns (see section 4.5). A

camera can be used to automate the calibration of the LCD panel.

DDC

Factory Test Station

Device-Under-Test

Camera

Figure 14.

Factory Calibration and Test Environment

4.6 Input Format Measurement (IFM)

The gm5115/25 has an Input Format Measurement block (the IFM) providing the capability of

measuring the horizontal and vertical timing parameters of the input video source. This

information may be used to determine the video format and to detect a change in the input

format. It is also capable of detecting the field type of interlaced formats.

The IFM features a programmable reset, separate from the regular gm5115/25 soft reset. This

reset disables the IFM, reducing power consumption. The IFM is capable of operating while the

gm5115/25 is running in power-down mode.

Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or

RCLK/4), while vertical measurements are measured in terms of HSYNC pulses.

For an overview of the internally synthesized clocks, see section 4.1.

4.6.1 HSYNC / VSYNC Delay

The active input region captured by the gm5115/25 is specified with respect to internal HSYNC

and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC at the input

pins and thus force the captured region to be bounded by external HSYNC and VSYNC timing.

However, the gm5115/25 provides an internal HSYNC and VSYNC delay feature that removes

this limitation. This feature is available for use with both the ADC input and the DVI Rx (DE-

regeneration mode). By delaying the sync internally, the gm5115/25 can capture data that spans

across the sync pulse.

It is possible to use HSNYC and VSYNC delay for image positioning. (Alternatively,

Source_HSTART and Source_VSTART in Figure 12 are used for image positioning of analog

input.) Taken to an extreme, the intentional movement of images across apparent HSYNC and

VSYNC boundaries creates a horizontal and/or vertical wrap effect.

HSYNC is delayed by a programmed number of selected input clocks.

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gm5115/25 Preliminary Data Sheet

active

HS(system)

HS(internal)

capture

programmable

delay

input block actually

captures across HSYNC

Figure 15.

HSYNC Delay

Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with

respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but with

different paths to the gm5115/25 (HSYNC is often regenerated from a PLL). As a result,

VSYNC may be seen earlier or later. Because VSYNC is used to reset the line counter and

HSYNC is used to increment it, any difference in the relative position of HSYNC and VSYNC is

seen on-screen as vertical jitter. By delaying the HSYNC a small amount, it can be ensured that

VSYNC always resets the line counter prior to it being incremented by the “first” HSYNC.

active data crosses HS boundary

delayed HS placed safely within blanking

Data

HS (system)

Internal Delayed HS

Figure 16.

Active Data Crosses HSYNC Boundary

4.6.2 Horizontal and Vertical Measurement

The IFM is able to measure the horizontal period and active high pulse width of the HSYNC

signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal

measurements are performed on only a single line per frame (or field). The line used is

programmable. It is able to measure the vertical period and VSYNC pulse width in terms of

rising edges of HSYNC.

Once enabled, measurement begins on the rising VSYNC and is completed on the following

rising VSYNC. Measurements are made on every field / frame until disabled.

4.6.3 Format Change Detection

The IFM is able to detect changes in the input format relative to the last measurement and then

alert both the system and the on-chip microcontroller. The microcontroller sets a measurement

difference threshold separately for horizontal and vertical timing. If the current field / frame

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gm5115/25 Preliminary Data Sheet

timing is different from the previously captured measurement by an amount exceeding this

threshold, a status bit is set. An interrupt can also be programmed to occur.

4.6.4 Watchdog

The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the

programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any

VSYNC period exceeds the programmed timing threshold (in terms of HSYNC pulses), a second

register bit is set. An interrupt can also be programmed to occur.

4.6.5 Internal Odd/Even Field Detection

The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user

specifies start and end values to outline a “window” relative to HSYNC. If the VSYNC leading

edge occurs within this window, the IFM signals the start of an ODD field. If the VSYNC

leading edge occurs outside this window, an EVEN field is indicated (the interpretation of odd

and even can be reversed). The window start and end points are selected from a predefined set of

values.

HS

window

Window

Start

Window End

VS - even

VS - odd

Figure 17.

ODD/EVEN Field Detection

4.6.6 Input Pixel Measurement

The gm5115/25 provides a number of pixel measurement functions intended to assist in

configuring system parameters such as pixel clock, SDDS sample clocks per line and phase

setting, centering the image, or adjusting the contrast and brightness.

4.6.7 Image Phase Measurement

This function measures the sampling phase quality over a selected active window region. This

feature may be used when programming the source DDS to select the proper phase setting. Please

refer to the gm5115/25 Programming Guide for the optimized algorithm.

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4.6.8 Image Boundary Detection

gm5115/25 Preliminary Data Sheet

The gm5115/25 performs measurements to determine the image boundary. This information is

used when programming the Active Window and centering the image.

4.6.9 Image Auto Balance

The gm5115/25 performs measurements on the input data that are used to adjust brightness and

contrast.

4.7 RealColor^TMDigital Color Controls

The gm5115/25 provides high-quality digital color controls. These consist of a subtractive “black

level” stage, followed by a full 3x3 RGB matrix multiplication stage, followed by an signed

offset stage as shown in Figure 18.

Subtractive

Offset

3x3 Color

Additive

Offset

Conversion

(Black Level)

(Brightness)

Red In

Red Out

-

+/-

X

Green In

Blue In

Green Out

Blue Out

Figure 18.

RealColor^TMDigital Color Controls

This structure can accommodate all RGB color controls such as black-level (subtractive stage),

contrast (multiplicative stage), and brightness (signed additive offset). In addition, it supports all

YUV color controls including brightness (additive factor applied to Y), contrast (multiplicative

factor applied to Y), hue (rotation of U and V through an angle) and saturation (multiplicative

factor applied to both Y and V).

To provide the highest color purity all mathematical functions use 10 bits of accuracy. The final

result is then dithered to eight or six bits (as required by the LCD panel).

4.7.1 RealColor™ Flesh tone Adjustment

The human eye is more sensitive to variations of flesh tones than other colors; for example, the

user may not care if the color of grass is modified slightly during image capture and/or display.

However, if skin tones are modified by even a small amount, it is unacceptable. The gm5115/25

features flesh tone adjustment capabilities. This feature is not based on lookup tables, but rather a

manipulation of YUV-channel parameters. Flesh tone adjustment is available for all inputs.

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gm5115/25 Preliminary Data Sheet

4.7.2 Color Standardization and sRGB Support

Internet shoppers may be very picky about what color they experience on the display.

Gm5115/25 RealColor^TMdigital color controls can be used to make the color response of an LCD

monitor compliant with standard color definitions, such as sRGB. SRGB is a standard for color

exchange proposed by Microsoft and HP (see www.srgb.com). gm5115/25 RealColor controls

can be used to make LCD monitors sRGB compliant, even if the native response of the LCD

panel itself is not. For more information on sRGB compliance using gm5115/25 family devices

please refer to the sRGB application brief C5115-APB-02A.

4.8 High-Quality Scaling

The gm5115/25 zoom/shrink scaler uses an adaptive scaling technique proprietary to Genesis

Microchip Inc., and provides high quality scaling of real time video and graphics images. An

input field/frame is scalable in both the vertical and horizontal dimensions.

Interlaced fields may be spatially de-interlaced by vertically scaling and repositioning the input

fields to align with the output display’s pixel map.

4.8.1 Variable Zoom Scaling

The gm5115/25 scaling filter can combine its advanced scaling with a pixel-replication type

scaling function. This is useful for improving the sharpness and definition of graphics when

scaling at high zoom factors (such as VGA to XGA).

4.8.2 Horizontal and Vertical Shrink

A shrink function may be performed on the input data. This is an arbitrary horizontal active

resolution reduction to between (50% + 1 pixel) to 100% of the input. For example, this allows

SXGA 1280 pixels to be displayed as 1024 (XGA).

The gm5115/25 provides an arbitrary vertical shrink down to (50% + 1 line) of the original image

size. Together with the arbitrary horizontal shrink, this allows the gm5115/25 to capture and

display images one VESA standard format larger than the native display resolution. For

example, SXGA may be captured and displayed on an XGA panel.

4.8.3 Moiré Cancellation

The gamma curve and other non-linearities can affect the energy distribution of pixels when

scaled to different areas of the screen. This is an example of the Moiré effect. The gm5115/25 has

hardware features to negate the Moiré effect, improving the scaling quality.

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gm5115/25 Preliminary Data Sheet

4.9 Bypass Options

The gm5115/25 has the capability to completely bypass internal processing. In this case,

captured input signals and data are passed, with a small latency, straight through to the display

output. The gm5115/25 is also able to bypass the zoom filter and the gamma LUT.

4.10 Gamma Look-Up-Table (LUT)

The gm5115/25 provides an 8 to 10-bit look-up table (LUT) for each input color channel

intended for Gamma correction and to compensate for a non-linear response of the LCD panel.

A 10-bit output results in an improved color depth control. The 10-bit output is then dithered

down to 8 bits (or 6 bits) per channel at the display (see section 4.11.3 below). The LUT is user-

programmable to provide an arbitrary transfer function. Gamma correction occurs after the zoom

/ shrink scaling block. If bypassed, the LUT does not require programming.

4.11 Display Output Interface

The Display Output Port provides data and control signals that permit the gm5115/25 to connect

to a variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit

RGB pixels, either single- or double-pixel wide. All display data and timing signals are

synchronous with the DCLK output clock.

4.11.1 Display Synchronization

Refer to section 4.1 for information regarding internal clock synthesis.

The gm5115/25 supports the following display synchronization modes:

•

Frame Sync Mode: The display frame rate is synchronized to the input frame or field

rate. This mode is used for standard operation.

•

Free Run Mode: No synchronization. This mode is used when there is no valid input

timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In free-

run mode, the display timing is determined only by the values programmed into the

display window and timing registers.

4.11.2 Programming the Display Timing

Display timing signals provide timing information so the Display Port can be connected to an

external display device. Based on values programmed in registers, the Display Output Port

produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals.

The figure below provides the registers that define the output display timing.

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gm5115/25 Preliminary Data Sheet

Horizontal values are programmed in single-pixel increments relative to the leading edge of the

horizontal sync signal. Vertical values are programmed in line increments relative to the leading

edge of the vertical sync signal.

DH_BKGND_START

DH_BKGND_END

DV_VS_END

VSYNC Region

Vertical Blanking (Back Porch)

DV_BKGND_START

DV_ACTIVE_START

Display Background Window

Display Active Window

DV_ACTIVE_LENGTH

DV_BKGND_END

Vertical Blanking (Front Porch)

DH_TOTAL

DHS

DEN **

DH_HS_END

** DEN is not asserted during vertical blanking

DH_ACTIVE_WIDTH

DH_ACTIVE_START

Figure 19.

Display Windows and Timing

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gm5115/25 Preliminary Data Sheet

The double-wide output only supports an even number of horizontal pixels.

DCLK (Output)

DEN (Output)

ER/EG/EB

XXX

rgb0

rgb1

XXX

rgb2

rgb3

rgb4

(Output)

OR/OG/OB

(Output)

Figure 20.

Single Pixel Width Display Data

DCLK (Output)

DEN (Output)

ER/EG/EB

(Output)

XXX

rgb0

rgb1

rgb2

rgb3

rgb4

rgb5

rgb6

rgb7

rgb8

rgb9

OR/OG/OB

(Output)

Figure 21.

Double Pixel Wide Display Data

4.11.3 Panel Power Sequencing (PPWR, PBIAS)

The gm5115/25 has two dedicated outputs PPWR and PBIAS (pins 113 and 114) to control LCD

power sequencing once data and control signals are stable. The timing of these signals is fully

programmable.

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gm5115/25 Preliminary Data Sheet

TMG1

TMG2

TMG1

PPWR Output

Panel Data and Control Signals

PBIAS Output

POWER_SEQ_EN = 1

POWER_SEQ_EN = 0

Figure 22.

Panel Power Sequencing

4.11.4 Output Dithering

The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down to

either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels.

The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image

free of contours is perceived. Dithering works by spreading the quantization error over

neighboring pixels both spatially and temporally. Two dithering algorithms are available: random

or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel.

All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8

bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).

4.12 Energy Spectrum Management (ESM)

High spikes in the electromagnetic interference (EMI) power spectrum can cause LCD monitor

products to violate emissions standards. The gm5115/25 programmable TCON has many features

that can be used to reduce EMI. These include:

•

transition minimization,

drive strength control,

data staggering,

even/odd, red/blue, bit 0/7 swapping for reduced trace length,

slew rate control,

dual-edge clocking, and

clock spectrum modulation.

These features eliminate the costs associated with EMI-reducing components and shielding.

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gm5115/25 Preliminary Data Sheet

4.13 Timing Controller (TCON)

The gm5115/25 features an integrated timing controller (TCON) that connects directly to

commercially available row and column drivers. It supports either 18 or 24-bits per pixel in 1 or

2 pixels per clock XGA operation. Also, it supports single or dual-edge clocking modes. Frame,

Line (Row) and pixel inversion is available for better image quality. In-Line inversion reduces

power consumption and EMI radiation. Data signals have programmable drive strength.

During panel power-up the TCON control signals can be held inactive. This is to provide correct

power sequencing that does not damage the panel. The TCON control signals only become active

when the panel power sequencing is complete.

4.13.1 Programmable Column Driver Interface

The gm5115/25 column driver interface is highly programmable. gm5115 supports dual bus /

dual port, dual bus / one port (both interleave and bank) as well as single bus / single port for

XGA column drivers. gm5125 supports dual bus / dual port and dual bus / one port (both

interleave and bank) for SXGA column drivers.

The column driver interface consists of the following signals:

OCLK/ECLK – Odd/Even Column Driver bus clock. OCLK and ECLK have a programmable

phase control (0-7ns) and programmable polarities. Even output data bus (ERGB) can be skewed

½ clock (early) to reduce the number of outputs switching simultaneously.

OSP/ESP – Odd/Even Starting Pulse. OSP and ESP have programmable positioning before valid

data. They also have programmable polarities.

ORGB[24]/ERGB[24] – Odd/Even 24 bits data bus supports 24 or 18 bits per pixel in 1 or 2

pixels per clock. These signals support even/odd, red/blue and data bit swap. They also have

programmable group and inter-group delays (0-7ns).

OPOL/EPOL – Odd/Even polarity. With programmable position of OPOL/EPOL, the

OPOL/EPOL can be switched when LP is active or before or after LP.

OINV/EINV – Odd/Even data transition inversion. These signals provide data inversion

capability to reduce electromagnetic interference (EMI). One INV signal can be used (either

EINV or OINV), or both.

LP – Load/Latch pulse. The Load/Latch pulse has a programmable width and polarity.

SHC – Output circuit control. This signal has programmable timing similar to OPOL/EPOL. It is

optionally available on GPIO6.

TDIV – Horizontal timing. This signal rises with LP and has a programmable falling edge. It is

optionally available on GPIO7.

All signals OCLK, ECLK, ORGB, ERGB, OSP, ESP, OPOL, EPOL, OINV, EINV have

programmable drive strengths and can be disabled.

Clocks (OCLK/ECLK), Polarities (EPOL/OPOL) and Data (ERGB/ORGB, ESP/OSP) can be

blanked separately, during horizontal and/or vertical blanking period (programmable) to reduce

power. Clocks and Polarities are forced to zero and Data (ERGB/ORGB) is forced to either white

or black during blanking period.

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gm5115/25 Preliminary Data Sheet

Refer to Figure 23 for the column driver interface timing. See the gm5115/25 programming guide

(C5115-DSR-01) for details regarding column driver programming.

Figure 23.

Column Driver Interface Timing

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gm5115/25 Preliminary Data Sheet

4.13.2 Programmable Row Driver Interface

The gm5115/25 row driver interface supports 2 and 3 voltage row drivers.

The row driver interface consists of the following signals. The starting time and pulse-width of

each are fully programmable.

RSP2 – Row Starting Pulse for 2 voltage Row Driver

RSP3 – Row Starting Pulse for 3 voltage Row Driver

ROWCLK – Row/Vertical shift clock

ROE – Row Output Enable or Row Blank Time or Gate Driver Output Enable. This signal is

used to control RC discharge time. Note that some vendors support three ROE’s for this function

to avoid 2 lines being activated at the same time (ROE2 and ROE3 are optionally available on

pins GPIO9 and GPIO10). The polarities of ROE, ROE2 and ROE3 are programmable. These

signals can be blanked during horizontal and/or vertical blanking to reduce power. In addition,

ROE, ROE2 and ROE3 may be staggered.

ROWCLK, ROE, ROE2 and ROE3 have programmable polarities and can be blanked during

horizontal and/or vertical blanking period (programmable) to reduce power. Note that ROE2 and

ROE3 can be used to drive GV and GVOFF signals required by some row driver ICs.

See the gm5115/25 programming guide (C5115-DSR-01) for details regarding row driver

programming.

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gm5115/25 Preliminary Data Sheet

Figure 24.

Row Driver Interface Timing

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gm5115/25 Preliminary Data Sheet

4.14 OSD

The gm5115/25 has a fully programmable, high-quality OSD controller. The graphics are divided

into “cells” 12 by 18 pixels in size. The cells are stored in an on-chip static RAM (4096 words by

24 bits) and can be stored as 1-bit per pixel data, 2-bit per pixel data or 4-bit per pixel data. This

permits a good compression ratio while allowing more than 16 colors in the image.

Some general features of the gm5115/25 OSD controller include:

OSD Position – The OSD menu can be positioned anywhere on the display region. The reference

point is Horizontal and Vertical Display Background Start (DH_BKGND_START and

DV_BKGND_START in Figure 19).

OSD Stretch – The OSD image can be stretched horizontally and/or vertically by a factor of two,

three, or four. Pixel and line replication is used to stretch the image.

OSD Blending – Sixteeen levels of blending are supported for the character-mapped and

bitmapped images. One host register controls the blend levels for pixels with LUT values of 128

and greater, while another host register controls the blend levels for pixels with LUT values of

127 and lower. OSD color LUT value 0 is reserved for transparency and is unaffected by the

blend attribute.

4.14.1 On-Chip OSD SRAM

The on-chip static RAM (4096 words by 24 bits) stores the cell map and the cell definitions.

In memory, the cell map is organized as an array of words, each defining the attributes of one

visible character on the screen starting from upper left of the visible character array. These

attributes specify which character to display, whether it is stored as 1, 2 or 4 bits per pixel, the

foreground and background colors, blinking, etc.

Registers CELLMAP_XSZ and CELLMAP_YSZ are used to define the visible area of the OSD

image. For example, Figure 25 shows a cell map for which CELLMAP_XSZ =25 and

CELLMAP_YSZ =10.

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gm5115/25 Preliminary Data Sheet

Address 1:

Address 25:

Attributes for

Cell Attributes for

upper-left hand cell

upper-right hand cell

CELLMAP_XSZ

Address26:

Cell attributes for

1^stcell, 2^ndrow

Brightness

Contrast

CELLMAP_YSZ

Figure 25.

OSD Cell Map

Cell definitions are stored as bit map data. On-chip registers point to the start of 1-bit per pixel

definitions, 2-bit per pixel definitions and 4-bit per pixel definitions respectively. 1, 2 and 4-bit

per pixel cell definitions require 9, 18 and 36 words of the OSD RAM respectively.

Note that the cell map and the cell definitions share the same on-chip RAM. Thus, the size of the

cell map can be traded off against the number of different cell definitions. In particular, the size

of the OSD image and the number of cell definitions must fit in OSD SRAM. That is, the

following inequality must be satisfied. (Note, the ROUND operation rounds 3.5 to 4).

(CELLMAP_XSZ+1) * CELLMAP_YSZ +

18 * ROUND(Number of 1-bit per pixel fonts / 2) +

18 * (Number of 2-bit per pixel fonts) +

36 * (Number of 4-bit per pixel fonts)

<= 4096

For example, an OSD menu 360 pixels wide by 360 pixels high is 30 cells in width and 20 cells

in height. Many of these cells would be the same (e.g. empty). In this case, the menu could

contain more than 32 1-bit per pixel cells, 100 2-bit per pixel cells, and 16 4-bit per pixel cells.

Of course, different numbers of each type can also be used.

4.14.2 Color Look-up Table (LUT)

Each pixel of a displayed cell is resolved to an 8-bit color code. This selected color code is then

transformed to a 24-bit value using a 256 x 24-bit look up table. This LUT is stored in an on-chip

RAM that is separate from the OSD RAM. Color index value 0x00 is reserved for transparent

OSD pixels.

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gm5115/25 Preliminary Data Sheet

4.15 On-Chip Microcontroller (OCM)

The gm5115/25 on-chip microcontroller (OCM) serves as the system microcontroller. It

programs the gm5115/25 and manages other devices in the system such as the keypad, the back

light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins.

The OCM can operate in two configurations, Standalone configuration and Full-Custom

configuration, as illustrated in Figure 26.

Factory

Port

Factory

Port

Analog

RGB

Analog

RGB

gm5115/25

Input

Output to

OCM

LCD Panel

DVI

ROM

On-chip ROM:

Input

• Auto mode detection

• Auto-configuration

• Standard high-quality OSD menus

• Factory test / calibration functions

NVRAM

PROM

Configuration settings in NVRAM:

• OSD Colors, Logo and other configuration

• Panel Parameters

User settings in NVRAM:

• Brightness/contrast settings, etc • Contains firmware code and data

for all firmware functions

External ROM:

• On mode-by-mode basis

• Additional input modes

• Code patches

Figure 26.

(No external ROM)

OCM Full-Custom and Standalone Configurations

Figure 26A - Standalone Configuration

Figure 26B - Full-Custom Configuration

(Program and Data stored in external ROM)

4.15.1 Standalone Configuration

Standalone configuration offers the most simple and inexpensive system solution for generic

LCD monitors. In this configuration the OCM executes firmware stored internally in gm5115/25.

This is illustrated in Figure 26A. The on-chip firmware provides all the standard functions

required in a high-quality generic LCD monitor. This includes mode-detection, auto-

configuration and a high-quality standard OSD menu system. No external ROM is required

(which reduces BOM cost) and no firmware development effort is required (which reduces time-

to-market).

In Standalone configuration many customization parameters are stored in NVRAM. These

include the LCD panel timing parameters (including TCON programming), the color scheme and

logos used in the OSD menus, the functions provided by the OSD menus, and arbitrary firmware

modifications. These customization parameters are described in the Standalone User’s Guide

(B0108-SUG-01). Based on the customization parameters, G-Wizard (a GUI-based development

tool used to program Genesis devices) produces the hex image file for NVRAM. G-Probe is then

used to download the NVRAM image file into the NVRAM device. This is illustrated in Figure

27 below.

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gm5115/25 Preliminary Data Sheet

Specify Configurable Parameters

(See Standalone Users Guide)

G-Wizard

NVRAM

Image File

(.nvram_image. hex)

G-Probe

NVRAM

LCD

Controller

Board

gm5115/25

OCM

Figure 27.

Programming OCM in Standalone Configuration

4.15.2 Full-Custom Configuration

In full-custom configuration the OCM executes a firmware program running from external ROM.

This is illustrated in Figure 26B. A parallel port with separate address and data busses is available

for this purpose. This port connects directly to standard, commercially available ROM or

programmable Flash ROM devices. Normally 64KB or 128KB of ROM is required.

Both instructions and data are fetched from external ROM on a cycle-by-cycle basis. The speed

of the accesses on the parallel port is determined by the gm5115/25 internal OCM_CLK. This in

turn determines the speed of the external ROM device. For example, if a 14.3 MHz crystal is

being used to produce TCLK, and the OCM_CLK is derived from TCLK, then a 45ns ROM can

be used.

To program gm5115/25 in full-custom configuration the content of the external ROM is

generated using Genesis software development tools G-Wizard and OSD-Workbench. This is

illustrated in Figure 28. G-Wizard is a GUI-based tool for capturing system information such as

panel timing, support modes, system configuration, etc. OSD-Workbench is a GUI based tool for

defining OSD menus and functionality.

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gm5115/25 Preliminary Data Sheet

G-Wizard

gm5115/25 Driver

OSD Workbench

gm5115/25 Driver

Firmware source files (*.c *.h)

Keil Compiler

External ROM

Image File (.hex)

ROM Programmer

ROM

LCD

Controller

Board

gm5115/25

OCM

Figure 28.

Programming the OCM in Full-Custom Configuration

Genesis recommends using Keil compiler (http://www.keil.com/) to compile the firmware source

code into a hex file. This hex file is then downloaded into the external ROM using commercially

available ROM programmers.

4.15.3 In-System-Programming (ISP) of FLASH ROM Devices

gm5115/25 has hardware to program FLASH ROM devices. In particular, the

GPIO11/ROM_WEn pin can be connected to the write enable of the FLASH ROM. Firmware is

then used to perform the writes using the gm5115/25 host registers.

4.15.4 UART Interface

The gm5115/25 OCM has an integrated Universal Asynchronous Remote Terminal (UART) port

that can be used as a factory debug port. In particular, the UART can be used to 1) read / write

chip registers (see section 4.17 below), 2) read / write to NVRAM (see section 4.15.1 above), and

3) read / write to FLASH ROM (see section 4.15.3 above).

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gm5115/25 Preliminary Data Sheet

The UART is connected to pins GPIO4/UART_DI and GPIO5/UART_DO. gm5115/25 has

serial-to-parallel conversion hardware which is accessed by firmware. The baud rate for serial

communication is determined by a gm5115/25 host register.

4.15.5 DDC2Bi Interface

The gm5115/25 also features hardware support for DDC2Bi communication over the DDC

channel of either the analog or DVI input ports. The specification for the DDC2Bi standard can

be obtained from VESA (www.vesa.org). The DDC2Bi port can be used as a factory debug port

or for field programming. In particular, the DDC2Bi port can be used to 1) read / write chip

registers (see section 4.17 below), 2) read / write to NVRAM (see section 4.15.1 above), and 3)

read / write to FLASH ROM (see section 4.15.3 above).

Two pairs of pins are available for DDC2Bi communication. For DDC2Bi communication over

the analog VGA connector pins GPIO22/HCLK and GPIO16/HFSn should be connected to the

DDC clock and data pins of the analog DSUB15 VGA connector. For DDC2Bi communication

over the DVI connector pins GPIO14/DDC_SCL and GPIO15/DDC_SDA should be connected

to the DDC clock and data pins of the DVI connector. gm5115/25 contains serial to parallel

conversion hardware, that is then accessed by firmware for interpretation and execution of the

DDC2Bi command set.

4.15.6 General Purpose Inputs and Outputs (GPIO)

The gm5115/25 has 21 general-purpose input/output (GPIO) pins. These are used by the OCM to

communicate with other devices in the system such as keypad buttons, NVRAM, LEDs, audio

DAC, etc. Each GPIO has independent direction control, open drain enable, for reading and

writing. Note that the GPIO pins have alternate functionality as described in Table 17 below.

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gm5115/25 Preliminary Data Sheet

Pin Name

Pin Number Alternate function

GPIO0/PWM0

40

41

42

43

44

45

46

47

39

48

49

50

51

52

6

PWM0, PWM1 and PWM2 back light intensity controls, as described in section 4.18.2 below.

GPIO1/PWM1

GPIO2/PWM2

GPIO3/TIMER1

GPIO4/UART_DI

GPIO5/UARD_D0

GPIO6/TCON_SHC

GPIO7/TCON_TDIV

GPIO8/IRQINn

GPIO9/TCON_ROE2

GPIO10/TCON_ROE3

GPIO11/ROM_WEn

GPIO12/NVRAM_SDA

GPIO13/NVRAM_SCL

GPIO14/DDC_SCL

GPIO15/DDC_SDA

GPIO16/HFSn

Timer1 input of the OCM.

OCM UART data in/out signals respectively (section 4.15.3 above).

Horizontal timing signals in the TCON column driver interface.

OCM external interrupt source (IRQINn).

Row output enables ROE2 and ROE3 in the TCON row driver interface.

Write enable for external ROM if programmable FLASH device is used (section 4.15.3 above).

Data and clock lines for master 2-wire serial interface to NVRAM when gm5115/25 is used in

standalone configuration (section Figure 26).

Clock and data lines for 2-wire serial interface connected to the Direct Data Channel (DDC) of the DVI

input, for passing HDCP keys (see 4.4.3 above) or for DDC2Bi communication (see 4.15.5 above).

7

205

1

Serial data line for 2-wire host interface or for DDC2Bi communication (see 4.15.5 above).

No alternative function.

GPIO17

GPIO18

208

207

206

4

GPIO19

GPIO20

GPIO21/IRQn

OCM interrupt output pin.

Serial input clock for 2-wire host interface or for DDC2Bi communication (see 4.15.5 above).

GPIO22/HCLK

204

Table 17. gm5115/25 GPIOs and Alternate Functions

4.16 Bootstrap Configuration Pins

During hardware reset, the external ROM address pins ROM_ADDR[15:0] are configured as

inputs. On the negating edge of RESETn, the value on these pins is latched and stored. This

value is readable by the on-chip microcontroller (or an external microcontroller via the host

interface). Install a 10K pull-up resistor to indicate a ‘1’, otherwise a ‘0’ is indicated because

ROM_ADDR[15:0] have a 60KΩ internal pull-down resistor.

Signal Name

Pin Name

Description

HOST_ADDR(4:0)

USER_BITS(4:0)

ROM_ADDR(4:0)

If using 2-wire host protocol, these are bits 4:0 of the serial bus device address.

Otherwise, these settings are available for reading from a status register but are otherwise unused by the

gm5115/25. Used for “soft” configuration settings.

HOST_ADDR(5)

HOST_ADDR(6)

ROM_ADDR5

ROM_ADDR6

If using 2-wire host protocol, this is bit 5 of serial the bus device address.

Otherwise, program this bit to 0.

If using 2-wire host protocol, this is bit 6 of the serial bus device address.

Otherwise, program this bit to 0.

HOST_PROTOCOL

HOST_PORT_EN

OCM_START

ROM_ADDR7

ROM_ADDR8

ROM_ADDR9

Program this bit to 0 for 2-wire host protocol operation.

Determines the operating condition of the OCM after HW reset:

0 = OCM remains in reset until enabled by register bit.

1 = OCM becomes active after OCM_CLK is stable.

USER_BITS(7:5)

OSC_SEL

ROM_ADDR(12:10)

ROM_ADDR13

These settings are available for reading from a status register but are otherwise unused by the gm5115/25.

Selects reference clock source:

0 = XTAL and TCLK pins are connected to a crystal oscillator (see Figure 4).

1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator (see Figure 7).

OCM_ROM_CNFG(1)

ROM_ADDR14

Together with OCM_CONTROL register (0x22) bit 4, this bit selects internal/external ROM configuration.

0 = All 48K of ROM is internal.

1 = All 48K of ROM is in external ROM using ROM_ADDR15:0 address outputs if

register 0x22 bit 4 is 0. If register 0x22 bit 4 is 1, 0-32K ROM is internal, and

32K~48K ROM is external using ROM_ADDR13:0 address outputs.

Table 18. Bootstrap Signals

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gm5115/25 Preliminary Data Sheet

4.17 Host Interface

gm5115/25 contains many internal registers that control its operation. These are described in the

gm5115 Family Register Listing (C5115-DSL-01).

A serial host interface is provided to allow an external device to peek and poke registers in the

gm5115/25. This is done using a 2-wire serial protocol. Note that 2-wire host interface requires

bootstrap settings as described in Table 18.

An arbitration mechanism ensures that register accesses from the OCM and the 2-wire host

interface port are always serviced (time division multiplexing).

4.17.1 Host Interface Command Format

Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two

nibbles respectively). These form an instruction byte, a device register address and/or one or

more data bytes. This is described in Table 19.

The first byte of each transfer indicates the type of operation to be performed by the gm5115/25.

The table below lists the instruction codes and the type of transfer operation. The content of bytes

that follow the instruction byte will vary depending on the instruction chosen. By utilizing these

modes effectively, registers can be quickly configured.

The two LSBs of the instruction code, denoted ‘A9’ and ‘A8’ in Table 19 below, are bits 9 and 8

of the internal register address respectively. Thus, they should be set to ‘00’ to select a starting

register address of less than 256, ‘01’ to select an address in the range 256 to 511, and ‘10’ to

select an address in the range 512 to 767. These bits of the address increment in Address

Increment transfers. The unused bits in the instruction byte, denoted by ‘x’, should be set to ‘1’.

Table 19. Instruction Byte Map

Bit

0 0 0 1 x x A9 A8

0 0 1 0 x x A9 A8

Operation Mode

Description

7 6 5 4 3 2

1 0

Write Address Increment

Allows the user to write a single or multiple bytes to a specified starting

address location. A Macro operation will cause the internal address pointer to

increment after each byte transmission. Termination of the transfer will cause

the address pointer to increment to the next address location.

Write Address No Increment

(for table loading)

1 0 0 1 x x A9 A8

1 0 1 0 x x A9 A8

Reserved

Allows the user to read multiple bytes from a specified starting address

location. A Macro operation will cause the internal address pointer to

increment after each read byte. Termination of the transfer will cause the

address pointer to increment to the next address location.

Read Address No Increment

(for table reading)

0 0 1 1 x x A9 A8

0 1 0 0 x x A9 A8

1 0 0 0 x x A9 A8

1 0 1 1 x x A9 A8

1 1 0 0 x x A9 A8

0 0 0 0 x x A9 A8

0 1 0 1 x x A9 A8

0 1 1 0 x x A9 A8

0 1 1 1 x x A9 A8

1 1 0 1 x x A9 A8

1 1 1 0 x x A9 A8

1 1 1 1 x x A9 A8

Reserved

Spare

No operation will be performed

4.17.2 2-wire Serial Protocol

The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional serial

data line HFSn (pin number 205). The bus master drives HCLK and either the master or slave

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gm5115/25 Preliminary Data Sheet

can drive the HFSn line (open drain) depending on whether a read or write operation is being

performed. The gm5115/25 operates as a slave on the interface.

The 2-wire protocol requires each device be addressable by a 7-bit identification number. The

gm5115/25 is initialized on power-up to 2-wire mode by asserting bootstrap pins

HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the rising

edge of RESETn (see Table 18). This provides flexibility in system configuration with multiple

devices that can have the same address.

A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the

figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while HCLK

is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn while HCLK

is held high) or by a START (to begin another transfer). The HFSn signal must be stable when

HCLK is high, it may only change when HCLK is low (to avoid being misinterpreted as START

or STOP).

HCLK

HFSn

1

2

3

4

5

6

7

8

9

1

2

8

9

A6

A5

A4

A3

A2

A1

A0

R/W ACK

D7

D6

D0

ACK

STOP

ADDRESS BYTE

Receiver acknowledges by holding SDA low

DATA BYTE

START

Figure 29.

2-Wire Protocol Data Transfer

Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of bytes

that can be transmitted per transfer is unrestricted. Each byte is transmitted with the most

significant bit (MSB) first. After the eight data bits, the master releases the HFSn line and the

receiver asserts the HFSn line low to acknowledge receipt of the data. The master device

generates the HCLK pulse during the acknowledge cycle. The addressed receiver is obliged to

acknowledge each byte that has been received.

The Write Address Increment and the Write Address No Increment operations allow one or

multiple registers to be programmed with only sending one start address. In Write Address

Increment, the address pointer is automatically incremented after each byte has been sent and

written. The transmission data stream for this mode is illustrated in Figure 30 below. The

highlighted sections of the waveform represent moments when the transmitting device must

release the HFSn line and wait for an acknowledgement from the gm5115/25 (the slave receiver).

1

2

3

4

5

6

7

8

9

1

2

9

1

2

3

4

5

6

7

8

9

HCLK

HFSn

1

2

3

4

5

6

7

8

9

DEVICE ADDRESS

R/W ACK

OPERATION CODE

REGISTER ADDRESS

DATA

A9 A8

ACK

Two MSBs of register address

START

STOP

Figure 30.

2-Wire Write Operations (0x1x & 0x2x)

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gm5115/25 Preliminary Data Sheet

The Read Address No Increment (0xA0) operation is illustrated in Figure 31. The highlighted

sections of the waveform represent moments when the transmitting device must release the HFSn

line and waits for an acknowledgement from the master receiver.

Note that on the last byte read, no acknowledgement is issued to terminate the transfer.

HCLK

DEVICE ADDRESS

R/W ACK

OPERATION CODE

REGISTERADDRESS

DEVICE ADDRESS

R/W ACK

DATA

ACK

DATA

HFSn

ACK

START

STOP

Figure 31.

2-Wire Read Operation (0xAx)

Please note that in all the above operations the operation code includes two address bits, as

described in Table 19.

4.18 Miscellaneous Functions

4.18.1 Power Down Operation

The gm5115/25 provides a low power state in which the clocks to selected parts of the chip may be

disabled (see Table 21).

4.18.2 Pulse Width Modulation (PWM) Back Light Control

Many of today’s LCD back light inverters require both a PWM input and variable DC voltage to

minimize flickering (due to the interference between panel timing and inverter’s AC timing), and

adjust brightness. Most LCD monitor manufacturers currently use a microcontroller to provide

these control signals. To minimize the burden on the external microcontroller, the gm5115/25

generates these signals directly.

There are three pins available for controlling the LCD back light, PWM0 (GPIO0), PWM1

(GPIO1) and PWM2 (GPIO2). The duty cycle of these signals is programmable. They may be

connected to an external RC integrator to generate a variable DC voltage for a LCD back light

inverter. Panel HSYNC is used as the clock for a counter generating this output signal.

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gm5115/25 Preliminary Data Sheet

5. ELECTRICAL SPECIFICATIONS

The following targeted specifications have been derived by simulation.

5.1 Preliminary DC Characteristics

Table 20. Absolute Maximum Ratings

PARAMETER

SYMBOL

V_{VDD_3.3}

V_{VDD_2.5}

V_IN5Vtol

V_IN

MIN

-0.3

TYP

MAX

3.6

2.75

5.5

UNITS

3.3V Supply Voltages ^(1,2)

2.5V Supply Voltages ^(1.2)

Input Voltage (5V tolerant inputs) ^(1,2)

Input Voltage (non 5V tolerant inputs) ^(1,2)

Electrostatic Discharge

V

kV

mA

°C

3.6

V_ESD

I_LA

±2.0

±100

70

125

Latch-up

Ambient Operating Temperature

Storage Temperature

T_A

T_STG

T_J

0

-40

0

Operating Junction Temp.

Thermal Resistance (Junction to Air) Natural Convection ⁽³⁾

θ

JA_5115

gm5115

gm5125

32.4

22.0

°C/W

JA_5125

Thermal Resistance (Junction to Case) Convection ⁽⁴⁾

gm5115

gm5125

Soldering Temperature (30 sec.)

θ

JC_5115

13.9

10.1

220

°C/W

JC_5125

T_SOL

T_VAP

°C

Vapor Phase Soldering (30 sec.)

NOTE (1): All voltages are measured with respect to GND

NOTE (2): Absolute maximum voltage ranges are for transient voltage excursions.

NOTE (3): Package thermal resistance is based on a PCB with one signal plane and two power planes. Package θ_JAis improved on a PCB with

four or more layers

NOTE (4): Based on the figures for the Operating Junction Temperature, θ_JCand Power Consumption in Table 21, the typical case temperature

is calculated as T_C= T_J- P₅₁₁₅x θ_JC. This equals 104 degrees Celsius for gm5115 and 106 degrees Celsius for gm5125.

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gm5115/25 Preliminary Data Sheet

Table 21. DC Characteristics

PARAMETER

SYMBOL

POWER

MIN

TYP

MAX

UNITS

Power Consumption @ 96 MHz (gm5115)

Power Consumption @ 135 MHz (gm5125)

Power Consumption @ Low Power Mode ⁽¹⁾

3.3V Supply Voltages (AVDD and RVDD)

2.5V Supply Voltages (VDD and CVDD)

Supply Current @ CLK = 96 MHz (gm5115)

• 2.5V digital supply ⁽²⁾

P₅₁₁₅

P₅₁₂₅

P_LP

1.5

1.8

0.15

3.3

2.5

400

W

V

mA

V_{VDD_3.3}

V_{VDD_2.5}

I₅₁₁₅

I_{5115_2.5_VDD}

I_{5115_2.5_AVDD}

I_{5115_3.3_VDD}

I_{5115_3.3_AVDD}

3.15

2.35

3.45

2.65

360⁽⁶⁾

40⁽⁶⁾

• 2.5V analog supply ⁽³⁾

50⁽⁶⁾

• 3.3V digital supply ⁽⁴⁾

150⁽⁶⁾

• 3.3V analog supply ⁽⁵⁾

Supply Current @ CLK =135MHz (gm5125)

I₅₁₂₅

500

50

mA

500⁽⁶⁾

50⁽⁶⁾

• 2.5V digital supply ⁽²⁾

I_{5125_2.5_VDD}

I_{5125_2.5_AVDD}

I_{5125_3.3_VDD}

I_{5125_3.3_AVDD}

• 2.5V analog supply ⁽³⁾

60⁽⁶⁾

• 3.3V digital supply ⁽⁴⁾

150⁽⁶⁾

• 3.3V analog supply ⁽⁵⁾

Supply Current @ Low Power Mode*

I_LP

INPUTS

V_IH

V_IL

V_IHC

V_ILC

I_IH

I_IL

C_IN

High Voltage

2.0

GND

2.4

GND

-25

V_DD

0.8

V_DD

0.4

25

8

V

Low Voltage

Clock High Voltage

Clock Low Voltage

High Current (V_IN= 5.0 V)

Low Current (V_IN= 0.8 V)

Capacitance (V_IN= 2.4 V)

V

µA

pF

-25

OUTPUTS

High Voltage (I_OH= 7 mA)

Low Voltage (I_OL= -7 mA)

Tri-State Leakage Current

V_OH

V_OL

I_OZ

2.4

GND

-25

V_DD

0.4

25

V

µA

NOTE (1): Low power figures result from setting the ADC, DVI, and clock power down bits so that only the micro-controller is running.

NOTE (2): Includes pins CVDD_2.5, VDD1_ADC_2.5, VDD2_ADC_2.5, VDD_RX0_2.5, VDD_RX1_2.5 and VDD_RX2_2.5.

NOTE (3): Includes only VDD_RXPLL_2.5.

NOTE (4): Includes pins VDD_DPLL, VDD_SDDS, VDD_DDDS and RVDD.

NOTE (5): Includes pins AVDD_RED, AVDD_GREEN, AVDD_BLUE, AVDD_IMB, AVDD_RX0, AVDD_RX1, AVDD_RX2,

AVDD_RXC, AVDD_RPLL, AVDD_SDDS and AVDD_DDDS.

NOTE (6): Maximum current figures are provided for the purposes of selecting an appropriate power supply circuit.

46

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

5.2 Preliminary AC Characteristics

All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum

operating conditions used were: T_DIE= 0 to 125° C, Vdd = 2.35 to 2.65V, Process = best to worst, C_L=

16pF for all outputs.

Table 22. Maximum Speed of Operation

Clock Domain

Max Speed of Operation

24 MHz (14.3MHz recommended)

165 MHz

Main Input Clock (TCLK)

DVI Differential Input Clock

ADC Clock (ACLK)

162.5 MHz

HCLK Host Interface Clock (2-wire protocol)

Input Format Measurement Clock (IFM_CLK)

Reference Clock (RCLK)

On-Chip Microcontroller Clock (OCM_CLK)

Display Clock (DCLK)

5 MHz

50MHz (14.3MHz recommended)

200MHz (200MHz recommended)

100 MHz

135 MHz

Table 23. Display Timing and DCLK Adjustments

DP_TIMING ->

Tap 0 (default)

Tap 1

Tap 2

Tap 3

Min

Max

Min

Max

Min

Max

Min

Max

(ns)

0.5

0.0

0.5

(ns)

-0.5

-1.0

-0.5

(ns)

-1.5

-2.0

-1.5

(ns)

Propagation delay from DCLK to DA*/DB*

1.0

0.5

1.0

4.5

3.5

2.5

1.5

Propagation delay from DCLK to DHS

Propagation delay from DCLK to DVS

Propagation delay from DCLK to DEN

Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the propagation

delay between DCLK and its related signals.

Table 24. 2-Wire Host Interface Port Timing

Parameter

Symbol

MIN

TYP

MAX

Units

SCL HIGH time

SCL LOW time

SDA to SCL Setup

SDA from SCL Hold

Propagation delay from SCL to SDA

T_SHI

T_SLO

T_SDIS

T_SDIH

T_SDO3

1.25

30

20

10

us

ns

150

Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)

47

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

6. ORDERING INFORMATION

Order Code

Application

Package

Temperature

Range

gm5115

gm5115-H ⁽¹⁾

gm5125

XGA

SXGA

208-pin PQFP

0-70°C

gm5125-H ⁽¹⁾

Note (1): gm5115-H and gm5125-H versions will be sold only to HDCP-licensed customers.

48

June 2002

C5115-DAT-01H

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

7. MECHANICAL SPECIFICATIONS

Figure 32.

gm5115/25 208-pin PQFP Mechanical Drawing

D

H

D

208

157

156

1

105

52

53

104

e

b

c

See Detail A

L

y

Seating Plane

1

L

Detail A

Dimension in mm

Min Nom Max

Symbol

3.92

0.25

3.15

0.18

0.13

4.07

A

A¹

3.23

3.30

0.28

0.23

A2

b

c

27.90 28.00 28.10

D

28.10

28.00

27.90

E

0.50 BSC

e

D

31.20 31.45

H

30.95

31.45

0.95

30.95 31.20

E

H

L

0.65

0.80

1.60 REF

L1

0.10

7

y

0

49

June 2002

C5115-DAT-01H

型号:	GM5120
生命周期：	Transferred
IHS 制造商：	GENESIS MICROCHIP
Reach Compliance Code：	unknown
风险等级：	5.63
Is Samacsys：	N
Base Number Matches：	1

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