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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • GS4881-IDA
  • 数量2500 
  • 厂家GENNUM 
  • 封装DIP8 
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  • GS4881
  • 数量4394 
  • 厂家GENNUM 
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  • 北京元坤伟业科技有限公司

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  • GS4881-IKA
  • 数量5000 
  • 厂家GENNUM 
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  • 深圳市宏世佳电子科技有限公司

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  • GS4881-CTA
  • 数量3570 
  • 厂家GENNUM 
  • 封装8SOP 
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  • 万三科技(深圳)有限公司

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  • GS4881-IKAE3
  • 数量660000 
  • 厂家Semtech(升特) 
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  • 深圳市惊羽科技有限公司

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  • GS4881-CKA
  • 数量18800 
  • 厂家GENNUM 
  • 封装SOP-8.贴片 
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  • 深圳市惊羽科技有限公司

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  • GS4881-IKAE3
  • 数量6328 
  • 厂家SEMTECH 
  • 封装SOIC-8 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GS4881
  • 数量25682 
  • 厂家GENNUM 
  • 封装DIP8 
  • 批号2023+ 
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  • 深圳市美思瑞电子科技有限公司

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  • GS4881-CKAE3
  • 数量12245 
  • 厂家SEMTECH/美国升特 
  • 封装SOP8 
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  • 现货,原厂原装假一罚十!
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  • 深圳市硅诺电子科技有限公司

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  • GS4881
  • 数量6800 
  • 厂家GENNUM 
  • 封装DIP8 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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  • 上海金庆电子技术有限公司

     该会员已使用本站15年以上
  • GS4881-CTA
  • 数量1421 
  • 厂家GENNUM 
  • 封装SOP8 
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  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • GS4881-CKAE3
  • 数量8999 
  • 厂家√ 欧美㊣品 
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  • 批号16+ 
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  • GS4881图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • GS4881
  • 数量22314 
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  • 封装SOP 
  • 批号2020+ 
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  • 深圳市浩兴林电子有限公司

     该会员已使用本站16年以上
  • GS4881-CKA
  • 数量1774 
  • 厂家GENNUM 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GS4881
  • 数量65000 
  • 厂家GENNUM 
  • 封装SOP8 
  • 批号23+ 
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  • GS4881图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • GS4881
  • 数量8800 
  • 厂家 
  • 封装N/A 
  • 批号2024 
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  • GS4881图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • GS4881
  • 数量68000 
  • 厂家GENNUM 
  • 封装SOP-8 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • GS4881
  • 数量12568 
  • 厂家GENNUM 
  • 封装SOP8 
  • 批号▊ NEW ▊ 
  • ★◆█◣【100%原装正品】★价格最低,不要错过★!量大可定!
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  • GS4881CKAE3图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GS4881CKAE3
  • 数量13880 
  • 厂家Semtech Corporation 
  • 封装8SOIC 
  • 批号21+ 
  • 公司只售原装 支持实单
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  • 深圳市隆鑫创展电子有限公司

     该会员已使用本站15年以上
  • GS4881-CKAE3
  • 数量30000 
  • 厂家NXP 
  • 封装TO252 
  • 批号2022+ 
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  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • GS4881-IDA
  • 数量6500000 
  • 厂家SEMTECH 
  • 封装原厂原装 
  • 批号22+ 
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  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • GS4881
  • 数量99000 
  • 厂家GENNUM 
  • 封装SOP8 
  • 批号23+ 
  • 一级代理进口原装现货、假一罚十价格合理
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • GS4881
  • 数量1023 
  • 厂家GENNUM 
  • 封装SOP 
  • 批号22+ 
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  • 深圳市晶美隆科技有限公司

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  • GS4881-CKA
  • 数量65800 
  • 厂家GENNUM 
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  • 深圳市晨豪科技有限公司

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  • GS4881
  • 数量89630 
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产品型号GS4881的概述

芯片GS4881的概述 GS4881是一款专为高性能模拟信号处理设计的集成电路,广泛应用于音频、视频及其他信号的处理与转换。该芯片是在多个行业中备受青睐,因其具有较高的抗干扰能力和良好的线性度,能够满足多种高精度信号应用的需求。 GS4881属于高频低噪声放大器,其设计目标是在保证信号完整性的同时,实现低功耗的电源管理。因此,它在消费电子、通信设备、医疗仪器及工业控制系统等领域都有着广泛的应用。GS4881的核心功能包括信号放大、滤波及多种模拟信号处理,其精确度和稳定性使其成为行业内的热门选择。 芯片GS4881的详细参数 GS4881的参数可以从几个关键维度进行分析,包括电气特性、机械特性和应用范围。以下为GS4881的一些主要技术参数: - 工作电压:3.0 V至5.5 V - 静态功耗:小于10 mA - 信噪比(SNR):高达100 dB - 增益:具有可调增益范围,最大增益可...

产品型号GS4881的Datasheet PDF文件预览

GS1881, GS4881, GS4981  
Monolithic Video Sync Separators  
DATA SHEET  
FEATURES  
DESCRIPTION  
• noise tolerant odd/even flag, back porch and  
horizontal sync pulse  
The GS1881, GS4881 and GS4981 are general purpose sync  
separators for use in a wide variety of video applications. The  
devices extract the timing information from composite video  
signals with scan rates from 15 to 130 kHz.  
• fast recovery from impulse noise  
• excellent temperature stability  
TheGS1881isadrop-inreplacementfortheindustrystandard  
LM1881 with much improved performance. The device  
generates composite sync, vertical sync, back porch and  
odd/evenfieldsignals. TheGS4881isidenticaltotheGS1881  
butfeaturesanoiseimmunebackporchpulsewhichmaintains  
a constant H rate during the vertical interval. The GS4981 is  
identicaltotheGS4881,exceptthatitprovideshorizontalsync  
in place of the odd/even output.  
• 0.5 V to 4 Vpp input signal amplitude with 5 V  
supply  
• well-controlled clamp discharge current and  
slicing level  
• programmable horizontal scan rate (up to 130 kHz)  
• composite, vertical, back porch, odd/even  
All three devices feature a self-adjusting windowing circuit for  
noise immunity, which synchronizes to H rate. This  
windowing circuit determines the odd or even field  
in the GS1881 and GS4881, gates the back porch pulse in  
the GS4881 and GS4981, and generates the horizontal sync  
output in the GS4981.  
(GS1881, GS4881), horizontal (GS4981) outputs  
• predictable vertical output pulse width with  
default trigger for non-standard video signals  
• 5 V to 12 V supply voltage range  
• pin compatible with LM1881 sync separator  
The devices feature an improved input stage which ensures  
that the input signal is sliced at a predictable point due to  
well-controlled input clamp discharge current and sync  
slicing level. A missing pulse detector enables the devices to  
recoverquicklyfromimpulsenoisedisturbancesbytemporarily  
increasing the clamp discharge current by roughly ten times.  
The input stage will operate with signals from 0.5 to 4 volts  
peak to peak with a 5 volt supply.  
SELECTION CHART  
APPLICATION  
CHOOSE DEVICE:  
Direct LM1881 Replacement  
with Improved Performance  
GS1881  
The GS1881, GS4881 and GS4981 also feature a predictable  
verticaloutputpulsewidthwithadefaulttriggerfornon-standard  
video signals. All three are available in commercial and  
industrial temperature ranges and are packaged in both DIP  
and SOIC.  
New Applications  
Substitution for LM1881  
GS4881  
GS4981  
New Applications Requiring  
Horizontal Sync Output  
PIN CONNECTIONS  
GS4981  
GS1881, GS4881  
COMPOSITE  
COMPOSITE  
SYNC OUT  
V
8
7
6
5
1
2
3
4
V
8
7
6
5
1
2
3
4
SYNC OUT  
cc  
cc  
COMPOSITE  
VIDEO IN  
HORIZONTAL  
COMPOSITE  
VIDEO IN  
ODD/EVEN  
VERTICAL  
SYNC OUT  
VERTICAL  
SYNC OUT  
R
R
SET  
SET  
GROUND  
BACK PORCH  
GROUND  
BACK PORCH  
8 PIN DIP  
8 PIN SOIC  
8 PIN DIP  
8 PIN SOIC  
Patent No. 5,432,559  
Document No. 520 - 23 - 03  
Revision Date: October 1995  
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-2055  
Japan Branch: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3247-8838 fax (03) 3247-8839  
(V = 5 V, R  
= 680 k, T = 25° C, unless otherwise specified)  
A
GS1881 ELECTRICAL CHARACTERISTICS  
CC  
SET  
PARAMETER  
CONDITIONS  
MIN  
TYP  
5
MAX  
13.2  
6.5  
UNITS  
V
Supply Voltage  
4.5  
Supply Current  
Outputs at Logic 1  
VCC = 5 V  
VCC = 12 V  
-
-
4.6  
5.0  
mA  
7.0  
mA  
Video Input (Pin 2)  
(a) Signal Level  
VCC = 5 V  
0.5  
500  
9
-
4
850  
13  
Vp-p  
µA  
µA  
µA  
µs  
(b) Clamp Current  
Charge  
650  
11  
Discharge - normal  
- Nosync flag raised  
65  
64  
-
95  
115  
130  
-
(c) Delay to raising of Nosync flag Video input held high  
(d) Sync Tip Clamp Voltage  
95  
1.55  
77  
V
Sync Slice Level  
Relative to sync tip clamp voltage  
70  
1.14  
84  
mV  
V
RSET Pin Reference Voltage (Pin 6) See Note 1  
1.24  
1.34  
Composite Sync Out (Pin 1)  
Delay from Video  
See Note 2  
40  
60  
80  
ns  
C
C
= 15p  
= 15p  
L
L
Back Porch Pulse Out (Pin 5)  
(a) Delay from Rising  
Edge of Sync  
400  
2.0  
500  
2.5  
650  
3.2  
ns  
(b) Pulse Width  
µs  
Vertical Sync Out (Pin 3)  
(a) Pulse Width  
Serrations during vertical interval  
No serrations during the vertical interval  
Modified RSET  
197.7  
48  
197.7  
197.7  
82  
µs  
µs  
(b) Default Starting Time  
Horizontal Scan Rate  
Logic Outputs  
65  
-
15  
130  
kHz  
(a) V  
IOH = 40 µA  
IOH = 1.6 mA  
IOL = -1.6 mA  
VCC = 5 V  
VCC = 12 V  
VCC = 5 V  
VCC = 12 V  
4.2  
11.2  
2.4  
9.4  
-
4.6  
11.6  
3.4  
-
V
V
V
V
V
OH  
-
-
10.4  
0.3  
-
(b) V  
0.6  
OL  
Note 1: When placing the R  
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close  
SET  
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.  
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.  
ORDERING INFORMATION  
Part Number  
GS1881 - CDA  
GS1881 - CKA  
GS1881 - CTA  
GS1881 - IDA  
GS1881 - IKA  
GS1881 - ITA  
Package Type  
8 PDIP  
Temperature Range  
0° to 70° C  
8 SOIC  
0° to 70° C  
8 TAPE  
0° to 70° C  
8 PDIP  
-25° to 85° C  
-25° to 85° C  
-25° to 85° C  
CAUTION  
ELECTROSTATIC  
SENSITIVE DEVICES  
8 SOIC  
8 TAPE  
DO NOT OPEN PACKAGES OR HANDLE  
EXCEPT AT A STATIC-FREE WORKSTATION  
520 - 23 - 03  
2
(V = 5 V, R  
= 680 k, T = 25° C, unless otherwise specified)  
A
GS4881 ELECTRICAL CHARACTERISTICS  
CC  
SET  
PARAMETER  
CONDITIONS  
MIN  
TYP  
5
MAX  
13.2  
6.5  
UNITS  
V
Supply Voltage  
4.5  
Supply Current  
Outputs at Logic 1  
VCC = 5 V  
VCC = 12 V  
-
-
4.6  
5.0  
mA  
7.0  
mA  
Video Input (Pin 2)  
(a) Signal Level  
VCC = 5 V  
0.5  
500  
9
-
4
850  
13  
Vp-p  
µA  
µA  
µA  
µs  
V
(b) Clamp Current  
Charge  
650  
11  
Discharge - normal  
- Nosync flag raised  
65  
64  
-
95  
115  
130  
-
(c) Delay to raising of Nosync flag Video input held high  
(d) Sync Tip Clamp Voltage  
95  
1.55  
77  
Sync Slice Level  
Relative to sync tip clamp voltage  
70  
1.14  
84  
mV  
V
RSET Pin Reference Voltage (Pin 6) See Note 1  
1.24  
1.34  
Composite Sync Out (Pin 1)  
Delay from Video  
See Note 2  
40  
60  
80  
ns  
C
C
= 15p  
= 15p  
L
L
Back Porch Pulse Out (Pin 5)  
(a) Delay from Rising  
Edge of Sync  
400  
2.0  
H
500  
2.5  
H
650  
3.2  
H
ns  
(b) Pulse Width  
µs  
(c) Occurence Rate  
Vertical Sync Out (Pin 3)  
(a) Pulse Width  
Serrations during vertical interval  
No serrations during the vertical interval  
Modified RSET  
197.7  
48  
197.7  
197.7  
82  
µs  
µs  
(b) Default Starting Time  
Horizontal Scan Rate  
Logic Outputs  
65  
-
15  
130  
kHz  
(a) V  
IOH = 40 µA  
IOH = 1.6 mA  
IOL = -1.6 mA  
VCC = 5 V  
VCC = 12 V  
VCC = 5 V  
VCC = 12 V  
4.2  
11.2  
2.4  
9.4  
-
4.6  
11.6  
3.4  
-
V
V
V
V
V
OH  
-
-
10.4  
0.3  
-
(b) V  
0.6  
OL  
Note 1: When placing the R  
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close  
SET  
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.  
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.  
ORDERING INFORMATION  
Part Number  
GS4881 - CDA  
GS4881 - CKA  
GS4881 - CTA  
GS4881 - IDA  
GS4881 - IKA  
GS4881 - ITA  
Package Type  
8 PDIP  
Temperature Range  
0° to 70° C  
8 SOIC  
0° to 70° C  
8 TAPE  
0° to 70° C  
8 PDIP  
-25° to 85° C  
-25° to 85° C  
-25° to 85° C  
8 SOIC  
8 TAPE  
520 - 23 - 03  
3
(V = 5 V, R  
= 680 k, T = 25° C, unless otherwise specified)  
A
GS4981 ELECTRICAL CHARACTERISTICS  
CC  
SET  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Supply Voltage  
4.5  
5
13.2  
6.5  
V
Supply Current  
Outputs at Logic 1  
VCC = 5 V  
VCC = 12 V  
-
-
4.6  
5.0  
mA  
mA  
7.0  
Video Input (Pin 2)  
(a) Signal Level  
VCC = 5 V  
0.5  
500  
9
-
650  
11  
4
850  
13  
Vp-p  
µA  
µA  
µA  
µs  
(b) Clamp Current  
Charge  
Discharge - normal  
- Nosync flag raised  
65  
64  
-
95  
115  
130  
-
(c) Delay to raising of Nosync flag Video input held high  
(d) Sync Tip Clamp Voltage  
95  
1.55  
77  
V
Sync Slice Level  
Relative to sync tip clamp voltage  
70  
1.14  
84  
mV  
V
RSET Pin Reference Voltage (Pin 6) See Note 1  
1.24  
1.34  
Composite Sync Out (Pin 1)  
Delay from Video  
See Note 2  
40  
60  
80  
ns  
C
C
= 15p  
= 15p  
L
L
Back Porch Pulse Out (Pin 5)  
(a) Delay from Rising  
Edge of Sync  
400  
2.0  
H
500  
2.5  
H
650  
3.2  
H
ns  
(b) Pulse Width  
µs  
(c) Occurence Rate  
Vertical Sync Out (Pin 3)  
(a) Pulse Width  
Serrations during vertical interval  
197.7  
48  
197.7  
65  
197.7  
82  
µs  
µs  
(b) Default Starting Time  
Horizontal Sync Out (Pin 7)  
(a) Delay from Video  
(b) Pulse Width  
No serrations during the vertical interval  
C
= 15p  
L
90  
5.0  
15  
190  
7.0  
-
290  
9.0  
ns  
µs  
Horizontal Scan Rate  
Logic Outputs  
Modified RSET  
130  
kHz  
(a) V  
I
I
= 40 µA  
V = 5 V  
CC  
4.2  
11.2  
2.4  
9.4  
-
4.6  
11.6  
3.4  
-
V
V
V
V
V
OH  
OH  
V
= 12 V  
= 5 V  
-
-
CC  
CC  
= 1.6 mA  
V
OH  
Note 3  
= -1.6 mA  
V
= 12 V  
10.4  
0.3  
-
CC  
(b) V  
I
0.6  
OL  
OL  
Note 1: When placing the R  
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close  
SET  
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.  
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.  
Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10 kpull-up to V  
.
CC  
ORDERING INFORMATION  
Part Number  
GS4981 - CDA  
GS4981 - CKA  
GS4981 - CTA  
GS4981 - IDA  
GS4981 - IKA  
GS4981 - ITA  
Package Type  
8 PDIP  
Temperature Range  
0° to 70° C  
8 SOIC  
0° to 70° C  
8 TAPE  
0° to 70° C  
8 PDIP  
-25° to 85° C  
-25° to 85° C  
-25° to 85° C  
8 SOIC  
8 TAPE  
520 - 23 - 03  
4
TYPICAL PERFORMANCE CHARACTERISTICS (V = 5V, T = 25° C unless otherwise shown)  
S
A
700  
600  
500  
400  
300  
200  
100  
0
70  
60  
50  
40  
30  
20  
10  
0
15  
35  
55  
75  
95  
115  
135  
0
100  
200  
300  
400  
500  
600  
700  
SCAN RATE (kHz)  
RSET (k)  
Fig. 1  
R
vs Scan Rate  
SET  
Fig. 2 Vertical Sync Default Starting Time  
vs R  
SET  
700  
600  
500  
400  
300  
200  
100  
0
3000  
2500  
2000  
1500  
1000  
500  
0
0
100  
200  
300  
400  
500  
600  
700  
0
100  
200  
300  
400  
500  
600  
700  
RSET (k)  
RSET (k)  
Fig. 4 Back Porch Width vs R  
SET  
Fig. 3 Back Porch Delay vs R  
SET  
8000  
7000  
6000  
5000  
4000  
3000  
2000  
1000  
0
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
100  
200  
300  
400  
500  
600  
700  
0
100  
200  
300  
400  
500  
600  
700  
RSET (k)  
RSET (k)  
Fig. 5 Horizontal Width vs R  
SET  
Fig. 6 Nosync Delay Time vs R  
SET  
520 - 23 - 03  
5
TEMPERATURE CHARACTERISTICS  
(VS = 5V, RSET = 680 kunless otherwise shown)  
Commercial Temperature Range (0 - 70 °C)  
10  
8
850  
740  
650  
550  
450  
350  
6
4
2
0
-2  
-4  
-6  
-25 -15 -5  
5
15  
25  
35  
45  
55  
65 75 85  
-25 -15 -5  
5
15  
25  
35  
45  
55  
65 75 85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Fig. 8 Clamping Current vs Temperature  
Fig. 7 Composite Sync Delay Variation  
vs Temperature  
125  
30  
20  
10  
0
100  
75  
50  
25  
0
-25  
-50  
-75  
100  
-125  
-10  
-20  
-25 -15  
-5  
5
15  
25 35  
45  
55  
65 75 85  
-25 -15 -5  
5
15  
25  
35  
45  
55  
65 75 85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Fig. 9 Back Porch Delay Variation  
vs Temperature  
Fig. 10 Back Porch Width Variation  
vs Temperature  
600  
500  
400  
300  
200  
100  
0
25  
20  
15  
10  
5
-100  
-200  
-300  
0
-5  
-25 -15 -5  
5
15  
25  
35  
45  
55  
65 75 85  
-25 -15 -5  
5
15  
25  
35  
45  
55  
65 75 85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Fig. 11 Horizontal Delay Variation  
vs Temperature  
Fig. 12 Horizontal Width Variation  
vs Temperature  
520 - 23 - 03  
6
BACK PORCH OUTPUT (pin 5)  
CIRCUIT DESPCRIPTION  
The block diagrams for the GS1881, GS4881 and GS4981,  
are shown in Figures 17 through 19, with timing diagrams for  
the devices shown in Figure 20.  
InanNTSCcompositevideosignal,horizontalsyncpulsesare  
followed by the back porch interval. The device generates a  
negative going pulse on pin 5 during this time. It is delayed  
typically 500 ns from the rising edge of sync and has a typical  
width of 2.5µs. Both of these times are set by the external RSET  
resistor.  
When stimulated by a composite input signal, the GS1881  
and GS4881 sync separators output composite sync,  
vertical sync, back porch, and odd/even field information.  
The GS4981 substitutes the odd/even output of the GS4881  
with a horizontal output. An external resistor on pin 6 is used  
todefineinternalcurrentsallowingthedevicestoaccommodate  
horizontal scan rates from 15 kHz to 130 kHz.  
During the pre-equalizing, vertical sync, and post-equalizing  
periods, composite sync doubles in frequency. The GS4881  
and GS4981 maintain the back porch output at the horizontal  
rate due to Back Porch Enable (BPEN), generated by the  
internal windowing circuit, which forces back porch to be  
asserted at the horizontal rate. This gating circuit is also the  
reason for the excellent impulse noise immunity of the back  
porch output as shown in Figure 14.  
COMPOSITE VIDEO INPUT (pin 2) and COMPOSITE  
SYNC OUTPUT (pin 1)  
Composite video is AC coupled via an external coupling  
capacitor to pin 2. The device clamps the sync tip of the input  
video to 1.5 V ( Vclamp ) and then slices at 77 mV above the  
clamp voltage ( Vslice ). The resultant signal, provided at  
pin 1, is a reproduction of the input signal with the active video  
portion removed. As Vclamp and Vslice are supply and input  
signal independent, for 0.5 V p-p signals (sync height of 143  
mV) slicing will occur at just above the 50% point and for 2 V  
p-p signals (sync height of 572 mV) slicing will occur at  
approximately 13% of sync height.  
Video  
Input  
Impulse  
Noise  
Back  
Porch  
Output  
GS4881  
GS4981  
The video signal path and composite sync slicing circuitry  
have been optimized and compensated to achieve a low  
propagationdelaythatisstableovertemperature. Thetypical  
delay is 60 ns with less than 3 ns drift over the commercial  
temperature range.  
Fig. 14 Back Porch Noise Immunity  
The typical input clamp discharge current is 11µA. This  
current is optimal under normal operating circumstances but  
needs to be increased when the clamp is trying to recover  
from negative going impulse noise. The device improves the  
recovery time by raising a NOSYNC flag when there has not  
been a sync pulse for approximately 11/2 horizontal lines.  
When this flag is raised the discharge current is increased by  
85 µA so that the recovery time is sped up by nearly 10 times.  
Figure 13 shows a comparison between the recovery times  
with and without the increased discharge current.  
VIDEO INPUT  
The GS1881 does not gate the Back Porch which allows for  
total pin compatibility with the LM1881.  
VERTICAL SYNC OUTPUT (pin 3)  
The vertical sync interval is detected by integrating the  
composite sync pulses. The first broad vertical sync pulse  
causes an internal capacitor to charge past a fixed threshold  
and raises an internal vertical flag. Once the vertical flag is  
raised, the positive edge of the next serration clocks out the  
vertical output. When the vertical sync interval ends, the first  
post equalizing pulse is unable to charge the capacitor  
sufficiently, causing the internal vertical flag to go high. The  
rising edge of the second post-equalizing pulse then clocks  
out the high flag to end the vertical sync pulse. The vertical  
output is clocked in and out and therefore is a fixed width of  
197.7µs (3H + 4.7 µs + 2.3 µs). In the case of a non-standard  
vertical interval that has no serrations, a second internal  
capacitor is charged and clocks the vertical pulse out after  
typically 65µs. In this case the end of the vertical pulse will still  
betherisingedgeofthesecondpost-equalizingpulse. Asthe  
vertical detector is designed as a true integrator, it provides  
improved noise immunity.  
IMPULSE NOISE  
COMPOSITE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM1881)  
RECOVERY TIME T1  
COMPOSITE SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS1881, GS4881, GS4981)  
RECOVERY TIME  
T1 / 10  
Fig. 13 Impulse Noise: Recovery Time Comparison  
520 - 23 - 03  
7
HORIZONTAL OUTPUT (pin 7 GS4981)  
ODD/EVEN FIELD OUTPUT (pin 7 GS1881, GS4881)  
As mentioned above, the odd/even field output of the  
GS1881 and GS4881 is generated by comparing vertical  
sync with an internal horizontal sync signal. This horizontal  
sync signal is a true horizontal signal (i.e. maintained during  
the vertical interval) and is outputted on pin 7 for the  
GS4981. A delay of 190 ns from the video input and a width  
of 6.5 µs are typically characteristics for this signal.  
NTSC PAL and SECAM composite video standards are  
interlaced video schemes and therefore have odd and even  
fields. For odd fields the first broad vertical sync pulse is  
coincident with the start of horizontal, while for even fields the  
firstbroadverticalsyncpulsestartsinthemiddleofahorizontal  
line. Thereforebycomparingtheverticalsyncwithan internally  
generated horizontal sync the odd/even field information is  
determined. This output is clocked out by the falling edge of  
vertical sync. The odd/even output is low during even fields  
and high during odd fields. This method of detecting odd and  
even fields is very noise tolerant.  
The windowing circuit which generates horizontal provides  
excellent impulse noise immunity as shown in Figure 16. This  
output buffer is an open collector stage with an internal  
10 kpull up resistor.  
Noise during the pre-equalizing pulses does not affect the  
output since the field decision is made at the beginning of the  
vertical interval. This noise immunity is displayed in Figure 15  
in which an extra pre-equalizing pulse has been added to the  
video input with no negative effect on the odd/even field  
information.  
Video  
Input  
Impulse  
Noise  
Video  
Input  
Horizontal  
Output  
Impulse  
Noise  
Fig. 16 Horizontal Output  
Even  
Odd  
Odd/Even  
Output  
Fig. 15 Odd/Even Output  
520 - 23 - 03  
8
C SYNC  
COMPOSITE  
SYNC OUTPUT  
(Pin 1)  
-
VIDEO  
INPUT  
(Pin 2)  
-
+
V SLICE  
HORIZONTAL  
+
-
+
ODD / EVEN  
OUTPUT  
(Pin 7)  
D
Q
Q
Q
Q
D
G
V CLAMP  
WINDOWING  
CIRCUIT  
CLK  
85µ  
11µ  
NOSYNC  
V
CC  
VERTICAL SYNC  
OUTPUT  
D
Q
Q
(Pin 8)  
VOLTAGE  
REGULATOR  
VERTICAL  
DETECTOR  
(PIN 3)  
CLK  
1.2V  
BACK PORCH  
OUTPUT  
(Pin 5)  
R_SET  
(Pin 6)  
BACK PORCH  
DETECTOR  
TIMING  
CURRENTS  
Fig. 17 GS1881 Block Diagram  
C SYNC  
COMPOSITE  
SYNC OUTPUT  
(Pin 1)  
-
VIDEO  
INPUT  
(Pin 2)  
-
+
V SLICE  
HORIZONTAL  
+
-
+
ODD / EVEN  
OUTPUT  
(Pin 7)  
D
G
Q
Q
V CLAMP  
D
Q
Q
WINDOWING  
CIRCUIT  
CLK  
85µ  
11µ  
NOSYNC  
B PEN  
V
CC  
VERTICAL SYNC  
OUTPUT  
(Pin 8)  
D
Q
Q
VOLTAGE  
REGULATOR  
VERTICAL  
DETECTOR  
(PIN 3)  
CLK  
BACK PORCH  
OUTPUT  
1.2V  
(Pin 5)  
R_SET  
(Pin 6)  
BACK PORCH  
DETECTOR  
TIMING  
CURRENTS  
Fig. 18 GS4881 Block Diagram  
520 - 23 - 03  
9
COMPOSITE  
SYNC OUTPUT  
(Pin 1)  
C SYNC  
-
VIDEO  
INPUT  
(Pin 2)  
-
+
V 1  
V 2  
+
10k  
-
+
HORIZONTAL  
OUTPUT  
WINDOWING  
CIRCUIT  
(Pin 7)  
85µ  
11µ  
NOSYNC  
B PEN  
V
CC  
VERTICAL SYNC  
OUTPUT  
D
(Pin 8)  
Q
Q
VOLTAGE  
REGULATOR  
VERTICAL  
DETECTOR  
(PIN 3)  
CLK  
BACK PORCH  
OUTPUT  
1.2V  
(Pin 5)  
R_SET  
(Pin 6)  
BACK PORCH  
DETECTOR  
TIMING  
CURRENTS  
Fig. 19 GS4981 Block Diagram  
525  
1
2
3
4
5
6
7
8
COMPOSITE  
VIDEO INPUT  
COMPOSITE SYNC OUTPUT  
GS1881, GS4881, GS4981  
BACK PORCH OUTPUT  
GS4881, GS4981  
BACK PORCH OUTPUT  
GS1881  
HORIZONTAL OUTPUT  
GS4981  
VERTICAL SYNC OUTPUT  
GS1881, GS4881, GS4981  
ODD/EVEN OUTPUT  
GS1881, GS4881  
600ns  
2.5µs  
COMPOSITE  
VIDEO INPUT  
BACK PORCH  
OUTPUT  
2.5µs  
500ns  
Fig. 20 GS1881, GS4881, GS4981 Video Sync Separator Timing Diagram  
520 - 23 - 03  
10  
APPLICATION NOTES  
(1) Choosing the Appropriate Input Coupling Capacitor to  
Optimize Slicing Level and Hum Rejection  
137  
127  
117  
107  
97  
Thevideodesignercanadjusttheslicinglevelbychoosingthe  
valueoftheinputcouplingcapacitor.Therelationshipbetween  
slicing level and input coupling capacitor is described by the  
following equation.  
IDIS  
VSLICE  
=
T = VDROOP  
87  
CC  
77  
0.01 0.02 0.03 0.04 0.05 0.06 0.07  
0.08 0.09 0.10  
where:  
IDIS = clamp discharge current = 11 µA  
T = TLINE - TSYNC = (63.5 µs - 4.7 µs)  
CC = input coupling capacitor  
INPUT COUPLING CAPACITOR (µF)  
Fig. 21 Slicing Level vs Input Coupling Capacitor  
Figure 21 is a graphical representation of this equation and  
photographs 1 and 2 show the input video waveforms  
for 0.1 µF and 0.01 µF input capacitors respectively. The  
advantage in choosing a smaller input coupling capacitor, is  
increased hum rejection as the following analyses illustrates.  
CH1  
CH2  
CH2  
CH1  
8
VIDEO  
2
4
0.1µF  
75  
6
680k  
0.1µ  
Test Circuit 1  
Photograph 1  
CH1  
CH2  
CH2  
CH1  
8
6
VIDEO  
2
0.01µF  
75  
4
680k  
0.1µ  
Test Circuit 2  
Photograph 2  
520 - 23 - 03  
11  
verifying that there is enough clamping current  
The interfering hum component is defined by:  
HUM(t) = VPcos(2πƒHUMt)  
Vt = 29.4 mV + 29.4 mV = 58.8 mV  
v
58.8 mV  
... i = 0.022 µ  
= 275 µA  
where: VP = Peak voltage of AC hum  
(
)
4.7 µ  
ƒHUM = Frequency of hum (50 Hz or 60 Hz)  
which is less than 650 µA.  
The maximum rate of change of this hum signal occurs at the  
zero crossing points and is:  
(2) FIltering  
dvHUM  
= ± VP2πƒHUM  
Inordertokeeptheinputtooutputdelaysmallandtemperature  
stable, no chrominance filtering is done within the device.  
External filtering may be necessary if the input signal contains  
large chrominance components (less than 77 mV from sync  
tip) or has significant amounts of high frequency noise. This  
filter can be a simple low pass RC network constructed by a  
resistance (RS) in series with the source and a capacitor (Cƒ)  
to ground. A single pole low pass filter having a corner  
frequency of approximately 500 kHz will provide ample  
bandwidth for passing sync pulses with almost 18 dB  
attenuation at 3.58 MHz. Care should be taken in choosing  
the value of the series resistor in the filter since the source  
resistanceseenbythesyncseparatoraffectsitsperformance.  
dt  
π
2
3π  
2
t =  
,
Sincethehorizontalscanperiodismuchfasterthantheperiod  
of the interference ( 63.5 µs << 1/ƒHUM)a good approximation  
is to assume that the maximum line to line voltage change  
resulting from the interfering hum is:  
VHUM = ± VP2πƒHUM TLINE  
where: TLINE = 63.5 µs  
Thetotallinetolinevoltagechange(VT)canthenbecalculated  
by adding the hum component (VHUM ) and the droop  
component (VDROOP). This calculation results in two cases:  
As the source resistance rises, the video input sync tip starts  
to be clipped due to the clamping current during the sync.  
This clamping current is relatively large due to the  
non-symmetric duty cycle of video. To a good approximation  
the amount of sync clamp current can be calculated as  
follows:  
V  
T
V  
T
Case A  
Case B  
( ICLAMP ) (TSYNC) = (IDIS) (TLINE - TSYNC  
)
AVG  
VT = VHUM + VDROOP  
ICLAMP (4.7 µs) = (11 µA) (63. 5 µs - 4.7 µs)  
AVG  
... ICLAMP  
To correct for VT in case A, the input stage must be able to  
charge the input capacitor VT volts in 4.7 µs. This is not a  
constraint as the typical clamping current of 650 µA can  
accomplish this for practical values of coupling capacitor.  
= 137.6 µA  
AVG  
This clamp current flows in the source resistance causing a  
voltage drop equal to :  
The only way to compensate for VT in case B is to make  
VDROOP >VHUM. VDROOP is increased by decreasing the input  
coupling capacitor value. Therefore the video designer can  
VCLIP = ( ICLAMP ) (RS)  
AVG  
= (137.6 µ) (RS)  
increasehumrejectionbydecreasingthevalueofthiscapacitor.  
The following is a numerical example:  
ICLAMP  
choosing C = 0.022 µF  
VIDEO  
INPUT  
c
RS  
11  
8
6
... VDROOP  
=
(63.5 µ - 4.7 µ) = 29.4 mV  
2
-
+
0.022  
V
CC  
CLIP  
the maximum amount of 60 Hz hum that could be rejected  
would be when:  
4
75  
C
ƒ
680k  
0.1µ  
VDROOP  
=
VHUM = VP 2πƒHUM TLINE  
Fig. 22 Simple Chrominance Filtering  
VDROOP 29.4mV  
... VP =  
=
=1.23vPEAK HUM  
2πƒHUMTLINE 2π(60) (63.5 µ)  
520 - 23 - 03  
12  
Photograph 3 shows the amount of sync clipping for a 560 Ω  
source resistor. A graph of VCLIP versus RS is shown in  
Figure 23, and Figure 24 shows the corresponding capacitor  
value for a particular series resistor to provide a corner  
frequency of 500 kHz.  
Anotherwaytominimizetheamountofattenuationistocontrol  
the source resistance seen by the sync separator by using a  
PNP emitter follower (Figure 25). A PNP emitter follower works  
well to drive the sync separator, and does not require much  
DC current because the transistor provides the current when  
it is needed during sync. Figure 26 is a typical application  
circuit that minimizes sync tip clipping.  
In applications where signal levels are small the amount of  
attenuationshouldbeminimized. ItfollowsfromFigure23and  
Figure 24 that in order to minimize attenuation a small series  
resistor and a larger capacitor to ground should be chosen.  
This however, increases the capacitive loading of the signal  
source.  
CH1  
CH2  
CH1  
CH2  
VIDEO  
8
6
2
560Ω  
75Ω  
0.1µF  
4
680k  
0.1µ  
Test Circuit 3  
Photograph 3  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
10  
9
8
7
6
5
4
3
2
1
0
0
100  
200  
300  
400  
500  
600  
700  
0
100  
200  
300  
400  
500  
600  
700  
SERIES RESISTOR ()  
SERIES RESISTOR ()  
Fig. 24 Cƒ vs Series Resistor  
Fig. 23 V  
vs Series Resistor  
CLIP  
VCC  
VCC  
5.6k  
5.6k  
VIDEO  
INPUT  
8
8
VIDEO  
INPUT  
2
2
5.6k  
CC  
CC  
FILTER  
6
4
6
4
680k  
0.1µ  
75  
56p  
75  
680k  
0.1µ  
-5V  
-5V  
Fig. 25 PNP Emitter Follower Buffer  
Fig. 26 Typical NTSC Application Circuit  
520 - 23 - 03  
13  
(3) Deriving Odd/Even Using the GS4981  
Odd/even field information can be derived using the vertical  
and horizontal outputs from the GS4981 along with an external  
positive edge D flip/flop. The horizontal output is used  
as the D input and the vertical output as the clock, as  
shown in Figure 27.  
Atthestartofanoddfieldtheverticaloutputendsinthemiddle  
of the horizontal line and a high will be latched. At the start of  
an even field, the vertical output ends near the beginning of  
the horizontal line and since the horizontal output is low, a low  
will be latched. This timing sequence is shown in Figure 28.  
GS4981  
COMPOSITE  
5 - 12V  
D FLIP/FLOP  
V
1
CC  
SYNC OUTPUT  
8
7
0.1µF  
HORIZONTAL  
COMPOSITE  
VIDEO INPUT  
ODD/EVEN  
OUTPUT  
2
D
Q
Q
680k  
VERTICAL  
SYNC OUTPUT  
3
4
CLK  
R
6
5
SET  
0.1µF  
BACK PORCH  
OUTPUT  
Fig. 27 Derivation of Odd/Even with GS4981  
START OF ODD FIELD  
525  
1
2
3
4
5
6
7
8
COMPOSITE  
VIDEO INPUT  
HORIZONTAL OUTPUT  
GS4981  
VERTICAL SYNC OUTPUT  
GS4981  
ODD/EVEN OUTPUT  
START OF EVEN FIELD  
263  
264  
265  
266  
267  
268  
269  
270  
COMPOSITE  
VIDEO INPUT  
HORIZONTAL  
GS4981  
VERTICAL SYNC OUTPUT  
GS4981  
ODD/EVEN OUTPUT  
Fig. 28 Timing Diagram  
DOCUMENT  
IDENTIFICATION  
PRODUCT PROPOSAL  
This data has been compiled for market investigation purposes  
only, and does not constitute an offer for sale.  
ADVANCE INFORMATION NOTE  
This product is in development phase and specifications are  
subject to change without notice. Gennum reserves the right to  
remove the product at any time. Listing the product does not  
constitute an offer for sale.  
PRELIMINARY  
The product is in a preproduction phase and specifications are  
subject to change without notice.  
REVISION NOTES  
The only change from 520-23-02 to 520-23-03 is that the document has been  
upgraded to a full DATA SHEET. It is no longer Preliminary.  
DATA SHEET  
The product is in production. Gennum reserves the right to  
make changes at any time to improve reliability, function or  
design, in order to provide the best product possible.  
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.  
© Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada.  
520 - 23 - 03  
14  

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