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产品型号GTLP16612MEAX的概述

芯片GTLP16612MEAX的概述 GTLP16612MEAX是一款先进的逻辑芯片，广泛应用于通信、电信以及高速数据传输等领域。其设计目的在于支持高频率和快速数据处理，同时降低功耗与电磁干扰。这种芯片的出现，标志着逻辑电路技术的升级与发展，使得设计者能够在日益复杂的电路中实现高效能和高可靠性。 GTLP16612MEAX采用Low Voltage TTL（LVTTL）输入，并兼容GTL（Gunning Transceiver Logic）信号，这使得其能够在不同的逻辑电平下工作，增加了其在多种系统中的适应性。此外，该芯片具有多达16个触发器的并行处理能力，能够在单个芯片上处理大量数据流。芯片GTLP16612MEAX的详细参数 GTLP16612MEAX具备众多显著的参数特点，包括但不限于以下几个方面： - 电源电压（VCC）： 3.3V±0.15V，适应现代数字电路的低电压需求。...

产品型号GTLP16612MEAX的Datasheet PDF文件预览

March 1995

Revised March 2001

GTLP16612

18-Bit TTL/GTLP Universal Bus Transceiver

General Description

Features

The GTLP16612 is an 18-bit universal bus transceiver

which provides TTL to GTLP signal level translation. The

device is designed to provide a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLP’s reduced output

swing (<1V), reduced input threshold levels and output

edge rate control which minimizes signal settling times.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

■ Bidirectional interface between GTLP and TTL logic

levels

■ Designed with an edge rate control circuit to reduce

output noise on GTLP port

■ V_REFpin provides external supply reference voltage for

receiver threshold adjustability

■ Special PVT compensation circuitry to provide

consistent performance over variations of process,

supply voltage and temperature

■ TTL compatible Driver and Control inputs

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different driver

output levels and receiver threshold. GTLP output low volt-

age is typically less than 0.5V, the output high is 1.5V and

the receiver threshold is 1.0V.

■ Designed using Fairchild advanced CMOS technology

■ Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live

insertion

■ 5V tolerant inputs and outputs on LVTTL port

■ Open drain on GTLP to support wired-or connection

■ Flow-through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port outputs source/sink −32 mA/+32 mA

Ordering Code:

Order Number

GTLP16612MEA

GTLP16612MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

DS012390

www.fairchildsemi.com

Pin Descriptions

Connection Diagram

Names

Description

OEAB

OEBA

CEAB

CEBA

LEAB

LEBA

CLKAB

CLKBA

V_REF

A-to-B Output Enable (Active LOW)

B-to-A Output Enable (Active LOW)

A-to-B Clock Enable (Active LOW)

B-to-A Clock Enable (Active LOW)

A-to-B Latch Enable (Transparent HIGH)

B-to-A Latch Enable (Transparent HIGH)

A-to-B Clock Pulse

B-to-A Clock Pulse

GTLP Input Reference Voltage

A1–A18 A-to-B TTL Data Inputs or

B-to-A 3-STATE Outputs

B1–B18 B-to-A GTLP Data Inputs or

A-to-B Open Drain Outputs

Functional Description

The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins

operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches

and D-type flip-flops to allow data flow in transparent, latched and clock mode.

The functional operation is described in the truth table below.

Truth Table

(Note 1)

Inputs

LEAB

Output

Mode

CEAB

OEAB

CLKAB

Latched

storage

B₀(Note 2)

B₀(Note 3)

of A data

Transparent

↑

Clocked storage

of A data

↑

B₀(Note 3)

Clock inhibit

Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.

Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

Note 3: Output level before the indicated steady-state input conditions were established.

www.fairchildsemi.com

Logic Diagram

www.fairchildsemi.com

Absolute Maximum Ratings(Note 4)

Recommended Operating

Conditions ^{(Note 6)}

Supply Voltage (V_CC, V_CCQ

DC Input Voltage (V_I)

DC Output Voltage (V_O)

Outputs 3-STATE

)

−0.5V to +7.0V

Supply Voltage V_CC

V_CC

3.15V to 3.45V

4.75V to 5.25V

1.35V to 1.65V

−0.5V to +7.0V

V_CCQ

Outputs Active (Note 5)

−0.5V to V_CC+ 0.5V

Bus Termination Voltage (V_TT

)

DC Output Sink Current into

A Port I_OL

Input Voltage (V_I)

64 mA

−64 mA

80 mA

on A Port and Control Pins

0.0V to 5.5V

DC Output Source Current from

A Port I_OH

HIGH Level Output Current (I_OH

A Port

)

−32 mA

DC Output Sink Current

into B Port in the LOW State, I_OL

LOW Level Output Current (I_OL

)

A Port

+32 mA

+34 mA

DC Input Diode Current (I_IK

)

B Port

V_I< 0V

−50 mA

Operating Temperature (T_A)

−40°C to +85°C

Note 4: The Absolute Maximum Ratings are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristic tables are not guaranteed at the absolute maximum rating.

The “Recommended Operating Conditions” table will define the conditions

for actual device operation.

DC Output Diode Current (I_OK

)

V_O< 0V

−50 mA

+50 mA

V_O> V_CC

Storage Temperature (T_STG

ESD Performance

)

−65°C to +150°C

>2000V

Note 5: I_OAbsolute Maximum Rating must be observed.

Note 6: Unused inputs must be held HIGH or LOW.

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

= 1.0V (Unless Otherwise Noted).

REF

Min

Typ

Max

Symbol

Test Conditions

Units

(Note 7)

V_IH

V_IL

B Port

Others

B Port

Others

_REF+0.1

V_TT

2.0

0.0

_REF−0.1

0.8

V_REF

V_IK

1.0

_CC= 3.15V,

_CCQ= 4.75V

I_I= −18 mA

−1.2

V_OH

A Port

V_CC, V_CCQ= Min to Max (Note 8)

_OH= −100 µA

_OH= −8 mA

_OH= −32 mA

_OL= 100 µA

_OL= 32 mA

_CC− 0.2

V_CC= 3.15V

2.4

V_CCQ= 4.75V

2.0

V_OL

V_CC, V_CCQ= Min to Max (Note 8)

0.2

0.5

_CC= 3.15V

_CCQ= 4.75V

B Port

_CC= 3.15V V_CCQ= 4.75V

_OL= 34 mA

0.65

±10

I_I

Control Pins

A Port

V_CC, V_CCQ= 0 or Max

V_I= 5.5V or 0V

V_I= 5.5V

µA

V_CC= 3.45V

V_CCQ= 5.25V

V_I= V_CC

µA

V_I= 0

−30

B Port

_CC= 3.45V

V_I= V_CCQ

V_I= 0

µA

_CCQ= 5.25V

_CC= V_CCQ= 0

_CC= 3.15V,

_CCQ= 4.75V

_CC= 3.45V,

_CCQ= 5.25V

_CC= 3.45V,

_CCQ= 5.25V

−5

I_OFF

A Port

V_Ior V_O= 0 to 4.5V

V_I= 0.8V

100

I_I(hold)

V_I= 2.0V

−20

I_OZH

A Port

B Port

A Port

B Port

_O= 3.45V

_O= 1.5V

_O= 0

µA

I_OZL

−20

−10

_O= 0.65V

www.fairchildsemi.com

DC Electrical Characteristics (Continued)

Min

Typ

(Note 7)

Max

Symbol

Test Conditions

Outputs HIGH

Units

I_CCQ

A or B

Ports

_CC= 3.45V,

(V_CCQ

)

V_CCQ= 5.25V,

Outputs LOW

_O= 0,

V_I= V_CCQor GND

Outputs Disabled

Outputs HIGH

Outputs LOW

I_CC

A or B

Ports

V_CC= 3.45V,

(V_CC

)

V_CCQ= 5.25V,

_O= 0,

V_I= V_CCQor GND

Outputs Disabled

One Input at 2.7V

∆I_CC

A Port and

V_CC= 3.45V,

(Note 9)

Control Pins

_CCQ= 5.25V,

A or Control Inputs at

V_CCor GND

C_IN

Control Pins

A Port

V_I= V_CCQor 0

C_I/O

B Port

Note 7: All typicaI values are at V_CC= 3.3V, V_CCQ= 5.0V, and T_A= 25°C.

Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.

Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than V_CCor GND.

AC Operating Requirements

Over recommended ranges of supply voltage and operating free-air temperature, V

= 1.0V (unless otherwise noted).

REF

Symbol

Min

150

3.0

3.2

0.5

3.1

1.3

3.7

Max

Unit

f_MAX

t_W

Maximum Clock Frequency

Pulse Duration

MHz

LEAB or LEBA HIGH

CLKAB or CLKBA HIGH or LOW

A before CLKAB↑

t_S

Setup Time

B before CLKBA↑

A before LEAB↓

B before LEBA↓

CEAB before CLKAB↑

0.4

CEBA before CLKBA↑

A after CLKAB↑

B after CLKBA↑

A after LEAB↓

1.0

1.5

0.0

0.5

0.0

t_H

Hold Time

B after LEBA↓

CEAB after CLKAB↑

CEBA after CLKBA↑

1.5

1.7

www.fairchildsemi.com

AC Electrical Characteristics

Over recommended range of supply voltage and operating free-air temperature, V

= 1.0V (unless otherwise noted).

REF

_L= 30 pF for B Port and C_L= 50 pF for A Port.

Symbol

From

(Input)

(Output)

Min

Typ

(Note 10)

4.3

Max

Unit

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

1.0

1.8

1.5

1.8

1.5

6.5

8.2

6.7

8.6

6.7

8.7

5.0

LEAB

4.5

5.3

CLKAB

4.6

5.4

t_PLH

t_PHL

t_RISE

t_FALL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

OEAB

1.6

1.3

4.4

6.1

2.6

5.6

5.0

4.2

3.3

4.4

3.5

6.2

9.8

Transition time, B outputs (20% to 80%)

2.0

1.4

2.1

1.9

2.3

2.2

8.2

7.2

6.3

5.0

6.8

5.2

LEBA

CLKBA

t_PZH, t_PZL

t_PHZ, t_PLZ

OEBA

1.5

1.9

5.0

3.9

6.2

7.9

Note 10: All typical values are at V_CC= 3.3V, V_CCQ= 5.0V, and T_A= 25°C.

www.fairchildsemi.com

Test Circuits and Timing Waveforms

Test Circuit for A Outputs

Test Circuit for B Outputs

_Lincludes probes and jig capacitance.

C_Lincludes probes and jig capacitance.

For B Port outputs, C_L= 30 pF is used for

worst case edge rate.

Voltage Waveforms Pulse Duration

(Vm = 1.5V for A Port and 1.0V for B Port)

Voltage Waveforms Propagation Delay Times

(A Port to B Port)

Voltage Waveforms Propagation Delay Times

(B Port to A Port)

Voltage Waveforms Setup and Hold Times

(Vm = 1.5V for A Port and 1.0V for B Port)

All input pulses have the following characteristics: frequency = 10 MHz, t_r= t_f= 2 ns, Z_O= 50Ω. The outputs are measured

one at a time with one transition per measurement.

Voltage Waveforms Enable and Disable Times (A Port)

Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with

internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics:

frequency = 10 MHz, t_r= t_f= 2 ns, Z_O= 50Ω. The outputs are measured one at a time with one transition per measurement.

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Package Number MS56A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

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GTLP16612MEAX产品参数

型号:	GTLP16612MEAX
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SSOP
包装说明：	SSOP,
针数：	56
Reach Compliance Code：	unknown
风险等级：	5.7
其他特性：	TRANSLATES BETWEEN GTL SIGNAL LEVELS AND LVTTL OR 5V TTL SIGNAL LEVELS
系列：	GTLP
JESD-30 代码：	R-PDSO-G56
JESD-609代码：	e3
长度：	18.415 mm
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER
湿度敏感等级：	1
位数：	18
功能数量：	1
端口数量：	2
端子数量：	56
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	OPEN-DRAIN/3-STATE
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	8.7 ns
认证状态：	COMMERCIAL
座面最大高度：	2.74 mm
最大供电电压 (Vsup)：	3.45 V
最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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