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512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O

Specification of

512M (16Mx32bit) Mobile SDRAM

Memory Cell Array

- Organized as 4banks of 4,194,304 x32

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.5 / Jan. 2009

1

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Document Title

4Bank x 4M x 32bits Synchronous DRAM

Revision History

Revision No.

History

Draft Date

Remark

0.1

Initial Draft

Sep. 2007

Preliminary

Correction

0.2

- PKG Height: 1.0mm (without Ball Height)

Feb. 2008

Preliminary

-> 1.0mm (with Ball Height)

0.3

1.0

Update: IDD values

Final Version

Mar. 2008

Apr. 2008

-. Corrected the description of BURST TERMINATE

-. Corrected the CKE state on every command

-. Deleted the extended temperature products

1.1

May 2008

1.2

1.3

1.4

1.5

Modify : tRAS (166MHz/133Mhz: 42ns/45ns)

Modify : tCK (CL=2, 166MHz [12ns -> 9.6ns])

Insert the reduced page Information

Jun. 2008

Jul. 2008

Jan. 2009

Change the ball height (page 54)

Rev 1.5 / Jan. 2009

2

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

DESCRIPTION

The Hynix H55S5122DFR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs.

The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the

main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

4,194,304x32.

Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch

each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the

input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/

Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8

locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-

tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed

operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column

address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while

accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-

access operation.

Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a

burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any

cycle(This pipelined design is not restricted by a 2N rule).

The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,

half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees ^oC.

The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to

reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically

adjust refresh rate according to temperature without external EMRS command.

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power

reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut

off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).

Rev 1.5 / Jan. 2009

3

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

INFORMATION for Hynix KNOWN GOOD DIE

With the advent of Multi-Chip package (MCPs), Package on Package (PoP) and system in a package (SiP) applications,

customer demand for Known Good Die (KGD) has increased.

Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solu-

tions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies

such as systems-in-a-package (SIPs) and multi-chip packages (MCPs) to reduce the board area required, making them

ideal for hand-held PCs, and many other portable digital applications.

Hynix Mobile DRAM will be able to continue its constant effort of enabling the Advanced package products of all appli-

cation customers.

- Please Contact Hynix Office for Hynix KGD product availability and informations.

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

FEATURES

●

Standard SDRAM Protocol

Clock Synchronization Operation

- All the commands registered on positive edge of basic input clock (CLK)

MULTIBANK OPERATION - Internal 4bank operation

- During burst Read or Write operation, burst Read or Write for a different bank is performed.

- During burst Read or Write operation, a different bank is activated and burst Read or Write

for that bank is performed

●

- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed

Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V

LVCMOS compatible I/O Interface

●

Low Voltage interface to reduce I/O power

Programmable burst length: 1, 2, 4, 8 or full page

Programmable Burst Type: sequential or interleaved

Programmable CAS latency of 3 or 2

Programmable Drive Strength

Low Power Features

- Programmable PASR(Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Programmable DS (Drive Strength)

- Deep Power Down Mode

●

Operation Temperature

- Mobile Temp.: -30^oC ~ 85^oC

Package Type: 90ball FBGA, 0.8mm pitch, 8 x 13 [mm²], t=1.0mm max, Lead & Halogen Free

512M SDRAM ORDERING INFORMATION

Page

Size

Part Number

Clock Frequency

Organization

Interface

Package

H55S5122DFR-60M

H55S5122DFR-75M

H55S5122DFR-A3M

H55S5132DFR-60M

H55S5132DFR-75M

H55S5132DFR-A3M

166MHz

133MHz

105MHz

166MHz

133MHz

105MHz

2KBytes

(Normal)

90 Ball FBGA

Lead & Halogen

Free

4banks x 4Mb x 32

LVCMOS

1KBytes

(Reduced)

Rev 1.5 / Jan. 2009

5

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

BALL DESCRIPTION

(A13 is used as 1KBytes reduced page)

1

2

3

4

6

7

8

9

DQ

26

DQ

24

DQ

23

DQ

21

A

VSS

VDD

DQ

28

DQ

19

VDDQ

VSSQ

B

VDDQ

VSSQ

DQ

27

DQ

25

DQ

22

DQ

20

VSSQ

VDDQ

C

DQ

29

DQ

30

DQ

17

DQ

18

D

VSSQ

DQ

31

DQ

16

VDDQ

NC

A3

A6

E

NC

A2

VSSQ

VDD

A1

DQM

3

DQM

2

F

VSS

A4

A10

A0

G

A5

BA

1

A7

A8

A12

A9

A13

A11

H

TOP

VIEW

BA

0

J

CLK

CKE

/CS

/RAS

DQM

0

DQM

1

K

NC

/CAS

VDD

/WE

DQ

8

DQ

7

L

VDDQ

VSS

VSSQ

VDDQ

DQ

9

DQ

6

DQ

5

DQ

10

VSSQ

M

DQ

12

DQ

14

DQ

1

DQ

3

VSSQ

VDDQ

N

DQ

11

DQ

4

P

VDDQ

VSSQ

VSS

VDDQ

VDD

VSSQ

DQ

15

DQ

0

DQ

13

R

DQ2

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

BALL DESCRIPTION

SYMBOL

TYPE

DESCRIPTION

Clock: The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CLK

INPUT

Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will

be one of the states among power down, suspend or self refresh

CKE

CS

INPUT

Chip Select: Enables or disables all inputs except CLK, CKE, DQM0~DQM3

Bank Address: Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

For 1KBytes Page Size, Row Address: RA0 ~ RA13, Column Address: CA0 ~ CA7

For 2KBytes Page Size, Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8

Auto-precharge flag: A10

A0 ~ A13

INPUT

Command Inputs: RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM0 ~ DQM3

INPUT

Data Mask: Controls output buffers in read mode and masks input data in write

mode

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

NC

I/O

SUPPLY

-

Data Input/Output: Multiplexed data input/output pin

Power supply for internal circuits

Power supply for output buffers

No connection

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

ABSOLUTE MAXIMUM RATING

Parameter

Symbol

Rating

Unit

^oC

Ambient Temperature

TA

-30 ~ 85

^oC

V

Storage Temperature

TSTG

VIN, VOUT

VDD

-55 ~ 125

-1.0 ~ 2.6

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Short Circuit Output Current

Power Dissipation

V

VDDQ

IOS

V

mA

W

PD

1

Soldering Temperature ^.Time

260 ^.20

ꢀꢀ^oC ^.Sec

TSOLDER

DC OPERATING CONDITION (TA= -30 to 85^oC)

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

VDD

Min

1.7

Typ

1.8

-

Max

Unit

Note

1

1.95

V

VDDQ

VIH

1.7

1, 2

0.8*VDDQ

-0.3

VDDQ+0.3

0.3

VIL

-

Note:

1. All Voltages are referenced to VSS = 0V

2. VDDQ must not exceed the level of VDD

AC OPERATING TEST CONDITION (TA= -30 to 85 ^oC, VDD = 1.8V, VSS = 0V)

Parameter

Symbol

VIH / VIL

Vtrip

Value

0.9*VDDQ/0.2

0.5*VDDQ

1

Unit

Note

AC Input High/Low Level Voltage

V

Input Timing Measurement Reference Level Voltage

Input Rise/Fall Time

tR / tF

Voutref

CL

ns

V

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

0.5*VDDQ

30

pF

Rev 1.5 / Jan. 2009

8

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CAPACITANCE (TA= 25 ^oC, f=1MHz)

6/H

Parameter

Symbol

Unit

Min

Max

CLK

CI1

CI2

2

4.0

pF

A0~A13, BA0, BA1, CKE, CS, RAS,

Input capacitance

2

4.0

4.5

CAS, WE, DQM0~3

DQ0 ~ DQ31

Data input/output capacitance

CI/O

DC CHARACTERRISTICS I (TA= -30 to 85^oC)

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

ILO

-1

1

uA

V

1

2

3

4

-1

VOH

VOL

VDDQ-0.2

-

0.2

V

Note:

1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.

2. DOUT is disabled. VOUT= 0 to 1.95V.

3. IOUT = - 0.1mA

4. IOUT = + 0.1mA

Rev 1.5 / Jan. 2009

9

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

DC CHARACTERISTICS II (TA= -30 to 85^oC)

Speed

Parameter

Symbol

Test Condition

Unit Note

166MHz 133MHz 105MHz

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA

Operating Current

IDD1

60

45

mA

1

Precharge Standby

Current

in Power Down Mode

IDD2P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK =ꢀ∞

0.3

mA

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= 15ns

Input signals are changed one time

during

2clks.

Precharge Standby

Current

in Non Power Down

Mode

IDD2N

5

mA

All other pins ≥ VDD-0.2V or ≤ꢀ0.2V

CKE ≥ VIH(min), tCK =ꢀ∞

Input signals are stable.

IDD2NS

1

IDD3P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK =ꢀ∞

5

3

Active Standby Current

in Power Down Mode

IDD3PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= 15ns

Input signals are changed one time

during

2clks.

IDD3N

10

Active Standby Current

in Non Power Down

Mode

mA

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

IDD4

5

Burst Mode Operating

Current

tCK ≥ tCK(min), IOL=0mA

All banks active

70

60

1

Auto Refresh Current IDD5

tRFC ≥ tRFC(min)

CKE ≤ 0.2V

100

mA

Self Refresh Current

IDD6

See Next Page

2

3

Standby Current in

Deep Power Down

Mode

See the pages for the Deep Power

Down operation.

IDD7

10

uA

Notes:

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. See the tables of next page for more specific IDD6 current values.

3. Please contact Hynix office for more information and ability for DPD operation.

Deep Power Down operation is a hynix optional function.

Rev 1.5 / Jan. 2009

10

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

DC CHARACTERISTICS III - Low Power (IDD6)

Memory Array

2 Banks

220

Temp.

(^oC)

Unit

4 Banks

250

1 Bank

200

45

85

uA

500

400

350

1. VDD / VDDQ = 1.8V

o

2. Related numerical values in this 45 C are examples for reference sample value only.

3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self refresh will automatically

adjust the interval of self-refresh operation according to ambient temperature variations.

Rev 1.5 / Jan. 2009

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

166MHz

133MHz

105MHz

Parameter

CAS Latency=3

Symbol

Unit Note

Min Max Min Max Min Max

System Clock

Cycle Time

tCK3

tCK2

6.0

9.6

1000

7.5

12

1000

9.5

15

1000

ns

CAS Latency=2

Clock High Pulse Width

Clock Low Pulse Width

tCHW

tCLW

tAC3

tAC2

tOH

2.0

-

2.5

-

3.0

-

ns

1

-

CAS Latency=3

CAS Latency=2

5.4

6.0

7.0

2, 3

3

Access Time From Clock

-

6.0

-

8.0

-

10

Data-out Hold Time

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

CKE Setup Time

2.6

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

-

2.6

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

-

2.6

3.0

1.5

3.0

1.5

3.0

1.5

3.0

1.5

1.0

-

tDS

1

tDH

-

1

tAS

-

1

tAH

-

1

tCKS

tCKH

tCS

-

1

CKE Hold Time

-

1

Command Setup Time

Command Hold Time

-

1

tCH

-

1

CLK to Data Output in Low-Z Time

tOLZ

tOHZ3

-

CLK to Data Output in

High-Z Time

CAS Latency=3

CAS Latency=2

5.4

6.0

7.0

tOHZ2

6.0

8.0

10

ns

Notes:

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF> 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR> 1ns, then (tR/2-0.5)ns

should be added to the parameter.

3. Output Load: 30pF+No termination

●

AC high level input voltage / low level input voltage: 1.6 / 0.2V

Input timing measurement reference level: 0.9V

Transition time (input rise and fall time): 0.5ns

Output timing measurement reference level: 0.9V

Output load: CL = 30pF

tCK

Z = 50Ω

tCH

tCL

Output

1.6V

0.9V

0.2V

CLK

30pF

tSETUP

tHOLD

tAC

1.6V

0.9V

0.2V

Input

Output Load

tOH

Output

Rev 1.5 / Jan. 2009

12

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

166MHz

133MHz

105MHz

Parameter

Symbol

Unit Note

Min Max Min Max Min Max

RAS Cycle Time

RAS to CAS Delay

RAS Active Time

tRC

60

18

-

72.5

22.5

-

90

-

ns

tRCD

tRAS

tRP

28.5

42 100K 45 100K 60 100K ns

RAS Precharge Time

18

12

72

1

-

22.5

15

72

1

-

28.5

19

72

1

-

ns

RAS to RAS Bank Active Delay

AUTO REFRESH Period

tRRD

tRFC

tCCD

tWTL

tDPL

ns

CAS to CAS Delay

CLK

Write Command to Data-In Delay

Data-in to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

0

2

tDAL

tDQZ

tDQM

tMRD

tPROZ3

tPROZ2

tDPL+tRP

2

0

2

3

2

-

2

0

2

3

2

-

2

0

2

3

2

-

CLK

DQM to Data-In Mask

MRS to New Command

CAS Latency=3

Precharge to Data Output

High-Z

CAS Latency=2

1CLK

+

1CLK

+

1CLK

+

Power Down Exit Time

tDPE

-

CLK

tCKS

Self Refresh Exit Time

Refresh Time

tXSR

tREF

120

-

120

-

120

-

ns

64

ms

Rev 1.5 / Jan. 2009

13

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 32 I/O Mobile Synchronous DRAM

PASR

Extended

Mode

Register

Self refresh

logic & timer

Internal Row

Counter

4Mx32 BANK3

4Mx32 BANK2

4Mx32 BANK1

4Mx32 BANK0

CLK

CKE

CS

Row

Pre

Decoder

Row Active

DQ0

RAS

CAS

WE

Refresh

Memory

Cell

Array

32

Column Active

Column

Pre

Decoder

DQM0

~ 3

DQ31

Column decoders

Column Add

Counter

Bank Select

Address

Register

A0

A1

Burst

Counter

CAS

Latency

A13

BA1

BA0

Mode Register

Data Out Control

(A13 is used as 1KBytes reduced page)

Rev 1.5 / Jan. 2009

14

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

(A13 is used as 1KBytes reduced page)

BA1 BA0 A13 A12 A11 A10

A9

OP Code

A8

0

A7

0

A6

A5

A4

A3

BT

A2

A1

A0

0

CAS Latency

Burst Length

OP Code

Burst Type

A9

0

Write Mode

A3

0

Burst Type

Sequential

Interleave

Burst Read and Burst Write

Burst Read and Single Write

1

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

Reserved

2

Burst Length

A2

A1

A0

A3 = 0

A3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

0

1

0

1

3

4

1

0

Reserved

8

1

0

1

Reserved

Full page

Reserved

1

0

1

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

BASIC FUNCTIONAL DESCRIPTION (Continued)

Extended Mode Register

(A13 is used as 1KBytes reduced page)

BA1

1

BA0 A13 A12

A11

0

A10

0

A9

0

A8

0

A7

A6

DS

A5

A4

0

A3

0

A2

A1

A0

0

PASR

DS (Driver Strength)

A7

0

A6

0

A5

0

Driver Strength

Full

0

1

1/2 Strength

1/4 Strength

Reserved

0

1

0

1

0

3/4 Strength

PASR (Partial Array Self Refresh)

A2

0

A1

0

A0 Self Refresh Coverage

0

1

0

1

0

1

0

1

All Banks

Half of Total Bank (BA1=0 or Bank 0,1)

0

1

Quarter of Total Bank (BA1=BA0=0 or Bank 0)

0

1

Reserved

1

0

Reserved

1

0

Half of Bank 0(Bank 0 and Row Address MSB=0)

1

Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0)

Reserved

1

Rev 1.5 / Jan. 2009

16

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

COMMAND TRUTH TABLE

A10

/AP

Function

CKEn-1

CKEn

CS

RAS CAS WE DQM ADDR

BA Note

H

X

L

X

Op Code

2

Mode Register Set

Extended Mode Register

Set

Op Code

H

X

H

L

H

L

H

X

L

H

X

H

L

H

X

H

L

X

No Operation

Device Deselect

Bank Active

Row Address

V

X

V

H

L

Column

X

L

H

L

Read

L

X

Read with Autoprecharge

Write

L

H

L

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst stop

H

L

X

H

L

X

Data Write/Output Enable

Data Mask/Output Disable

Auto Refresh

V

L

H

X

H

X

H

X

H

X

V

X

Self Refresh Entry

H

L

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

L

H

L

H

L

X

1

Self Refresh Exit

H

L

Precharge Power Down

Entry

H

L

Precharge Power Down Exit

Clock Suspend Entry

H

L

H

L

H

Clock Suspend Exit

L

H

L

H

L

X

Deep Power Down Entry

Deep Power Down Exit

L

H

L

H

Notes:

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.

2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.

Rev 1.5 / Jan. 2009

17

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CURRENT STATE TRUTH TABLE (Sheet 1 of 4)

Command

Current

State

Action

Notes

BA0/

BA1

CS RAS CAS WE

Amax-A0

Description

L

H

L

OP CODE

Mode Register Set

Set the Mode Register

14

5

X

Auto or Self Refresh Start Auto or Self Refresh

H

BA

Precharge

No Operation

Activate the specified

bank and row

L

H

L

H

L

BA

Row Add.

Bank Activate

Col. Add.

A10

Idle

H

Write/WriteAP

ILLEGAL

4

Col. Add.

A10

L

H

X

L

H

X

H

X

BA

X

Read/ReadAP

ILLEGAL

4

3

X

No Operation

No Operation or Power

Down

H

X

Device Deselect

Mode Register Set

L

H

L

OP CODE

ILLEGAL

13,14

X

Auto or Self Refresh ILLEGAL

13

7

H

BA

Precharge

ILLEGAL

H

Row Add.

Bank Activate

4

Row

Active

Col. Add.

A10

Start Write: optional

AP(A10=H)

L

H

L

BA

Write/WriteAP

Read/ReadAP

6

Col. Add.

A10

Start Read: optional

AP(A10=H)

H

L

H

L

H

X

L

H

X

L

H

X

L

X

No Operation

ILLEGAL

Device Deselect

Mode Register Set

OP CODE

13,14

13

L

H

X

Auto or Self Refresh ILLEGAL

Termination Burst: Start

the Precharge

L

H

L

H

L

BA

Precharge

Row Add.

Bank Activate

Write/WriteAP

ILLEGAL

4

Read

Col. Add.

A10

Termination Burst: Start

Write(optional AP)

H

8,9

Col. Add.

A10

Termination Burst: Start

Read(optional AP)

L

H

L

H

BA

X

Read/ReadAP

No Operation

8

H

X

Continue the Burst

Rev 1.5 / Jan. 2009

18

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CURRENT STATE TRUTH TABLE (Sheet 2 of 4)

Command

Current

State

Action

Notes

BA0/

CS RAS CAS WE

Amax-A0

Description

BA1

Read

H

L

X

L

X

L

X

L

X

Device Deselect

Continue the Burst

ILLEGAL

OP CODE

Mode Register Set

13,14

13

L

H

X

Auto or Self Refresh ILLEGAL

Termination Burst: Start

the Precharge

L

H

L

H

L

BA

Precharge

10

4

Row Add.

Bank Activate

Write/WriteAP

ILLEGAL

Write

Col. Add.

A10

Termination Burst: Start

Write(optional AP)

H

8

Col. Add.

A10

Termination Burst: Start

Read(optional AP)

L

H

L

H

BA

Read/ReadAP

8,9

L

H

L

H

L

H

X

L

H

X

L

H

X

L

X

No Operation

Continue the Burst

ILLEGAL

Device Deselect

Mode Register Set

OP CODE

13,14

13

L

H

L

X

BA

X

Auto or Self Refresh ILLEGAL

L

H

L

Precharge

ILLEGAL

4,12

12

Read with

Auto

Precharge

L

H

L

Row Add.

Bank Activate

ILLEGAL

H

X

L

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

ILLEGAL

L

H

X

L

ILLEGAL

12

H

X

L

X

No Operation

Continue the Burst

ILLEGAL

X

Device Deselect

Mode Register Set

OP CODE

13,14

13

L

H

L

X

BA

X

Auto or Self Refresh ILLEGAL

L

H

L

Precharge

ILLEGAL

4,12

12

Write with

Auto

Precharge

L

H

L

Row Add.

Bank Activate

ILLEGAL

H

X

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

ILLEGAL

L

H

X

ILLEGAL

12

H

X

No Operation

Continue the Burst

X

Device Deselect

Rev 1.5 / Jan. 2009

19

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CURRENT STATE TRUTH TABLE (Sheet 3 of 4)

Command

BA0/

Current

State

Action

Notes

CS RAS CAS WE

Amax-A0

Description

BA1

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

H

X

Auto or Self Refresh ILLEGAL

No Operation:

Bank(s) idle after tRP

L

H

L

BA

Precharge

L

H

L

H

L

BA

Row Add.

Bank Activate

ILLEGAL

4,12

Precharging

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

ILLEGAL

L

H

ILLEGAL

No Operation:

Bank(s) idle after tRP

L

H

X

H

X

H

X

No Operation

No Operation:

Bank(s) idle after tRP

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

X

Auto or Self Refresh ILLEGAL

H

BA

Precharge

ILLEGAL

4,12

4,11,1

2

L

H

BA

Row Add.

Bank Activate

Row

Activating

L

H

L

BA

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

ILLEGAL

4,12

H

No Operation: Row

Active after tRCD

L

H

X

H

X

H

X

No Operation

No Operation: Row

Active after tRCD

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

X

Auto or Self Refresh ILLEGAL

H

BA

Precharge

ILLEGAL

4,13

4,12

H

Row Add.

Bank Activate

Write

Recovering

Start Write:

Optional AP(A10=H)

L

H

L

H

BA

X

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

Start Read: Optional

AP(A10=H)

9

No Operation:

Row Active after tDPL

H

X

No Operation

Rev 1.5 / Jan. 2009

20

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CURRENT STATE TRUTH TABLE (Sheet 4 of 4)

Command

Current

State

Action

Notes

BA0/

CS RAS CAS WE

Amax-A0

Description

BA1

Write

Recovering

No Operation:

Row Active after tDPL

H

X

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

4,13

4,12

4,9,12

Write

L

H

L

Row Add.

Bank Activate

Recovering

with Auto

Precharge

H

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

L

H

No Operation:

Precharge after tDPL

L

H

X

H

X

H

X

No Operation

No Operation:

Precharge after tDPL

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

13

L

H

L

Row Add.

Bank Activate

13

H

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

13

Refreshing

L

H

13

No Operation:

idle after tRC

L

H

X

H

X

H

X

No Operation

No Operation:

idle after tRC

H

Device Deselect

L

H

L

OP CODE

Mode Register Set

ILLEGAL

13,14

13

X

Auto or Self Refresh ILLEGAL

L

H

L

BA

Precharge

ILLEGAL

13

L

H

L

Row Add.

Bank Activate

13

Mode

Register

Accessing

H

Col. Add. A10 Write/WriteAP

Col. Add. A10 Read/ReadAP

13

L

H

13

No Operation:

idle after 2 clock cycles

L

H

X

H

X

H

X

No Operation

No Operation:

idle after 2 clock cycles

H

Device Deselect

Rev 1.5 / Jan. 2009

21

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Notes:

1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.

2. All entries assume that CKE was active during the preceding clock cycle.

3. If both banks are idle and CKE is inactive, then in power down cycle

4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,

depending on the state of that bank.

5. If both banks are idle and CKE is inactive, then Self Refresh mode.

6. Illegal if tRCD is not satisfied.

7. Illegal if tRAS is not satisfied.

8. Must satisfy burst interrupt condition.

9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

10. Must mask preceding data which don't satisfy tDPL.

11. Illegal if tRRD is not satisfied

12. Illegal for single bank, but legal for other banks in multi-bank devices.

13. Illegal for all banks.

14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.

Rev 1.5 / Jan. 2009

22

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CKE Enable(CKE) Truth TABLE (Sheet 2 of 1)

CKE

Command

Current

State

Previ-

ous Cy-

cle

Action

Notes

Current

Cycle

BA0, Amax

CS RAS CAS WE

BA1

-A0

H

L

X

INVALID

1

2

Exit Self Refresh with

Device Deselect

H

X

Exit Self Refresh with

No Operation

L

H

L

H

X

2

Self

Refresh

L

H

L

H

L

H

L

X

H

X

L

X

ILLEGAL

2

ILLEGAL

L

X

H

X

L

ILLEGAL

L

X

H

L

X

H

L

Maintain Self Refresh

INVALID

H

X

1

2

Power Down mode exit,

all banks idle

L

H

Power

Down

L

X

ILLEGAL

2

X

L

X

Maintain Power Down Mode

INVALID

H

X

1

5

Deep

Power

Down

Deep Power

Down mode exit

L

H

L

X

Maintain Deep

Power Down Mode

Rev 1.5 / Jan. 2009

23

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)

CKE

Command

Current

State

Action

Notes

Previous Current

BA0, Amax-

CS RAS CAS WE

Cycle

BA1

A0

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

3

Refer to the idle State section

of the Current State

Truth Table

L

X

Auto Refresh

L

OP CODE

Mode Register Set

4

3

4

All

Banks

Idle

X

H

L

X

H

L

X

H

L

Refer to the idle State section

of the Current State

Truth Table

L

X

Entry Self Refresh

Mode Register Set

Power Down

L

OP CODE

X

4

Refer to operations of

the Current State

Truth Table

H

L

X

Any State

other than

listed above

Begin Clock Suspend

next cycle

X

Exit Clock Suspend

next cycle

L

H

L

X

Maintain Clock Suspend

Notes:

1. For the given current state CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.

When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of

clock after CKE goes high.

3. The address inputs depend on the command that is issued.

4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered

from the all banks idle state.

5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.

When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of

clock after CKE goes high and is maintained for a minimum 200usec.

Rev 1.5 / Jan. 2009

24

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Mobile SDR SDRAM OPERATION

State Diagram

Power

On

ACT :

Active

DPDS :

Enter Deep

Power-Down

Precharge

All

Bank

Auto

Refresh

DPDSX :

Exit Deep Power-

DownEMRS

EMRS :

Ext. Mode Reg.

Set

(E)MRS

REFS

(EXTENDED)

Mode Register

Self

Refresh

IDLE

REFX

Set

MRS :

Mode Register Set

PRE :

Precharge

DEEP

POWER

DOWN

PREALL :

Precharge All

Banks

Power

Down

REFA :

Auto Refresh

WRITEA

SUSPEND

READA

SUSPEND

Active

Power

Down

REFS :

Enter Self Refresh

REFSX :

Exit Self Refresh

READ

with AP

WRITE

with AP

READ :

Read w/o Auto

Precharge

Read

Write

READA :

Read with Auto

Precharge

Read

ROW

Write

READ

WRITE

ACTIVE

WRITE :

Write w/o Auto

Precharge

WRITEA :

Write with Auto

Precharge

WRITE

SUSPEND

READ

SUSPEND

Automatic Sequence

Precharge

Manual input

All

Rev 1.5 / Jan. 2009

25

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

DESELECT

The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile

SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command is used to perform a NOP to a Mobile SDRAM that is selected (CS = Low, RAS =

CAS = WE = High). This command is not an execution command. However, the internal operations continue. This pre-

vents unwanted commands from being registered during idle or wait states. Operations already in progress are not

affected. (see to next figure)

ACTIVE

The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of

the BA0,BA1 inputs selects the bank, and the address provided on A0-A13(only for the 1KBytes page size. For the

2KBytes page size, A0~A12 are provided) selects the row. This row remains active (or open) for accesses until a PRE-

CHARGE command is issued to that bank. (see to next figure)

CLK

CKE

CLK

CKE

High

CS

RAS

CAS

WE

CAS

WE

RA

BA

A0~A13

BA0,1

A0~A13

BA0,1

Row Address

Bank Address

Don't Care

ACTIVATING A SPECIFIC

ROW IN A SPECIFIC BANK

NOP command

(A13 is used as 1KBytes reduced page)

Rev 1.5 / Jan. 2009

26

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ / WRITE COMMAND

Before executing a read or write operation, the corresponding bank and the row address must be activated by the

bank active (ACT) command. An interval of tRCD is required between the bank active command input and the follow-

ing read/write command input.

The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and

address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being

accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open

for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.

The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank

and address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being

accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open

for subsequent access.

When READ or WRITE command issues, the A0~A7 (column address) are provided if only 1KBytes page size. If the

page size is 2KBytes, the A0~A8 (column address) are provided as shown below figure.

CLK

CKE

CLK

CKE

High

CS

RAS

CAS

W E

CAS

W E

CA

BA

CA

BA

A0 ~ A8

High to Enable

Auto Precharge

A10

Low to Disable

Auto Precharge

BA0,1

Read Com m and

Operation

W rite Com m and

Operation

Don't Care

READ / WRITE COMMAND

(A13 is used as 1KBytes reduced page)

Rev 1.5 / Jan. 2009

27

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ

A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)

cycle after read command set. The SDRAM can perform a burst read operation.

The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and

the bank select address at the read command set cycle. In a read operation, data output starts after the number of

clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.

When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the suc-

cessive burst-length data has been output.

The /CAS latency and burst length must be specified at the mode register.

tCK

CLK

REA

D

Command

DQ

NOP

tOH

Do0

tLZ

Do1

Do2

Do3

tAC

CL = 2

REA

D

NOP

tOH

Do0

Command

tLZ

Do1

Do2

Do3

DQ

tAC

Undefined

Don't Care

CL = 3

Read Burst Showing CAS Latency

Rev 1.5 / Jan. 2009

28

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ to READ

Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the

new burst follows either the last element of a completed burst or the last desired element of a longer burst that is

being truncated.

When another read command is executed at the same ROW address of the same bank as the preceding read com-

mand execution, the second read can be performed after an interval of no less than 1 clock. Even when the first com-

mand is a burst read that is not yet finished, the data read by the second command will be valid.

CLK

Command

Address

NOP

READ’

READ

NOP

BA, Col

a

BA, Col

b

CL =2

DQ

Doa0

Doa1

Doa0

Dob0

Doa1

Dob1

Dob0

CL =3

Don't Care

Consecutive Read Bursts

A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are

shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig.

Rev 1.5 / Jan. 2009

29

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CLK

Command

READ

BA, Col

n

BA, Col

b

Address

DQ

CL =2

CL =3

Don

Dob

Don

DQ

Don't Care

1) Don (or b): Data out from column n

2) BA, Col n (b) = Bank A, Column n (b)

3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b)

Non-Consecutive Read Bursts

CLK

Command

READ

BA, Col

g

BA, Col

n

BA, Col

x

BA, Col

b

Address

DQ

CL =2

CL =3

Dog'

Dog

Dox

Dox'

Dox

Dob

Dox'

Don

Don'

Don

Dob'

Dob

Dog

Dob'

Dog’

Don'

DQ

1) Don, etc: Data out from column n, etc

n', x', etc : Data Out elements, accoding to the programmd burst order

2) BA, Col n = Bank A, Column n

Don't Care

3) Burst Length = 1, 2, 4, 8 or full page in cases shown

4) Read are to active row in any banks

Random Read Bursts

Rev 1.5 / Jan. 2009

30

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ BURST TERMINATE

Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is

equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com-

mand where X equals the desired data-out element.

CLK

Command

Address

READ

BURST

BA, Col

n

CL =2

CL =3

DQ

Don

Don'

Don

Don'

1) Don : Data out from column n

2) BA, Col n = Bank A, Column n

Don't Care

3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elements

Terminating a Read Burst

Rev 1.5 / Jan. 2009

31

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ to WRITE

Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun-

cation is necessary, the BURST TERMINATE command must be used, as shown in next fig.

CLK

Command

Address

READ

BURST

WRITE

BA, Col

n

BA, Col

b

CL =2

CL =3

DQ

Don

Don'

Don

DIb0

DIb3

DIb1

DIb2

Don'

Don't Care

1) DO n = Data Out from column n; DI b = Data In to column b

Read to Write

Notes:

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as

the preceding read command, the write command can be performed after an interval of no less than 1 clock.

However, DQM must be set High so that the output buffer becomes High-Z before data input.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;

it is necessary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided

that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before

data input.

Rev 1.5 / Jan. 2009

32

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

READ to PRECHARGE

Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.

Note that part of the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time

(as described above) provides the same operation that would result from the same fixed-length burst with auto pre-

charge.

The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at

the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to trun-

cate fixed-length or full-page bursts.

CLK

Command

Address

READ

PRE

ACT

tRP

Bank

A, All

BA, Col

n

BA,

Row

CL =2

CL =3

DQ

Don

Don't Care

1) DO n = Data Out from column n

2) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.

3) The ACTIVE command may be applied if tRC has been met.

READ to PRECHARGE

Rev 1.5 / Jan. 2009

33

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Write

Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing

coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;

if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to

that byte / column location.

During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subse-

quent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length

burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will

be ignored. A full-page burst will continue until terminated.

Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE

burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any

clock following the previous WRITE command, and the data provided coincident with the new command applies to the

new command.

CLK

Command

Address

WRITE

BA, Col

b

DQ

BL = 1

BL = 2

BL = 4

BL = 8

DIb0

DIb1

DQ

DIb1

DIb0

DIb2

DIb3

DIb4

DIb5

DIb6

DIb7

Don't Care

CL = 2 or 3

Basic Write timing parameters for Write Burst Operation

Notes:

1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the

preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes,

the second write command has priority.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;

it is necessary to separate the two write commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock,

provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

WRITE to WRITE

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,

a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of

the clock following the previous WRITE command. The first data-in element from the new burst is applied after either

the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The

new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of

desired data-in element.

CLK

Command

WRITE

BA, Col

b

BA, Col

n

Address

DQ

DIb1

DIn0

DIb0

DIn1

DIb2 DIb3

DIn2 DIn3

DM

CL = 2 or 3

Don't Care

Concatenated Write Bursts

CLK

Command

WRITE

NOP

BA, Col

b

BA, Col

x

BA, Col

n

BA, Col

a

BA, Col

g

Address

DQ

DIb'

DIn

DIb

DIn’

DIx

DIa

DIg

DIx’

DIa’

DIg’

DM

Don't Care

CL = 2 or 3

Random Write Cycles

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

WRITE to READ

CLK

Command

WRITE

READ

BA, Col

b

BA, Col

n

Address

CL = 2

CL = 3

BL = 4

DIb1

DOn0

DIb0

DOn1

DOn0

DOn2 DOn3

DQ

DOn1

DOn2

DOn3

Don't Care

The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new

read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency.

The preceding write operation (WRIT) writes only the data input before the read command.

The data bus must go into a high-impedance state at least one cycle before output of the latest data.

Notes:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank

as the preceding write command, the read command can be performed after an interval of no less than 1 clock.

However, in the case of a burst write, data will continue to be written until one clock before the read command is

executed.

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be

executed; it is necessary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1

clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will

continue to be written until one clock before the read command is executed (as in the case of the same bank

and the same address).

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

WRITE to PRECHARGE

Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto

Precharge was not activated). When the precharge command is executed for the same bank as the write command

that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is

unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a

WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.

CLK

Command

Address

WRITE

PRE

BA, Col

b

CL = 2 or 3

BL = 4

DIb0

DIb3

DIb1

DIOb2

DQ

tDPL

Non-Interrupting Write to Precharge

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.

Note that only data-in that are registered prior to the tDPL period are written to the internal array, and any subsequent

data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com-

mand to the same bank cannot be issued until tRP is met.

CLK

Command

Address

WRITE

PRE

BA, Col

b

CL = 2 or 3

BL = 4

DIb0

DIb1

DIOb2

tDPL

DQ

Interrupting Write to Precharge

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

WRITE BURST TERMINATE

WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input

data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command.

CLK

Command

Address

WRITE

BST

BA, Col

b

High-Z

BL = 4 or higher CL = 2 or 3

DIb0

DIb1

DIOb2

DQ

Don’t care - Data ignored

Terminating a Burst Write command with BST

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

BURST TERMINATE

The BURST TERMINATE command is used to truncate read bursts or write bursts (with auto precharge disabled). The

most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as

shown in the Operation section of this datasheet. The BURST TERMINATE command is not bank specific.

The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided.

CLK

CKE

High

CS

RAS

CAS

WE

A0~A13

Don't Care

BA0, 1

BURST TERMINATE COMMAND

(A13 is used as 1KBytes reduced page)

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.

Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is

completed.

If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,

A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE

command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the

process of precharging.

The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided.

CKE

High

A10 defines the precharge

mode when a precharge

command, a read command

or a write command is

issued.

CS

RAS

If A10 = High when a

precharge command is

issued, all banks are

precharged.

CAS

WE

If A10 = Low when a

precharge command is

issued, only the bank that is

selected by BA1/BA0 is

precharged.

A0~A9

A11~A13

If A10 = High when read or

write command, auto-

precharge function is

enabled.

A10

While A10 = Low, auto-

precharge function is

disabled.

BA0,1

BA

Bank Address

Don't Care

PRECHARGE command

(A13 is used as 1KBytes reduced page)

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with-

out requiring an explicit command.

This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write

command. This precharges the bank/row after the Read or Write burst is complete.

Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is

desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.

The user must not issue another command to the same bank until the precharge time (tRP) is completed.

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

AUTO REFRESH AND SELF REFRESH

Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two

ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:

- AUTO REFRESH.

This command is used during normal operation of the Mobile SDRAM. It is non persistent, so must be issued each time

a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile SDRAM requires

AUTO REFRESH commands at an average periodic interval of tREF.

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile SDRMA, and

the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is

8*tREF.

-SELF REFRESH.

This state retains data in the Mobile SDRAM, even if the rest of the system is powered down. Note refresh interval tim-

ing while in Self Refresh mode is scheduled internally in the Mobile SDRAM and may vary and may not meet tREF time.

After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self refresh

operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh

exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF

(max.) period on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all

refresh addresses are completed.

2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below* after exiting

from self-refresh mode.

Note: tREF (max.) / refresh cycles.

The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is

raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom-

mended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self

Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section.

The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile

SDRAM operates refresh cycle asynchronously.

The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM

can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode regis-

ters. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Tempera-

ture Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the

value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these

two modes.

The figure of next page shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided.

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CLK

CKE

CLK

CKE

High

CS

RAS

CAS

WE

CAS

WE

A0~A13

BA0, 1

A0~A13

Don't Care

BA0, 1

AUTO REFRESH COMMAND

SELF REFRESH ENTRY COMMAND

(A13 is used as 1KBytes reduced page)

Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set.

Function

Auto Refresh

CKEn-1

CKEn

CS

RAS CAS WE DQM ADDR

A10/AP

BA

H

L

H

X

Self Refresh Entry

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

MODE REGISTER SET

The mode registers are loaded via the address bits.

BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register

description in the register definition section. The MODE REGISTER SET command can only be issued when all banks

are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met.

The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided.

(A13 is used as 1KBytes reduced page)

CLK

CKE

High

CS

RAS

CAS

WE

Code

A0~A13

BA0, 1

Don't Care

MODE REGISTER SET COMMAND

Note: BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register.

CLK

MRS

NOP

tMRD

Valid

Command

Address

Code

Don't Care

Code = Mode Register / Extended Mode Register selection

(BA0, BA1) and op-code (A0 - An)

tMRD DEFINITION

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

POWER DOWN

Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in

progress. If power down occurs when all banks are idle, it is Precharge Power Down.

If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot

stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is

exited by setting CKE high while issuing a Device Deselect or NOP command.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down

deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby.

DEEP POWER-DOWN

The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the

Mobile SDRAM are stopped and all memory data is lost in this mode.

All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER-DOWN

COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus

prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.

To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least

200 us. After 200 us a complete re-initialization routing is required defined for the initialization sequence.

The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided.

CLK

CKE

CS

RAS

CAS

WE

CAS

WE

A0~A13

BA0, 1

A0~A13

BA0, 1

Don't Care

DEEP POWER-DOWN COMMAND

(A13 is used as 1KBytes reduced page)

POWER-DOWN COMMAND

Rev 1.5 / Jan. 2009

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CLK

CKE

COMMAND

NOP

ACTIVE

tRCD

NOP

All banks idle

Input buffers gated off

tRAS

tRC

Enter power-down mode. Exit power-down mode.

DON’T CARE

CLK

CKE

tCKS

NOP

200us(min)

Deep Power down Exit

PCG

NOP

APCG

COMMAND

Input buffers gated off

Pre-charge all

Deep Power down entry

DON’T CARE

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

CLK

CKE

tCKS

Power down Exit Time

CS

RAS

CAS

WE

Ra

Ca

VDDR

BA0, BA1

AP

Hi-Z

Qa0 Qa1 Qa2

DQ

DQM

Row Active

Read

Precharge

Power down

Entry

Precharge

Power down Power down Power down

Exit Entry Exit

Active

Don’t care

Note : CKE should be set high at least 1CLK + tCKS prior to Row active command.

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

tCK

tCH

tCL

CLK

tCKS

tRAS(MIN)

tCKS

tCMS

tCKH

tCMH

CKE

COMMAND

DQM

AUTO

REFRESH

or COMMAND

INHIBIT

PRECHARGE

NOP

Any COM

A0-

A9,Amax

ALL BANKS

A10

SINGLE BANK

tAS

tAH

BANKS

BA0, BA1

DQ

High-Z

tRP

tXSR

Enter self refresh mode

Precharge all

active banks

Exit self refresh mode

(Restart refresh time base)

DON’T CARE

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Power-up and Initialization

Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined man-

ner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After

power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDRAM.

Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register

set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a

extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The fol-

lowing these cycles, the Mobile SDRAM is ready for normal operation.

Programming the registers

Mode Register

The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of

a burst length(1, 2, 4, 8, Full Page), a cas latency(2 or 3), a burst type. The mode register set must be done before any

activate command after the power up sequence. Any contents of the mode register be altered by re-programming the

mode register through the execution of mode register set command.

Extended Mode Register

The extended mode register contains the specific features of self refresh operation of the Mobile SDRAM. This register

includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set

must be done before any activate command after the power up sequence. Any contents of the mode register be altered

by re-programming the mode register through the execution of extended mode register set command.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by

activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects

the bank, and the value on the A0-A13(or A12 which depends on page size) selects the row. This row remains active

for column access until a precharge command is issued to that bank. Read and write operations can only be initiated

on this activated bank after the minimum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and

deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Pre-

charge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not

selected, the row will remain active for subsequent accesses.

The length of burst and the CAS latency will be determined by the values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE

and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the starting column location. The value on input A10 determines whether or not Auto Precharge is used.

If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Pre-

charge is not selected, the row will remain active for subsequent accesses.

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Precharge

The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the

precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open

row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the

precharge command is issued.

Auto Precharge

The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If

A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.

Burst Termination

The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst

Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts

a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the

bank open.

Data Mask

The Data Mask command is used to mask READ or WRITE data. During a READ operation, When this command is is-

sued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When

this command is issued, data inputs can't be written with no clock delay.

If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled.

If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During

the write cycle, DQM mask data input with zero latency

CK

WRIT

CMD

DM

Data Masking

0 Latency

Data Masking

0 Latency

Hi-Z

MK

D1

D0

DIN0

D1

D0

D1

D0

DIN2

D1

D0

DQ

MK

Write Data Masking

CK

READ

CMD

DM

DQ

Data Masking

2 Latency

Hi-Z

MK

D0

D1

D0

D1

D0

D1

D0

D1

DOUT0

DOUT1

DDOT2

Read Data Masking

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Clock Suspend

The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops

transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the

device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends

data Read and Write operations. (See examples in next Figures)

CLK

Command

CKE

RD

Masked by CKE

Internal CLK

DQ

Frozen Int. CLK by CKE

(CKE = Fixed Low)

Q2

Q3

Q4

Q1

Clock Suspend

Mode

Command

CKE

WR

D1

Masked by CKE

Internal CLK

DQ

Frozen Int. CLK by CKE

(CKE = Fixed Low)

D2

D3

D4

Clock Suspend

Mode

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Power Down

The Power Down command is used to reduce stand-by current. Before this command is issued, all banks must be pre-

charged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping

CKE low, all of the input buffer except CKE are gated off.

Auto Refresh

The Auto Refresh command is used during normal operation and is similar to CBR refresh in Conventional DRAMs.

This command must be issued each time a refresh is required. When an Auto Refresh command is issued, the address

bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter.

Self Refresh

The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM

operates refresh cycle asynchronously.

The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM

can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers.

The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature

Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of

PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two

modes.

Deep Power Down

The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory

array of the devices.

For more information, see the special operation for Low Power consumption of this data sheet.

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Special Operation for Low Power Consumption

Deep Power Down Mode

Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole

memory array of the devices.

Data will not be retained once the device enters Deep Power Down Mode.

Full initialization is required when the device exits from Deep Power Down Mode.

Truth Table

Current State

Idle

Command

CKEn-1

CKEn

CS

L

RAS

H

CAS

H

WE

L

Deep Power Down Entry

Deep Power Down Exit

H

L

Deep Power Down

H

X

Deep Power Down Mode Entry

The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the

clock, while CKE is low. The following diagram illustrates deep power down mode entry.

CKE

CS

RAS

CAS

WE

tRP

Pre-charge

if needed

Deep Power

Down Entry

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512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

Deep Power Down Mode (Continued)

Deep Power Down Mode Exit Sequence

The Deep Power Down mode is exited by asserting CKE high.

After the exit, the following sequence is needed to enter a new command.

1. Maintain NOP input conditions for a minimum of 200usec

2. Issue precharge commands for all banks of the device

3. Issue 8 or more auto refresh commands

4. Issue a mode register set command to initialize the mode register

5. Issue an extended mode register set command to initialize the extended mode register

The following timing diagram illustrates deep power down mode exit sequence.

CLK

CKE

CS

RAS

CAS

WE

200us

tRP

tRC

Extended

Mode

Register

Set

New

Mode

Register

Set

Deep Power Down Exit

All Banks

Precharge Refresh

Auto

Refresh

Command

Accepted

Here

Rev 1.5 / Jan. 2009

53

11

512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122DFR Series / H55S5132DFR Series

PACKAGE INFORMATION

90 Ball FBGA 0.8mm pitch (8.0mm x 13.0mm)

A1 INDEX MARK

8.00 Typ.

0.8

0.8Typ.

Unit [mm]

0.90.

0.80 Typ.

Bottom

View

0.45

+/- 0.05

0.35

+/- 0.05

0.90

6.40 Typ.

0.8

1.00 max

Rev 1.5 / Jan. 2009

54

型号:	H55S5122DFR-60M
是否Rohs认证：	符合
生命周期：	Obsolete
包装说明：	FBGA, BGA90,9X15,32
Reach Compliance Code：	compliant
风险等级：	5.81
最长访问时间：	5.4 ns
最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PBGA-B90
JESD-609代码：	e1
内存密度：	536870912 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	32
端子数量：	90
字数：	16777216 words
字数代码：	16000000
最高工作温度：	85 °C
最低工作温度：	-30 °C
组织：	16MX32
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA
封装等效代码：	BGA90,9X15,32
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, FINE PITCH
电源：	1.8 V
认证状态：	Not Qualified
刷新周期：	8192
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.0003 A
子类别：	DRAMs
最大压摆率：	0.1 mA
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
端子形式：	BALL
端子节距：	0.8 mm
端子位置：	BOTTOM
Base Number Matches：	1

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