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产品型号H5TQ1G63DFR-PBC的概述

芯片H5TQ1G63DFR-PBC的概述 H5TQ1G63DFR-PBC是一款由韩国三星(Samsung)公司生产的DDR2(双倍数据速率)SDRAM(同步动态随机存取内存)芯片,广泛应用于各种电子设备中,如手机、平板电脑、笔记本电脑和嵌入式系统。该芯片具有较高的存储密度和低功耗的特点,能够满足现代电子设备对存储性能和功耗的严格要求。 芯片H5TQ1G63DFR-PBC的详细参数 H5TQ1G63DFR-PBC芯片的参数主要包括以下几个方面: 1. 型号: H5TQ1G63DFR-PBC 2. 内存类型: DDR2 SDRAM 3. 容量: 1GB(即1Gbit) 4. 数据总线宽度: 16位 5. 工作电压: 1.8V(Vdd) 6. 时序: CL(CAS Latency)= 5 7. 存取速度: 400 MHz(有效工作速度) 8. 封装形式: FBGA(Fine Ball Gri...

产品型号H5TQ1G63DFR-PBC的Datasheet PDF文件预览

1Gb DDR3 SDRAM  
1Gb DDR3 SDRAM  
Lead-Free&Halogen-Free  
(RoHS Compliant)  
H5TQ1G83DFR-xxC  
H5TQ1G83DFR-xxI  
H5TQ1G83DFR-xxL  
H5TQ1G83DFR-xxJ  
H5TQ1G63DFR-xxC  
H5TQ1G63DFR-xxI  
H5TQ1G63DFR-xxL  
H5TQ1G63DFR-xxJ  
*Hynix Semiconductor reserves the right to change products or specifications without notice  
Rev. 1.8 /June. 2013  
1
Revision History  
Revision No.  
History  
Date  
Remark  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
Added IDD Value  
Corrected Typo Error  
Aug. 2010  
Sep. 2010  
Oct. 2010  
Dec. 2010  
Dec. 2010  
Dec. 2010  
Jun. 2011  
Sep. 2011  
Corrected Typo Error(Ordering Information)  
Added 1866/2133 Speed Support  
Added IDD Specification(1866/2133 Speed)  
Modified OPERATING FREQUENCY Table  
Added J and L-part support  
Updated 1866/2133 x8 IDD Specification  
and 1866 Frequency downbinning  
0oC ~ 85 oC --> 0oC ~ 95 oC  
1.8  
Commercial Temperature Range update  
June. 2013  
Rev. 1.8 /June. 2013  
2
Description  
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchro-  
nous DRAM, ideally suited for the main memory applications which requires large memory density and  
high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and  
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK  
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and  
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-  
width.  
Device Features and Ordering Information  
FEATURES  
• DQ Power & Power supply : VDD & VDDQ = 1.5V +/-  
0.075V  
• Programmable BL=4 supported (tCCD=2CLK) for Digi-  
tal consumer Applications.  
DQ Ground supply : VSSQ = Ground  
• Programmable ZQ calibration supported  
• BL switch on the fly  
• Fully differential clock inputs (CK, CK) operation  
• Differential Data Strobe (DQS, DQS)  
• 8banks  
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)  
- 7.8 µs at -0oC ~ 85 oC  
• On chip DLL align DQ, DQS and DQS transition with CK  
transition  
- 3.9 µs at 85oC ~ 95 oC  
• DM masks write data-in at the both rising and falling   
edges of the data strobe  
Commercial Temperature ( 0oC ~ 95 oC)  
Industrial Temperature ( -40oC ~ 95 oC)  
• All addresses and control inputs except data,   
data strobes and data masks latched on the   
rising edges of the clock  
• Auto Self Refresh supported  
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)  
• Driver strength selected by EMRS  
• Dynamic On Die Termination supported  
• Asynchronous RESET pin supported  
• TDQS (Termination Data Strobe) supported (x8 only)  
• Write Levelization supported  
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13  
and 14 supported  
• Programmable additive latency 0, CL-1, and CL-2   
supported  
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,  
10  
• Programmable burst length 4/8 with both nibble  
sequential and interleave mode  
• On Die Thermal Sensor supported  
• 8 bit pre-fetch  
• Programmable PASR(Partial Array Self-Refresh) for  
Digital consumer Applications.  
* This product in compliance with the RoHS directive.  
Rev. 1.8 /June. 2013  
3
ORDERING INFORMATION  
Part No.  
Configuration  
Power Consumption  
Temperature  
Package  
H5TQ1G83DFR-*xxC  
H5TQ1G83DFR-*xxI  
H5TQ1G83DFR-*xxL  
H5TQ1G83DFR-*xxJ  
H5TQ1G63DFR-*xxC  
H5TQ1G63DFR-*xxI  
H5TQ1G63DFR-*xxL  
H5TQ1G63DFR-*xxJ  
Commercial  
Industrial  
Normal Consumption  
128M x 8  
64M x 16  
78ball FBGA  
Commercial  
Industrial  
Low Power Consumption  
(IDD6 Only)  
Commercial  
Industrial  
Normal Consumption  
96ball FBGA  
Commercial  
Industrial  
Low Power Consumption  
(IDD6 Only)  
* xx means Speed Bin Grade  
OPERATING FREQUENCY  
Frequency [MHz]  
CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 CL14  
Speed  
Grade  
(Marking)  
Remark  
(CL-tRCD-tRP)  
-G7  
-H9  
-PB  
-RD  
-TE  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DDR3-1066 7-7-7  
O
O
O
O
O
O
O
O
DDR3-1333 9-9-9  
O
O
O
DDR3-1600 11-11-11  
DDR3-1866 13-13-13  
DDR3-2133 14-14-14  
O
O
O
O
O
Rev. 1.8 /June. 2013  
4
Package Ballout/Mechanical Dimension  
x8 Package Ball out (Top view): 78ball FBGA Package (no support balls)  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS  
VSS  
VDD  
VSSQ  
DQ2  
DQ6  
VDDQ  
VSS  
VDD  
CS  
NC  
DQ0  
DQS  
DQS  
DQ4  
RAS  
CAS  
WE  
NU/TDQS  
DM/TDQS  
DQ1  
VSS  
VSSQ  
DQ3  
VSS  
DQ5  
VSS  
VDD  
ZQ  
VDD  
VDDQ  
VSSQ  
VSSQ  
VDDQ  
NC  
A
B
C
D
E
F
VDDQ  
VSSQ  
VREFDQ  
NC  
VDD  
DQ7  
CK  
G
H
J
ODT  
NC  
CK  
CKE  
NC  
G
H
J
A10/AP  
NC  
VSS  
BA0  
A3  
BA2  
A0  
VREFCA  
BA1  
A4  
VSS  
K
L
VDD  
VSS  
A12/BC  
A1  
VDD  
VSS  
K
L
A5  
A2  
M
N
VDD  
VSS  
A7  
A9  
A11  
A6  
VDD  
VSS  
M
N
RESET  
A13  
NC  
A8  
1
2
3
4
5
6
7
8
9
1
2
3
7
8
9
A
B
C
D
E
(Top View: See the balls through the Package)  
F
Populated ball  
Ball not populated  
G
H
J
K
L
M
N
Rev. 1.8 /June. 2013  
5
x16 Package Ball out (Top view): 96ball FBGA Package (no support balls)  
1
2
3
4
5
6
7
8
9
DQU4  
DQSU#  
DQSU  
DQU0  
DML  
A
B
C
D
E
F
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VSS  
DQU5  
VDD  
DQU7  
VSS  
VDDQ  
DQU6  
DQU2  
VSSQ  
VSSQ  
DQL3  
VSS  
VSS  
VSSQ  
VDDQ  
VDD  
VDDQ  
VSSQ  
VSSQ  
VDDQ  
NC  
A
B
C
D
E
F
DQU3  
VDDQ  
VSSQ  
DQL2  
DQL6  
VDDQ  
VSS  
DQU1  
DMU  
DQL0  
DQSL  
DQSL#  
DQL4  
RAS#  
CAS#  
WE#  
BA2  
VDDQ  
VSSQ  
VREFDQ  
NC  
DQL1  
VDD  
G
H
J
G
H
J
DQL7  
CK  
DQL5  
VSS  
K
L
ODT  
VDD  
CK#  
VDD  
CKE  
NC  
K
L
NC  
CS#  
A10/AP  
NC  
ZQ  
M
N
P
R
T
VSS  
BA0  
VREFCA  
BA1  
VSS  
M
N
P
R
T
VDD  
A3  
A0  
A12/BC#  
A1  
VDD  
VSS  
VSS  
A5  
A2  
A4  
VDD  
A7  
A9  
A11  
A6  
VDD  
VSS  
VSS  
RESET#  
NC  
NC  
A8  
1
2
3
4
5
6
7
8
9
1
2
3
7
8
9
A
B
C
D
E
F
(Top View: See the balls through the Package)  
G
H
J
Populated ball  
Ball not populated  
K
L
M
N
P
R
T
Rev. 1.8 /June. 2013  
6
Pin Functional Description  
Symbol  
Type  
Function  
Clock: CK and CK are differential clock inputs. All address and control input signals are  
sampled on the crossing of the positive edge of CK and negative edge of CK.  
CK, CK  
Input  
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and  
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down  
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any  
bank).  
CKE, (CKE0),  
(CKE1)  
Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable  
during the power on and initialization sequence, they must be maintained during all  
operations (including Self-Refresh). CKE must be maintained high throughout read and  
write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-  
down. Input buffers, excluding CKE, are disabled during Self-Refresh.  
Chip Select: All commands are masked when CS is registered HIGH.  
CS provides for external Rank selection on systems with multiple Ranks.  
CS is considered part of the command code.  
CS, (CS0),  
(CS1), (CS2),  
(CS3)  
Input  
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the  
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,  
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8  
configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,  
DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable  
ODT.  
ODT, (ODT0),  
(ODT1)  
Input  
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.  
RAS.  
CAS. WE  
Input  
Input  
Input Data Mask: DM is an input mask signal for write data. Input data is masked when  
DM is sampled HIGH coincident with that input data during a Write access. DM is sampled  
on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by  
Mode Register A11 setting in MR1.  
DM, (DMU),  
(DML)  
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge  
BA0 - BA2  
A0 - A15  
Input command is being applied. Bank address also determines if the mode register or extended  
mode register is to be accessed during a MRS cycle.  
Address Inputs: Provide the row address for Active commands and the column address for  
Read/Write commands to select one location out of the memory array in the respective  
bank. (A10/AP and A12/BC have additional functions, see below).  
Input  
The address inputs also provide the op-code during Mode Register Set commands.  
Auto-precharge: A10 is sampled during Read/Write commands to determine whether  
Autoprecharge should be performed to the accessed bank after the Read/Write operation.  
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge  
command to determine whether the Precharge applies to one bank (A10 LOW) or all  
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank  
addresses.  
A10 / AP  
A12 / BC  
Input  
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst  
Input chop (on-the-fly) will be performed.  
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.  
Rev. 1.8 /June. 2013  
7
Symbol  
Type  
Function  
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when  
RESET is HIGH. RESET must be HIGH during normal operation.  
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.  
1.20V for DC high and 0.30V for DC low.  
RESET  
Input  
Input /  
Output  
DQ  
Data Input/ Output: Bi-directional data bus.  
Data Strobe: output with read data, input with write data. Edge-aligned with read data,  
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential  
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the  
system during reads and writes. DDR3 SDRAM supports differential data strobe only and  
does not support single-ended.  
DQU, DQL,  
DQS, DQS,  
DQSU, DQSU, Output  
DQSL, DQSL  
Input /  
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via  
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance  
TDQS, TDQS Output function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11  
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x16  
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.  
NC  
NF  
No Connect: No internal electrical connection is present.  
No Function  
VDDQ  
VSSQ  
VDD  
Supply DQ Power Supply: 1.5 V +/- 0.075 V  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
DQ Ground  
Power Supply: 1.5 V +/- 0.075 V  
Ground  
VSS  
Reference voltage for DQ  
Reference voltage for CA  
Reference Pin for ZQ calibration  
VREFDQ  
VREFCA  
ZQ  
Note:  
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.  
Rev. 1.8 /June. 2013  
8
ROW AND COLUMN ADDRESS TABLE  
1Gb  
Configuration  
# of Banks  
128Mb x 8  
64Mb x 16  
8
8
Bank Address  
Auto precharge  
BL switch on the fly  
Row Address  
Column Address  
Page size 1  
BA0 - BA2  
A10/AP  
A12/BC  
A0 - A13  
A0 - A9  
1 KB  
BA0 - BA2  
A10/AP  
A12/BC  
A0 - A12  
A0 - A9  
2 KB  
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers   
when an ACTIVE command is registered. Page size is per bank, calculated as follows:  
page size = 2 COLBITS * ORG 8  
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits  
Rev. 1.8 /June. 2013  
9
Absolute Maximum Ratings  
Absolute Maximum DC Ratings  
Absolute Maximum DC Ratings  
Symbol  
Parameter  
Voltage on VDD pin relative to Vss  
Voltage on VDDQ pin relative to Vss  
Voltage on any pin relative to Vss  
Storage Temperature  
Rating  
Units  
Notes  
VDD  
- 0.4 V ~ 1.975 V  
V
1,3  
VDDQ  
VIN, VOUT  
TSTG  
- 0.4 V ~ 1.975 V  
- 0.4 V ~ 1.975 V  
-55 to +100  
V
1,3  
1
V
oC  
1, 2  
Notes:  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at these or any other conditions above  
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-  
ing conditions for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement  
conditions, please refer to JESD51-2 standard.  
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than  
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.  
DRAM Component Operating Temperature Range  
Temperature Range  
Symbol  
Parameter  
Normal Operating Temperature Range  
Extended Temperature Range  
Rating  
0 to 85  
85 to 95  
Units  
oC  
oC  
Notes  
1,2  
1,4  
TOPER  
-40 to 95  
oC  
1,3,4  
Industrial Temperature Range  
Notes:  
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-  
surement conditions, please refer to the JEDEC document JESD51-2.  
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-  
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.  
3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported.  
During operation, the DRAM case temperature must be maintained between -40 - 85oC under all operating condi-  
tions.  
4. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC  
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:  
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.  
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Man-  
ual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).  
Rev. 1.8 /June. 2013  
10  
AC & DC Operating Conditions  
Recommended DC Operating Conditions  
Recommended DC Operating Conditions  
Rating  
Symbol  
Parameter  
Units  
Notes  
Min.  
Typ.  
Max.  
VDD  
1.425  
1.500  
1.575  
V
V
1,2  
1,2  
Supply Voltage  
Supply Voltage for Output  
VDDQ  
1.425  
1.500  
1.575  
Notes:  
1. Under all conditions, VDDQ must be less than or equal to VDD.  
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.  
Rev. 1.8 /June. 2013  
11  
IDD and IDDQ Specification Parameters and Test Conditions  
IDD and IDDQ Measurement Conditions  
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure  
1. shows the setup and test load for IDD and IDDQ measurements.  
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,  
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all  
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-  
rents.  
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all  
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-  
rents.  
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can  
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In  
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one  
merged-power layer in Module PCB.  
For IDD and IDDQ measurements, the following definitions apply:  
”0” and “LOW” is defined as VIN <= V  
ILAC(max).  
”1” and “HIGH” is defined as VIN >= V  
IHAC(min).  
“MID_LEVEL” is defined as inputs are VREF = VDD/2.  
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.  
Basic IDD and IDDQ Measurement Conditions are described in Table 2.  
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.  
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-  
ited to setting  
RON = RZQ/7 (34 Ohm in MR1);  
Qoff = 0 (Output Buffer enabled in MR1);  
B
RTT_Nom = RZQ/6 (40 Ohm in MR1);  
RTT_Wr = RZQ/2 (120 Ohm in MR2);  
TDQS Feature disabled in MR1  
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time  
before actual IDD or IDDQ measurement is started.  
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}  
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}  
Rev. 1.8 /June. 2013  
12  
IDDQ (optional)  
IDD  
VDD  
RESET  
CK/CK  
VDDQ  
DDR3  
SDRAM  
RTT = 25 Ohm  
CKE  
CS  
DQS, DQS  
DQ, DM,  
VDDQ/2  
RAS, CAS, WE  
TDQS, TDQS  
A, BA  
ODT  
ZQ  
VSS  
VSSQ  
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements  
[Note: DIMM level Output test load condition may be different from above]  
Application specific  
memory channel  
environment  
IDDQ  
Test Load  
Channel  
IO Power  
Simulation  
IDDQ  
Simulation  
IDDQ  
Simulation  
Correction  
Channel IO Power  
Number  
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported  
by IDDQ Measurement  
Rev. 1.8 /June. 2013  
13  
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns  
DDR3-1066  
DDR3-1333  
DDR3-1600  
DDR3-1866  
DDR3-2133  
Symbol  
Unit  
7-7-7  
1.875  
7
9-9-9  
1.5  
9
11-11-11  
13-13-13  
1.07  
13  
14-14-14  
0.935  
14  
tCK  
1.25  
11  
11  
39  
28  
11  
24  
32  
5
ns  
CL  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nRCD  
nRC  
nRAS  
nRP  
7
9
13  
14  
27  
20  
7
33  
24  
9
45  
50  
32  
36  
13  
14  
1KB page size  
2KB page size  
1KB page size  
2KB page size  
20  
27  
4
20  
30  
4
26  
27  
nFAW  
33  
38  
5
6
nRRD  
6
5
6
6
7
nRFC -512Mb  
nRFC-1 Gb  
nRFC- 2 Gb  
nRFC- 4 Gb  
nRFC- 8 Gb  
48  
59  
86  
160  
187  
60  
74  
107  
200  
234  
72  
88  
128  
240  
280  
85  
97  
103  
150  
281  
328  
118  
172  
321  
375  
Table 2 -Basic IDD and IDDQ Measurement Conditions  
Symbol  
Description  
Operating One Bank Active-Precharge Current  
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT  
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:  
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see  
IDD0  
Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:  
see Table 3.  
Operating One Bank Active-Read-Precharge Current  
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between  
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to  
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table  
IDD1  
4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see  
Table 4.  
Rev. 1.8 /June. 2013  
14  
Symbol  
Description  
Precharge Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank  
IDD2N  
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;  
Pattern Details: see Table 5.  
Precharge Standby ODT Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: partially toggling according to Table 6; Data IO: MID-LEVEL; DM: stable at 0; Bank  
IDD2NT  
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling  
according to Table 6; Pattern Details: see Table 6.  
Precharge Power-Down Current Slow Exit  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;  
IDD2P0  
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down  
Mode: Slow Exitc)  
Precharge Power-Down Current Fast Exit  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;  
IDD2P1  
IDD2Q  
IDD3N  
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down  
Mode: Fast Exitc)  
Precharge Quiet Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;  
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0  
Active Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank  
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;  
Pattern Details: see Table 5.  
Rev. 1.8 /June. 2013  
15  
Symbol  
IDD3P  
Description  
Active Power-Down Current  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,  
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks open;  
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0  
Operating Burst Read Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,  
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst  
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank  
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer  
IDD4R  
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.  
Operating Burst Write Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,  
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst  
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank  
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-  
IDD4W  
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.  
Burst Refresh Current  
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-  
mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID-LEVEL; DM:  
stable at 0; Bank Activity: REF command every nREC (see Table 9); Output Buffer and RTT: Enabled in  
IDD5B  
Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.  
Self-Refresh Current: Normal Temperature Range  
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);  
IDD6  
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,  
Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-  
put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL  
Self-Refresh Current: Extended Temperature Range  
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-  
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,  
Address, Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-  
IDD6ET  
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-  
LEVEL  
Rev. 1.8 /June. 2013  
16  
Symbol  
Description  
Operating Bank Interleave Read Current  
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1;  
CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according  
to Table 10; Data IO: read data burst with different data between one burst and the next one according  
to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with  
IDD7  
different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:  
stable at 0; Pattern Details: see Table 10.  
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B  
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;  
RTT_Wr enable: set MR2 A[10,9] = 10B  
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit  
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature  
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range  
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B  
Rev. 1.8 /June. 2013  
17  
Table 3 - IDD0 Measurement-Loop Patterna)  
Datab)  
0
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2  
3,4  
...  
repeat pattern 1...4 until nRAS - 1, truncate if necessary  
nRAS  
PRE  
0
0
1
0
0
0
00  
0
0
0
0
-
...  
repeat pattern 1...4 until nRC - 1, truncate if necessary  
1*nRC+0  
1*nRC+1, 2  
1*nRC+3, 4  
...  
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC+1...4 until 1*nRC + nRAS - 1, truncate if necessary  
PRE 00  
1*nRC+nRAS  
...  
0
0
1
0
0
0
0
0
F
0
-
repeat pattern nRC+1...4 until 2*nRC - 1, truncate if necessary  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
1
2
3
4
5
6
7
2*nRC  
4*nRC  
6*nRC  
8*nRC  
10*nRC  
12*nRC  
14*nRC  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
18  
Table 4 - IDD1 Measurement-Loop Patterna)  
Datab)  
0
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2  
3,4  
...  
repeat pattern 1...4 until nRCD - 1, truncate if necessary  
RD 00  
repeat pattern 1...4 until nRAS - 1, truncate if necessary  
nRCD  
...  
0
1
0
1
0
0
0
0
0
0
0
0
00000000  
-
nRAS  
PRE  
0
0
1
0
0
0
00  
0
0
...  
repeat pattern 1...4 until nRC - 1, truncate if necessary  
1*nRC+0  
1*nRC+1,2  
1*nRC+3,4  
...  
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCD - 1, truncate if necessary  
RD 00  
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary  
PRE 00  
1*nRC+nRCD  
...  
0
1
0
1
0
0
0
0
F
0
00110011  
-
1*nRC+nRAS  
...  
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until 2* nRC - 1, truncate if necessary  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
1
2
3
4
5
6
7
2*nRC  
4*nRC  
6*nRC  
8*nRC  
10*nRC  
12*nRC  
14*nRC  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
19  
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)  
Datab)  
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
8-11  
12-15  
16-19  
20-23  
24-27  
28-31  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)  
Datab)  
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
0
1
0
0
0
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7  
8-11  
12-15  
16-19  
20-23  
24-27  
28-31  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
20  
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)  
Datab)  
0
RD  
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000  
0
1
-
2,3  
D,D  
RD  
D
-
4
00110011  
5
-
-
6,7  
D,D  
1
2
3
4
5
6
7
8-15  
16-23  
24-31  
32-39  
40-47  
48-55  
56-63  
repeat Sub-Loop 0, but BA[2:0] = 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 0, but BA[2:0] = 3  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 0, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 0, but BA[2:0] = 7  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
21  
Table 8 - IDD4W Measurement-Loop Patterna)  
Datab)  
0
WR  
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000  
0
1
-
2,3  
D,D  
WR  
D
-
4
00110011  
5
-
-
6,7  
D,D  
1
2
3
4
5
6
7
8-15  
16-23  
24-31  
32-39  
40-47  
48-55  
56-63  
repeat Sub-Loop 0, but BA[2:0] = 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 0, but BA[2:0] = 3  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 0, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 0, but BA[2:0] = 7  
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.  
Table 9 - IDD5B Measurement-Loop Patterna)  
Datab)  
0
1
REF  
D, D  
D, D  
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
0
1.2  
00  
00  
3,4  
5...8  
repeat cycles 1...4, but BA[2:0] = 1  
repeat cycles 1...4, but BA[2:0] = 2  
repeat cycles 1...4, but BA[2:0] = 3  
repeat cycles 1...4, but BA[2:0] = 4  
repeat cycles 1...4, but BA[2:0] = 5  
repeat cycles 1...4, but BA[2:0] = 6  
repeat cycles 1...4, but BA[2:0] = 7  
9...12  
13...16  
17...20  
21...24  
25...28  
29...32  
33...nRFC-1  
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
22  
Table 10 - IDD7 Measurement-Loop Patterna)  
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9  
Datab)  
0
1
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00  
00  
00  
0
1
0
0
0
0
0
0
0
0
0
0
-
0
1
2
...  
00000000  
-
repeat above D Command until nRRD - 1  
nRRD  
nRRD+1  
nRRD+2  
...  
2*nRRD  
3*nRRD  
4*nRRD  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00  
00  
00  
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011  
-
repeat above D Command until 2* nRRD - 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 1, but BA[2:0] = 3  
2
3
D
1
0
0
0
0
3
00  
0
0
F
0
-
4
Assert and repeat above D Command until nFAW - 1, if necessary  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 1, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 1, but BA[2:0] = 7  
5
6
7
8
nFAW  
nFAW+nRRD  
nFAW+2*nRRD  
nFAW+3*nRRD  
nFAW+4*nRRD  
D
1
0
0
0
0
7
00  
0
0
F
0
-
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary  
2*nFAW+0  
2*nFAW+1  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00  
00  
00  
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011  
-
10  
2*nFAW+2  
Repeat above D Command until 2* nFAW + nRRD - 1  
2*nFAW+nRRD  
2*nFAW+nRRD+1 RDA  
ACT  
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00  
00  
00  
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000  
-
11  
D
2*nFAW+nRRD+2  
Repeat above D Command until 2* nFAW + 2* nRRD - 1  
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2  
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3  
D
1
0
0
0
0
3
00  
0
0
0
0
-
14 2*nFAW+4*nRRD  
Assert and repeat above D Command until 3* nFAW - 1, if necessary  
repeat Sub-Loop 10, but BA[2:0] = 4  
15 3*nFAW  
16 3*nFAW+nRRD  
repeat Sub-Loop 11, but BA[2:0] = 5  
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6  
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7  
D
1
0
0
0
0
7
00  
0
0
0
0
-
19 3*nFAW+4*nRRD  
Assert and repeat above D Command until 4* nFAW - 1, if necessary  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.  
Rev. 1.8 /June. 2013  
23  
IDD Specifications  
IDD values are for full operating range of voltage and temperature unless otherwise noted.  
IDD Specification  
Speed Grade DDR3 - 1066 DDR3 - 1333 DDR3 - 1600 DDR3 - 1866 DDR3 - 2133  
Bin  
Symbol  
IDD0  
7-7-7  
Max.  
45  
55  
50  
9-9-9  
Max.  
45  
58  
55  
11-11-11  
13-13-13  
Max.  
55  
14-14-14  
Max.  
65  
Unit  
Notes  
Max.  
50  
60  
60  
70  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
x8  
x16  
x8  
x16  
x8/x16  
x8  
65  
65  
75  
30  
40  
40  
10  
20  
75  
75  
85  
30  
40  
40  
10  
20  
IDD1  
65  
30  
68  
30  
IDD2N  
30  
IDD2NT  
30  
30  
35  
x16  
IDD2P0  
IDD2P1  
IDD2Q  
10  
20  
30  
10  
20  
30  
10  
20  
30  
x8/x16  
x8/x16  
x8/x16  
x8/x16  
x8/x16  
x8  
x16  
x8  
x16  
x8  
30  
35  
45  
45  
45  
45  
50  
I
DD3N  
IDD3P  
25  
80  
25  
90  
25  
25  
30  
105  
160  
105  
160  
120  
150  
10  
12  
12  
6
150  
210  
130  
175  
130  
175  
125  
155  
10  
12  
12  
6
190  
230  
140  
185  
140  
185  
135  
165  
10  
12  
12  
6
210  
250  
IDD4R  
130  
80  
130  
110  
120  
10  
12  
12  
6
130  
180  
140  
90  
140  
115  
130  
10  
12  
12  
6
140  
200  
IDD4W  
IDD5B  
IDD6  
IDD6ET  
x16  
x8/x16  
x8/x16  
x8/x16  
x8/x16  
x8  
IDD6TC  
IDD6 Low Power  
IDD7  
x16  
Notes:  
1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC.  
2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC.  
Rev. 1.8 /June. 2013  
24  
Input/Output Capacitance  
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133  
Min Max Min Max Min Max Min Max Min Max  
Parameter  
Symbol  
Units Notes  
Input/output capacitance  
(DQ, DM, DQS, DQS,  
TDQS, TDQS)  
CIO  
1.5  
2.7  
1.5  
2.5  
1.5  
2.3  
1.4  
2.2  
1.4  
2.1  
pF  
1,2,3  
Input capacitance, CK  
and CK  
Input capacitance delta  
CK and CK  
Input capacitance delta,  
DQS and DQS  
Input capacitance  
CCK  
CDCK  
CDDQS  
CI  
0.8  
0
1.6  
0.8  
0
1.4  
0.8  
0
1.4  
0.8  
0
1.3  
0.8  
0
1.3  
pF  
pF  
pF  
pF  
2,3  
0.15  
0.20  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
2,3,4  
2,3,5  
2,3,6  
0
0
0
0
0
0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2  
(All other input-only pins)  
Input capacitance delta CDI_CTR  
-0.5  
-0.5  
0.3 -0.4  
0.5 -0.4  
0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2  
0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4  
pF 2,3,7,8  
pF 2,3,9,10  
(All CTRL input-only pins)  
L
Input capacitance delta  
(All ADD/CMD input-only  
pins)  
CDI_ADD  
_CMD  
Input/output capacitance  
delta  
(DQ, DM, DQS, DQS)  
Input/output capacitance  
of ZQ pin  
CDIO  
-0.5  
-
0.3 -0.5  
0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3  
pF  
pF  
2,3,11  
2,3,12  
CZQ  
3
-
3
-
3
-
3
-
3
Notes:  
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.  
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is  
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK   
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,   
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.  
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here  
4. Absolute value of CCK-CCK.  
5. Absolute value of CIO(DQS)-CIO(DQS).  
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.  
7. CDI_CTR applies to ODT, CS and CKE.  
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))  
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.  
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))  
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))  
12. Maximum external load capacitance an ZQ pin: 5 pF.  
Rev. 1.8 /June. 2013  
25  
Standard Speed Bins  
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.  
DDR3-1066 Speed Bins  
For specific Notes see “Speed Bin Table Notes” on page 31.  
Speed Bin  
DDR3-1066  
7-7-7  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
Internal read command to first  
data  
tAA  
13.125  
13.125  
13.125  
50.625  
20  
ns  
ns  
ns  
ns  
ACT to internal read or write  
delay time  
tRCD  
tRP  
PRE command period  
ACT to ACT or REF command  
period  
tRC  
tRAS  
ACT to PRE command period  
37.5  
3.0  
9 * tREFI  
3.3  
ns  
ns  
1,2,3,4,6,  
tCK(AVG)  
CWL = 5  
CL = 5  
10,11  
4
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 6  
Reserved  
ns  
ns  
CWL = 5  
CL = 6  
2.5  
3.3  
1,2,3,6  
1,2,3,4  
4
CWL = 6  
Reserved  
Reserved  
ns  
CWL = 5  
CL = 7  
ns  
CWL = 6  
1.875  
1.875  
< 2.5  
< 2.5  
ns  
1,2,3,4  
4
CWL = 5  
CL = 8  
Reserved  
ns  
CWL = 6  
ns  
1,2,3  
13  
nCK  
nCK  
Supported CL Settings  
5, 6, 7, 8  
5, 6  
Supported CWL Settings  
Rev. 1.8 /June. 2013  
26  
DDR3-1333 Speed Bins  
For specific Notes see “Speed Bin Table Notes” on page 31.  
Speed Bin  
DDR3-1333  
9-9-9  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
Internal read command to first  
data  
tAA  
13.5  
20  
ns  
ns  
ns  
ns  
ACT to internal read or write  
delay time  
tRCD  
13.5  
13.5  
49.5  
tRP  
PRE command period  
ACT to ACT or REF command  
period  
tRC  
tRAS  
ACT to PRE command period  
36  
9 * tREFI  
3.3  
ns  
ns  
1,2,3,4,7,  
tCK(AVG)  
CWL = 5  
CL = 5  
3.0  
10,11  
4
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 6, 7  
Reserved  
ns  
ns  
ns  
ns  
ns  
CWL = 5  
2.5  
3.3  
1,2,3,7  
CL = 6  
CL = 7  
CL = 8  
CWL = 6  
CWL = 7  
CWL = 5  
Reserved  
Reserved  
Reserved  
1,2,3,4,7  
4
4
1.875  
< 2.5  
tCK(AVG)  
CWL = 6  
ns  
1,2,3,4,7  
(Optional)  
Note 5,11  
Reserved  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 7  
CWL = 5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4  
4
Reserved  
CWL = 6  
1.875  
< 2.5  
1,2,3,7  
1,2,3,4  
4
CWL = 7  
Reserved  
Reserved  
CWL = 5, 6  
CWL = 7  
CL = 9  
1.5  
1.5  
<1.875  
<1.875  
1,2,3,4  
4
CWL = 5, 6  
Reserved  
(Optional)  
CL = 10  
ns  
ns  
1,2,3  
5
tCK(AVG)  
CWL = 7  
nCK  
Supported CL Settings  
Supported CWL Settings  
5,6,(7),9,(10)  
5, 6, 7  
nCK  
Rev. 1.8 /June. 2013  
27  
DDR3-1600 Speed Bins  
For specific Notes see “Speed Bin Table Notes” on page 31.  
Speed Bin  
DDR3-1600  
11-11-11  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
Internal read command to first  
data  
ACT to internal read or write  
delay time  
tAA  
13.75  
20  
ns  
ns  
ns  
ns  
ns  
ns  
tRCD  
tRP  
13.75  
13.75  
48.75  
35  
PRE command period  
ACT to ACT or REF command  
period  
tRC  
tRAS  
ACT to PRE command period  
9 * tREFI  
3.3  
1,2,3,4,8,  
tCK(AVG)  
CWL = 5  
CL = 5  
3.0  
10,11  
4
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 6, 7, 8  
Reserved  
ns  
ns  
ns  
ns  
ns  
CWL = 5  
2.5  
3.3  
1,2,3,8  
CL = 6  
CL = 7  
CWL = 6  
CWL = 7, 8  
CWL = 5  
Reserved  
Reserved  
Reserved  
1,2,3,4,8  
4
4
1.875  
< 2.5  
tCK(AVG)  
(Optional)  
CWL = 6  
ns  
1,2,3,4,8  
Note 5,11  
Reserved  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 7  
CWL = 8  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8  
CWL = 5, 6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4,8  
4
4
Reserved  
Reserved  
1.875  
1.5  
< 2.5  
1,2,3,8  
1,2,3,4,8  
1,2,3,4  
4
CL = 8  
CL = 9  
Reserved  
Reserved  
Reserved  
<1.875  
tCK(AVG)  
(Optional)  
CWL = 7  
ns  
1,2,3,4,8  
Note 5,11  
Reserved  
Reserved  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 8  
CWL = 5, 6  
CWL = 7  
ns  
ns  
ns  
ns  
ns  
1,2,3,4  
4
CL = 10  
CL = 11  
1.5  
<1.875  
<1.5  
1,2,3,8  
1,2,3,4  
4
CWL = 8  
Reserved  
Reserved  
CWL = 5, 6,7  
tCK(AVG)  
CWL = 8  
1.25  
ns  
1,2,3  
nCK  
nCK  
Supported CL Settings  
Supported CWL Settings  
5,6,(7),8,(9),10,11  
5, 6, 7, 8  
Rev. 1.8 /June. 2013  
28  
DDR3-1866 Speed Bins  
For specific Notes see “Speed Bin Table Notes” on page 31.  
Speed Bin  
DDR3-1866  
13-13-13  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
13.91(13.125)  
Internal read command to  
first data  
tAA  
20  
ns  
(Optional Note 5,11)  
Note 5,  
13.91(13.125)  
(Optional Note 5,11)  
ACT to internal read or write  
delay time  
tRCD  
tRP  
tRAS  
tRC  
ns  
ns  
ns  
ns  
13.91(13.125)  
(Optional Note 5,11)  
PRE command period  
ACT to PRE command  
period  
34  
9 * tREFI  
-
47.91(47.125)  
(Optional Note 5,11)  
ACT to ACT or PRE  
command period  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CL = 5  
Reserved  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4, 9  
CWL = 6,7,8,9  
Reserved  
4
CWL = 5  
2.5  
3.3  
1, 2, 3, 9  
1, 2, 3, 4, 9  
4
CL = 6  
CL = 7  
CWL = 6  
CWL = 7,8,9  
CWL = 5  
Reserved  
Reserved  
Reserved  
4
1, 2, 3, 4,  
9,11  
tCK(AVG)  
CWL = 6  
1.875 (Optional)  
1.875  
< 2.5 (Optional)  
< 2.5  
ns  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 7,8,9  
CWL = 5  
Reserved  
Reserved  
ns  
ns  
ns  
ns  
ns  
ns  
4
4
CWL = 6  
1, 2, 3, 9  
1, 2, 3, 4, 9  
4
CL = 8  
CL = 9  
CWL = 7  
Reserved  
Reserved  
Reserved  
CWL = 8,9  
CWL = 5, 6  
4
1, 2, 3, 4,  
9,11  
1, 2, 3, 4, 9  
tCK(AVG)  
CWL = 7  
1.5 (Optional)  
<1.875 (Optional)  
ns  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
Reserved  
Reserved  
Reserved  
CWL = 8  
CWL = 9  
ns  
ns  
ns  
ns  
ns  
ns  
4
CWL = 5, 6  
CWL = 7  
4
CL = 10  
CL = 11  
1.5  
<1.875  
1, 2, 3, 9  
1, 2, 3, 4, 9  
Reserved  
CWL = 8  
CWL = 5,6,7  
Reserved  
4
1, 2, 3, 4,  
9,11  
tCK(AVG)  
CWL = 8  
1.25 (Optional)  
<1.5 (Optional)  
ns  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 9  
CWL = 5,6,7,8  
CWL = 9  
Reserved  
Reserved  
Reserved  
Reserved  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4  
4
CL = 12  
CL = 13  
1,2,3,4  
4
CWL = 5,6,7,8  
CWL = 9  
1.07  
<1.25  
1, 2, 3  
Rev. 1.8 /June. 2013  
29  
nCK  
nCK  
Supported CL Settings  
Supported CWL Settings  
6, (7), 8, (9), 10, (11), 13  
5, 6, 7, 8, 9  
DDR3-2133 Speed Bins  
For specific Notes see “Speed Bin Table Notes” on page 31.  
Speed Bin  
DDR3-2133  
14-14-14  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
Internal read command to  
first data  
ACT to internal read or write  
tAA  
13.09  
20.0  
ns  
ns  
tRCD  
13.09  
delay time  
tRP  
tRAS  
PRE command period  
ACT to PRE command period  
ACT to ACT or PRE  
command period  
13.09  
33.0  
ns  
ns  
9 * tREFI  
tRC  
46.09  
-
ns  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CWL = 6,7,8,9,10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4, 10  
Reserved  
Reserved  
CL = 5  
4
CWL = 5  
2.5  
3.3  
1, 2, 3, 10  
1, 2, 3, 4, 10  
CL = 6  
CL = 7  
CWL = 6  
CWL = 7,8,910  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8,9,10  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8,9,10  
CWL = 5, 6  
CWL = 7  
Reserved  
Reserved  
Reserved  
4
4
1.875  
1.875  
1.5  
< 2.5  
1, 2, 3, 10  
1, 2, 3, 4, 10  
Reserved  
Reserved  
Reserved  
4
4
< 2.5  
1, 2, 3, 10  
1, 2, 3, 4, 10  
CL = 8  
CL = 9  
Reserved  
Reserved  
Reserved  
4
4
<1.875  
<1.875  
1, 2, 3, 10  
1, 2, 3, 4, 10  
CWL = 8  
Reserved  
Reserved  
Reserved  
CWL = 9,10  
CWL = 5, 6  
CWL = 7  
CWL = 8  
CWL = 9  
CWL = 10  
CWL = 5,6,7  
CWL = 8  
4
4
1.5  
1, 2, 3, 9  
1, 2, 3, 4, 9  
CL = 10  
Reserved  
Reserved  
Reserved  
Reserved  
4
4
4
1.25  
1.07  
<1.5  
1, 2, 3, 10  
1, 2, 3, 4, 10  
1, 2, 3, 4  
4
1,2,3,4, 10  
4
CL = 11  
CL = 12  
CWL = 9  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
CWL = 10  
CWL = 5,6,7,8  
CWL = 9  
CWL = 10  
CWL = 5,6,7,8  
CWL = 9  
4
Reserved  
CL = 13  
<1.25  
1, 2, 3, 10  
1, 2, 3, 4  
CWL = 10  
Reserved  
Rev. 1.8 /June. 2013  
30  
tCK(AVG)  
tCK(AVG)  
CWL = 5,6,7,8,9  
CWL = 10  
ns  
ns  
4
Reserved  
CL = 14  
0.935  
<1.07  
1, 2, 3  
nCK  
nCK  
Supported CL Settings  
Supported CWL Settings  
5, 6, 7, 8, 9, 10, 11, 12, 13, 14  
5, 6, 7, 8, 9, 10  
Speed Bin Table Notes  
Absolute Specification (T  
; V  
= V = 1.5V +/- 0.075 V);  
OPER  
DDQ DD  
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-  
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-  
ments from CWL setting.  
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-  
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should  
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-  
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL, where tCK(AVG) =  
3.0 ns should only be used for CL = 5 calculation.  
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)  
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is  
tCK(AVG).MAX corresponding to CL SELECTED.  
4. ‘Reserved’ settings are not allowed. User must program a different value.  
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-  
datory feature. Refer to Hynix DIMM data sheet and/or the DIMM SPD information if and how this set-  
ting is supported.  
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
10. Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
11. Hynix DDR3 SDRAM devices supporting optional down binning to CL=7, 9 and CL=11, and tAA/tRCD/  
tRP must be 13.125 ns. SPD settings must be programmed to match. For example, DDR3-1866 RD  
devices supporting down binning to DDR3-1600K or DDR3-1333 H9 or 1066 G7 should program  
13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP  
(Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly.  
For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333 H9 and 48.125ns  
(tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600 PB.  
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-  
tory in SPD coding.  
Rev. 1.8 /June. 2013  
31  
Package Dimensions  
Package Dimension(x8): 78Ball Fine Pitch Ball Grid Array Outline  
7.5000.100  
A1 CORNER  
INDEX AREA  
(1.875)  
1.1000.100  
0.3400.050  
3.0 X 5.0 MIN  
FLAT AREA  
TOP  
SIDE  
0.800 X 8 = 6.400  
2.1000.100  
0.800  
0.5500.100  
A1 BALL MARK  
9
8
7
3
2
1
A
B
C
D
E
F
2-R0.130 MAX  
G
H
J
K
L
M
N
78x0.4500.050  
1.600 1.600  
BOTTOM  
Rev. 1.8 /June. 2013  
32  
Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline  
7.5000.100  
A1 CORNER  
INDEX AREA  
(1.875)  
1.1000.100  
0.3400.050  
3.0 X 5.0 MIN  
FLAT AREA  
TOP  
0.800 X 8 = 6.400  
SIDE  
2.1000.100  
0.800  
0.5500.100  
A1 BALL MARK  
9
8
7
3
2
1
A
B
C
D
E
F
2-R0.130 MAX  
G
H
J
K
L
M
N
P
R
T
96x0.4500.050  
1.600 1.600  
BOTTOM  
Rev. 1.8 /June. 2013  
33  
配单直通车
H5TQ1G63DFR-PBC产品参数
型号:H5TQ1G63DFR-PBC
是否Rohs认证: 符合
生命周期:Obsolete
零件包装代码:BGA
包装说明:TFBGA, BGA96,9X16,32
针数:96
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.32.00.32
风险等级:5.79
访问模式:MULTI BANK PAGE BURST
其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):800 MHz
I/O 类型:COMMON
交错的突发长度:4,8
JESD-30 代码:R-PBGA-B96
JESD-609代码:e1
长度:13 mm
内存密度:1073741824 bit
内存集成电路类型:DDR DRAM
内存宽度:16
功能数量:1
端口数量:1
端子数量:96
字数:67108864 words
字数代码:64000000
工作模式:SYNCHRONOUS
最高工作温度:85 °C
最低工作温度:
组织:64MX16
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA
封装等效代码:BGA96,9X16,32
封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260
电源:1.5 V
认证状态:Not Qualified
刷新周期:8192
座面最大高度:1.2 mm
自我刷新:YES
连续突发长度:4,8
最大待机电流:0.01 A
子类别:DRAMs
最大压摆率:0.21 mA
最大供电电压 (Vsup):1.575 V
最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V
表面贴装:YES
技术:CMOS
温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL
端子节距:0.8 mm
端子位置:BOTTOM
处于峰值回流温度下的最长时间:20
宽度:7.5 mm
Base Number Matches:1
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