HA5023
traces connected to -IN, and that connections to -IN be kept
as short as possible to minimize the capacitance from this
node to ground.
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 8 and Figure 9 in the typical performance section,
illustrate the performance of the HA5023 in various closed
loop gain configurations. Although the bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
amplifier’s unique relationship between bandwidth and R .
All current feedback amplifiers require a feedback resistor,
100Ω
F
R
V
+
-
IN
V
OUT
even for unity gain applications, and R , in conjunction with
F
R
T
C
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
L
R
F
R
I
inversely proportional to R . The HA5023 design is
F
optimized for a 1000Ω R at a gain of +1. Decreasing R in
a unity gain application decreases stability, resulting in
excessive peaking and overshoot. At higher gains the
F
F
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
amplifier is more stable, so R can be decreased in a trade-
off of stability for bandwidth.
F
The selection criteria for the isolation resistor is highly
dependent on the load, but 27Ω has been determined to be
a good starting value.
The table below lists recommended R values for various
F
gains, and the expected bandwidth.
Power Dissipation Considerations
Due to the high supply current inherent in dual amplifiers, care
must be taken to insure that the maximum junction
GAIN
(A
BANDWIDTH
(MHz)
)
R (Ω)
F
CL
-1
+1
750
1000
681
100
125
95
temperature (T , see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient temperature
versus supply voltage for the available package styles (Plastic
J
+2
DIP, SOIC). At ±5V
quiescent operation both package
DC
o
+5
1000
383
52
styles may be operated over the full industrial range of -40 C
o
to 85 C. It is recommended that thermal calculations, which
+10
-10
65
take into account output power, be performed by the designer.
750
22
140
130
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
120
110
100
90
PDIP
SOIC
80
70
60
50
Attention must be given to decoupling the power supplies. A
large value (10µF) tantalum or electrolytic capacitor in
parallel with a small value (0.1µF) chip capacitor works well
in most cases.
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
vs SUPPLY VOLTAGE
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is
recommended that the ground plane be removed under
7