HCPL-263L应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>H字母起始型号索引_>H字母起始型号索引第344页更新时间：2024-10-23 17:06:04

产品型号HCPL-263L的概述

HCPL-263L 芯片概述 HCPL-263L 是一款由安费诺（Avago Technologies）设计和制造的光耦合器，也称为光隔离器。这种芯片主要用于信号隔离、数据传输、开关电源以及其他需要电气隔离的应用。HCPL-263L 提供了优良的电气隔离性能，有助于提高系统的可靠性和安全性。它的核心特点是通过光耦合技术实现输入和输出之间的电气隔离，同时允许信号的高效传递。其内部结构通常包括一个发光二极管（LED）和一个光敏接收器，二者通过一个绝缘层分隔，确保信号在传输过程中不会受到干扰。 HCPL-263L 的详细参数 HCPL-263L 的主要参数如下： - 输入电压：通常可以承受 5V 至 15V 的输入电压范围。 - 输出电流：最大输出电流可达 20 mA。 - 工作温度：-55°C 到 +100°C 的工作温度范围。 - 隔离电压：常见的电气隔离电压高达 5000 VRMS。 ...

产品型号HCPL-263L的Datasheet PDF文件预览

Agilent HCPL-260L/ 060L/263L/063L

High Speed LVTTL Compatible

3.3 Volt Optocouplers

Data Sheet

Features

•

Low power consumption

•

15 kV/µs minimum Common Mode

Rejection (CMR) at V_CM= 50 V

•

High speed: 15 MBd typical

LVTTL/LVCMOS compatible

Low input current capability:

5 mA

Description

•

Guaranteed AC and DC performance

over temperature: –40˚C to +85˚C

The HCPL-260L/060L/263L/063L

are optically coupled gates that

combine a GaAsP light emitting

diode and an integrated high gain

photo detector. An enable input

allows the detector to be strobed.

The output of the detector IC is an

open collector Schottky-clamped

transistor. The internal shield

provides a guaranteed common

mode transient immunity

This unique design provides

maximum AC and DC circuit

isolation while achieving

LVTTL/LVCMOS compatibility.

The optocoupler AC and DC

operational parameters are

guaranteed from –40˚C to +85˚C

allowing trouble-free system

performance.

•

Available in 8-pin DIP, SOIC-8

Strobable output (single channel

products only)

•

Safety approvals; UL, CSA, VDE

(pending)

Applications

•

Isolated line receiver

specification of 15 kV/µs.

Computer-peripheral interfaces

Microprocessor system interfaces

Functional Diagram

Digital isolation for A/D, D/A

conversion

HCPL-260L/060L

HCPL-263L/063L

ANODE

CATHODE

ANODE

•

Switching power supply

Instrument input/output isolation

Ground loop elimination

Pulse transformer replacement

Field buses

ANODE

CATHODE

GND

SHIELD

TRUTH TABLE

(POSITIVE LOGIC)

TRUTH TABLE

(POSITIVE LOGIC)

LED ENABLE OUTPUT

LED OUTPUT

OFF

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent

damage and/or degradation which may be induced by ESD.

6－104

These optocouplers are suitable

for high speed logic interfacing,

input/output buffering, as line

receivers in environments that

conventional line receivers

cannot tolerate and are

recommended for use in

extremely high ground or induced

noise environments.

Ordering Information

Specify Part Number followed by Option Number (if desired).

Example:

HCPL-260L #XXX

060 = VDE 0884 V_IORM= 630 Vpeak Option

500 = Tape and Reel Packaging Option

Option data sheets available. Contact Agilent sales representative or

authorized distributor for information.

These optocouplers are available

in an 8-pin DIP and industry

standard SO-8 package. The part

numbers are as follows:

8-pin DIP

HCPL-260L

HCPL-263L

SO-8 Package

HCPL-060L

HCPL-063L

Schematic

HCPL-260L/060L

HCPL-263L/063L

–

GND

SHIELD

–

USE OF A 0.1 F BYPASS CAPACITOR CONNECTED

BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).

GND

SHIELD

6－105

Package Outline Drawings

8-Pin DIP Package

7.62 0.25

(0.300 0.010)

9.65 0.25

(0.380 0.010)

6.35 0.25

(0.250 0.010)

TYPE NUMBER

OPTION CODE*

DATE CODE

A XXXXZ

YYWW

U R

RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076

- 0.051

0.254

5° TYP.

+ 0.003)

- 0.002)

(0.010

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

1.080 0.320

(0.043 0.013)

0.65 (0.025) MAX.

*MARKING CODE LETTER FOR OPTION NUMBERS

"L" = OPTION 020

"V" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

2.54 0.25

(0.100 0.010)

6－106

Small Outline SO-8 Package

5.994 0.203

(0.236 0.008)

XXX

YWW

3.937 0.127

(0.155 0.005)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

PIN ONE

0.406 0.076

(0.016 0.003)

1.270

(0.050)

BSG

0.432

(0.017)

7°

5.080 0.127

(0.200 0.005)

45° X

3.175 0.127

(0.125 0.005)

0 ~ 7°

0.228 0.025

(0.009 0.001)

1.524

(0.060)

0.203 0.102

(0.008 0.004)

TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

5.207 0.254 (0.205 0.010)

0.305

(0.012)

MIN.

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

Solder Reflow Temperature Profile

(Surface Mount Option Parts)

Regulatory Information

The HCPL-260L/060L/263L/063L

are pending by the following

organizations:

260

240

220

∆T = 145°C, 1°C/SEC

∆T = 115°C, 0.3°C/SEC

200

180

160

140

120

100

Approval (pending) under UL

1577, Component Recognition

Program, File E55361.

∆T = 100°C, 1.5°C/SEC

CSA

Approval (pending) under CSA

Component Acceptance Notice

#5, File CA 88324.

TIME – MINUTES

VDE

NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS HIGHLY RECOMMENDED.

Approval (pending) according to

VDE 0884/06.92.

6－107

Insulation and Safety Related Specifications

8-Pin DIP

(300 Mil)

Value

SO-8

Parameter

Symbol

Value Units Conditions

Minimum External Air

Gap (External Clearance)

Minimum External Tracking L (102)

(External Creepage)

Minimum Internal Plastic

Gap (Internal Clearance)

L (101)

7.1

4.9

Measured from input terminals to output

terminals, shortest distance through air.

Measured from input terminals to output

7.4

4.8

terminals, shortest distance path along body.

0.08

Through insulation distance, conductor to

conductor, usually the direct distance

between the photoemitter and photodetector

inside the optocoupler cavity.

Minimum Internal Tracking

(Internal Creepage)

Tracking Resistance

(Comparative Tracking

Index)

200

Measured from input terminals to output

terminals, along internal cavity.

DIN IEC 112/VDE 0303 Part 1

CTI

Volts

Isolation Group

IIIa

Material Group (DIN VDE 0110, 1/89, Table 1)

VDE 0884 Insulation Related Characteristics

Description

Symbol

Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 V rms

I-IV

I-III

for rated mains voltage ≤ 450 V rms

Climatic Classification

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

V_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

Partial Discharge < 5 pC

55/85/21

630

V_IORM

V_PR

V_peak

1181

Input to Output Test Voltage, Method a*

V_IORMx 1.5 = V_PR, Type and Sample Test,

t_m= 60 sec, Partial Discharge < 5 pC

V_PR

945

V_peak

Highest Allowable Overvoltage*

V_IOTM

6000

(Transient Overvoltage, t_ini= 10 sec)

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Figure 16, Thermal Derating curve.)

Case Temperature

Input Current

Output Power

Insulation Resistance at T_S, V_IO= 500 V

T_S

175

230

600

˚C

I_S,INPUT

P_S,OUTPUT

R_S

≥ 10

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

6－108

Absolute Maximum Ratings (No Derating Required up to 85˚C)

Parameter

Symbol

Package**

Min.

–55

–40

Max.

125

Units

˚C

Note

Storage Temperature

Operating Temperature†

Average Forward Input Current

T_S

T_A

I_F

Single 8-Pin DIP

Single SO-8

Dual 8-Pin DIP

Dual SO-8

8-Pin DIP, SO-8

1, 3

Reverse Input Voltage

V_R

Input Power Dissipation

Supply Voltage (1 Minute Maximum)

Enable Input Voltage (Not to Exceed

V_CCby more than 500 mV)

P_I

V_CC

V_E

V_CC+ 0.5

Single 8-Pin DIP

Single SO-8

Enable Input Current

I_E

I_O

V_O

P_O

Output Collector Current

Output Collector Voltage

Output Collector Power Dissipation

Single 8-Pin DIP

Single SO-8

Dual 8-Pin DIP

Dual SO-8

1, 4

Lead Solder Temperature

(Through Hole Parts Only)

T_LS

8-Pin DIP

260˚C for 10 sec., 1.6 mm below

seating plane

260˚C for 10 sec., up to seating

plane

Solder Reflow Temperature Profile

(Surface Mount Parts Only)

SO-8

See Package Outline Drawings

section

**Ratings apply to all devices except otherwise noted in the Package column.

Recommended Operating Conditions

Parameter

Symbol

I_FL*

I_FH**

V_CC

V_EL

V_EH

T_A

Min.

2.7

2.0

–40

Max.

250

3.3

0.8

V_CC

Units

µA

Input Current, Low Level

Input Current, High Level^[1]

Power Supply Voltage

Low Level Enable Voltage

High Level Enable Voltage

Operating Temperature

Fan Out (at R_L= 1 kΩ)^[1]

Output Pull-up Resistor

˚C

4 k

TTL Loads

Ω

R_L

330

*The off condition can also be guaranteed by ensuring that V ≤ 0.8 volts.

**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used

for best performance and to permit at least a 20% LED degradation guardband.

6－109

Electrical Specifications

Over Recommended Temperature (T_A= –40˚C to +85˚C) unless otherwise specified. All Typicals at V_CC= 3.3 V,

T_A= 25˚C. All enable test conditions apply to single channel products only. See Note 5.

Parameter

High Level Output Current

Sym.

I_OH

Min. Typ.

Max. Units Test Conditions

Fig.

Note

1, 15

4.5

µA

V_CC= 3.3 V, V_E= 2.0 V,

V_O= 3.3 V, I_F= 250 µA

Input Threshold Current

Low Level Output Voltage

I_TH

3.0

5.0

V_CC= 3.3 V, V_E= 2.0 V,

V_O= 0.6 V,

I_OL(Sinking) = 13 mA

V_CC= 3.3 V, V_E= 2.0 V,

I_F= 5 mA,

V_OL

0.35

0.6

_OL(Sinking) = 13 mA

High Level Supply Current

Low Level Supply Current

I_CCH

I_CCL

4.7

7.0

V_E= 0.5 V V_CC= 3.3 V

I_F= 0 mA

V_E= 0.5 V V_CC= 3.3 V

I_F= 10 mA

10.0

High Level Enable Current

Low Level Enable Current

High Level Enable Voltage

Low Level Enable Voltage

Input Forward Voltage

I_EH

–0.5

–1.2

V_CC= 3.3 V, V_E= 2.0 V

V_CC= 3.3 V, V_E= 0.5 V

I_EL*

V_EH

V_EL

V_F

2.0

0.8

1.75*

1.4

1.5

T_A= 25˚C I_F= 10 mA

I_R= 10 µA

Input Reverse Breakdown

Voltage

BV_R*

Input Diode Temperature

Coefficient

∆V_F/

∆T_A

–1.6

mV˚C I_F= 10 mA

–1.9

Input Capacitance

C_IN

f = 1 MHz, V_F= 0 V

*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.

6－110

Switching Specifications

Over Recommended Temperature (T_A= –40˚C to +85˚C), V_CC= 3.3 V, I_F= 7.5 mA unless otherwise specified. All Typicals

at T_A= 25˚C, V_CC= 3.3 V.

Parameter

Sym.

Package** Min. Typ. Max. Units Test Conditions

Fig.

Note

Propagation Delay

Time to High Output

Level

t_PLH

T_A= 25˚C

R_L= 350 Ω 6, 7, 8 1, 6, 15

C_L= 15 pF

Propagation Delay

Time to Low Output

Level

t_PHL

1, 7, 15

Pulse Width

Distortion

Propagation Delay

Skew

Output Rise Time

(10-90%)

Output Fall Time

(90-10%)

|t_PHL– t_PLH| 8-Pin DIP

9, 15

8, 9, 15

1, 15

SO-8

t_PSK

t_r

t_f

Propagation Delay

Time of Enable from

V_EHtp V_EL

t_ELH

R_L= 350 Ω,

C_L= 15 pF,

V_EL= 0 V, V_EH= 3 V

Propagation Delay

Time of Enable from

V_ELto V_EH

t_EHL

*JEDEC registered data for the 6N137.

**Ratings apply to all devices except otherwise noted in the Package column.

Parameter Sym.

Device

Min. Typ.

Units Test Conditions

Fig. Note

Logic High |CM_H| HCPL-263L 15,000 25,000 V/µs |V_CM| = 10 V

V_CC= 3.3 V, I_F= 0 mA,

V_O(MIN)= 2 V,

R_L= 350 Ω, T_A= 25˚C

12, 14, 15

Common

Mode

HCPL-063L

Transient

Immunity

HCPL-260L 15,000 25,000

HCPL-060L

|V_CM| = 50 V

Logic Low

Common

Mode

Transient

Immunity

|CM_L| HCPL-263L 15,000 25,000 V/µs |V_CM| = 10 V

V_CC= 3.3 V, I_F= 7.5 mA,

V_O(MAX)= 0.8 V,

R_L= 350 Ω, T_A= 25˚C

13, 14, 15

HCPL-063L

HCPL-260L 15,00 25,000

HCPL-060L

|V_CM| = 50 V

6－111

Package Characteristics

All Typicals at T _A= 25˚C.

Parameter

Input-Output

Insulation

Sym. Package

Min. Typ. Max

Units Test Conditions

µA 45% RH, t = 5 s,

_I-O= 3 kV DC, T_A= 25˚C

Fig. Note

16, 17

I_I-O

Single 8-Pin DIP

Single SO-8

Input-Output

Momentary

Withstand

Voltage**

Input-Output

Resistance

Input-Output

Capacitance

Input-Input

Insulation

Leakage

Current

V_ISO

8-Pin DIP, SO-8

2500

V rms RH ≤ 50%, t = 1 min,

T_A= 25˚C

16, 17

R_I-O

C_I-O

I_I-I

8-Pin, SO-8

Ω

V_I-O=500 V dc

1, 16, 19

8-Pin DIP, SO-8

Dual Channel

0.6

µA

f = 1 MHz, T_A= 25˚C

0.005

RH ≤ 45%, t = 5 s,

V_I-I= 500 V

Resistance

(Input-Input)

Capacitance

(Input-Input)

R_I-I

C_I-I

Dual Channel

Ω

Dual 8-Pin Dip

Dual SO-8

0.03

0.25

f = 1 MHz

*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level

safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."

Notes:

1. Each channel.

2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not

exceed 20 mA.

3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not

exceed 15 mA.

4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.

5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in

Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.

6. The t

propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge

PLH

of the output pulse.

7. The t

of the output pulse.

propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge

PHL

8. t

is equal to the worst case difference in t

and/or t

that will be seen between units at any given temperature and specified test

PSK

conditions.

PHL

PLH

9. See test circuit for measurement details.

10. The t

enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the

ELH

rising edge of the output pulse.

11. The t

enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the

ELH

falling edge of the output pulse.

12. CM is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state

(i.e., V > 2.0 V).

13. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state

< 0.8 V).

(i.e., V

14. For sinusoidal voltages, (|dV | / dt)

= πf

(p-p).

max

CM CM

15. No external pull up is required for a high logic state on the enable input. If the V pin is not used, tying V to V will result in improved

CMR performance. For single channel products only. See application information provided.

16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage

detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the

I-O

VDE 0884 Insulation Characteristics Table, if applicable.

18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage

detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the

I-O

VDE 0884 Insulation Characteristics Table, if applicable.

19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.

20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.

6－112

8-PIN DIP, SO-8

= 3.3 V

8-PIN DIP, SO-8

0.8

0.7

= 3.3 V * FOR SINGLE

= 0.6 V

= 3.3 V

= 2.0 V*

= 250 µA

= 2.0 V*

CHANNEL

PRODUCTS ONLY

= 5.0 mA

0.6

0.5

0.4

0.3

0.2

* FOR SINGLE

CHANNEL

PRODUCTS

ONLY

= 350 Ω

= 1 KΩ

= 13 mA

0.1

= 4 KΩ

20 40

-60 -40 -20

20 40 60 80 100

-60 -40 -20

20 40

80 100

-60 -40 -20

80 100

– TEMPERATURE – °C

Figure 1. Typical high level output current vs.

temperature.

Figure 2. Typical input threshold current vs.

temperature.

Figure 3. Typical low level output voltage vs.

temperature.

8-PIN DIP, SO-8

1000

= 3.3 V

* FOR SINGLE

CHANNEL

PRODUCTS ONLY

= 25 °C

= 2.0 V*

100

= 0.6 V

–

1.0

= 5.0 mA

0.1

0.01

0.001

1.1

1.2

1.3

1.4

1.5

1.6

-60 -40 -20

20 40

80 100

– FORWARD VOLTAGE – V

– TEMPERATURE – °C

Figure 4. Typical low level output current vs.

temperature.

Figure 5. Typical input diode forward

characteristic.

PULSE GEN.

= 50 Ω

= t = 5 ns

SINGLE CHANNEL

DUAL CHANNEL

3.3 V

PULSE GEN.

= 50 Ω

= t = 5 ns

INPUT

MONITORING

NODE

OUTPUT V

0.1

MONITORING

NODE

BYPASS

0.1

OUTPUT V

MONITORING

NODE

INPUT

MONITORING

NODE

BYPASS

C *

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

= 7.50 mA

= 3.75 mA

INPUT

PLH

PHL

OUTPUT

1.5 V

Figure 6. Test circuit for t

and t

PLH

PHL

6－113

150

120

= 3.3 V

= 7.5 mA

= 3.3 V

= 7.5 mA

, R = 350 Ω

PLH

= 350 Ω

, R = 350 Ω

PHL

-60

-40 -20

20 40

80 100

-60 -40 -20

20 40

80 100

– TEMPERATURE – °C

Figure 7. Typical propagation delay vs.

temperature.

Figure 8. Typical pulse width distortion vs.

temperature.

PULSE GEN.

= 50 Ω

= t = 5 ns

INPUT V

MONITORING NODE

+3.3 V

3.0 V

1.5 V

INPUT

7.5 mA

0.1

BYPASS

ELH

EHL

OUTPUT V

MONITORING

NODE

OUTPUT

1.5 V

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

Figure 9. Test circuit for t

and t

EHL

ELH

SINGLE CHANNEL

DUAL CHANNEL

+3.3 V

OUTPUT V

MONITORING

NODE

0.1

BYPASS

OUTPUT V

MONITORING

NODE

0.1

BYPASS

GND

–

PULSE

GENERATOR

= 50 Ω

GENERATOR

= 50 Ω

(PEAK)

(MIN.)

0 V

SWITCH AT A: I = 0 mA

3.3 V

SWITCH AT B: I = 7.5 mA

(MAX.)

0.5 V

Figure 10. Test circuit for common mode transient immunity and typical waveforms.

6－114

GND BUS (BACK)

BUS (FRONT)

ENABLE

OUTPUT

0.1

10 mm MAX.

(SEE NOTE 5)

SINGLE CHANNEL

DEVICE ILLUSTRATED.

Figure 11. Recommended printed circuit board layout.

SINGLE CHANNEL DEVICE

3.3 V

CC1

CC2

220 Ω

D1*

0.1

BYPASS

–

GND 1

GND 2

SHIELD

*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.

DUAL CHANNEL DEVICE

CHANNEL 1 SHOWN

3.3 V

CC1

CC2

220 Ω

D1*

0.1

BYPASS

–

GND 1

GND 2

SHIELD

Figure 12. Recommended LVTTL interface circuit.

6－115

Application Information

Common-Mode Rejection for

HCPL-260L

CC+

0.01

HCPL-260L Families:

220 Ω

350 Ω

Figure 13 shows the recom-

mended drive circuit for optimal

common-mode rejection

performance. Two main points to

note are:

74LS04

OR ANY TOTEM-POLE

OUTPUT LOGIC GATE

GND

SHIELD

1. The enable pin is tied to V_CC

rather than floating (this

applies to single-channel parts

only).

GND1

GND2

HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).

2. Two LED-current setting

resistors are used instead of

one. This is to balance I_LED

variation during common-

mode transients.

Figure 13. Recommended drive circuit for High-CMR.

If the enable pin is left floating, it

is possible for common-mode

transients to couple to the enable

pin, resulting in common-mode

failure. This failure mechanism

only occurs when the LED is on

and the output is in the Low

State. It is identified as occurring

when the transient output voltage

rises above 0.8 V. Therefore, the

enable pin should be connected

to either V_CCor logic-level high

for best common-mode

1/2 R

0.01

LED

350 Ω

15 pF

GND

SHIELD

–

Figure 14. AC equivalent circuit.

performance with the output low

(CMR_L). This failure mechanism

is only present in single-channel

parts which have the enable

function.

For transients occurring when the

LED is on, common-mode rejec-

tion (CMR_L, since the output is in

the “low” state) depends upon the

amount of LED current drive (I_F).

For conditions where I_Fis close

to the switching threshold (I_TH),

CMR_Lalso depends on the extent

which I_LPand I_LNbalance each

other. In other words, any

condition where common-mode

transients cause a momentary

decrease in I_Fwill cause

common-mode failure for

transients which are fast enough.

output is “high”), if an imbalance

between I_LPand I_LNresults in a

transient I_Fequal to or greater

than the switching threshold of

the optocoupler, the transient

“signal” may cause the output to

spike below 2 V (which consti-

tutes a CMR_Hfailure).

Also, common-mode transients

can capacitively couple from the

LED anode (or cathode) to the

output-side ground causing

current to be shunted away from

the LED (which can be bad if the

LED is on) or conversely cause

current to be injected into the

LED (bad if the LED is meant to

be off). Figure 14 shows the

parasitic capacitances which

exists between LED

By using the recommended

circuit in Figure 13, good CMR

can be achieved. The balanced

I_LED-setting resistors help equalize

I_LPand I_LNto reduce the amount

by which I_LEDis modulated from

transient coupling through C_LA

and C_LC

anode/cathode and output ground

(C_LAand C_LC). Also shown in

Figure 14 on the input side is an

AC-equivalent circuit.

Likewise for common-mode

transients which occur when the

LED is off (i.e. CMR _H, since the

6－116

CMR with Other Drive

Circuits

HCPL-260L

CMR performance with drive

circuits other than that shown in

Figure 13 may be enhanced by

following these guidelines:

420 Ω

(MAX)

2N3906

(ANY PNP)

74L504

(ANY

TTL/CMOS

GATE)

LED

1. Use of drive circuits where

current is shunted from the

”

LED in the LED off” state (as

shown in Figures 15 and 16).

This is beneficial for good

CMR_H.

2. Use of I _FH> 3.5 mA. This is

good for high CMR_L.

Figure 15. TTL interface circuit.

Figure 15 shows a circuit which

can be used with any totem-pole-

output TTL/LSTTL/HCMOS logic

gate. The buffer PNP transistor

allows the circuit to be used with

logic devices which have low

current-sinking capability. It also

helps maintain the driving-gate

power-supply current at a

HCPL-260L

74HC00

(OR ANY

LED

OPEN-COLLECTOR/

OPEN-DRAIN

LOGIC GATE)

constant level to minimize ground

shifting for other devices

connected to the input-supply

ground.

Figure 16. TTL open-collector/open drain gate drive circuit.

When using an open-collector

TTL or open-drain CMOS logic

gate, the circuit in Figure 16 may

be used. When using a CMOS

gate to drive the optocoupler, the

circuit shown in Figure 17 may

be used. The diode in parallel

with the R_LEDspeeds the turn-off

of the optocoupler LED.

HCPL-260L

1N4148

220 Ω

74HC04

(OR ANY

LED

TOTEM-POLE

OUTPUT LOGIC

GATE)

Figure 17. CMOS gate drive circuit.

www.semiconductor.agilent.com

Data subject to change.

5980-2523EN (11/00)

6－117

HCPL-263L相关文章

配单直通车

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

HCPL-263L产品参数

型号:	HCPL-263L
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	0.300 INCH, DIP-8
Reach Compliance Code：	compliant
HTS代码：	8541.40.80.00
风险等级：	5.32
Is Samacsys：	N
其他特性：	UL RECOGNIZED, OPEN COLLECTOR, CMOS COMPATIBLE
配置：	SEPARATE, 2 CHANNELS
标称数据速率：	15 MBps
最大正向电流：	0.015 A
最大绝缘电压：	3750 V
JESD-609代码：	e0
元件数量：	2
最大通态电流：	0.05 A
最高工作温度：	85 °C
最低工作温度：	-40 °C
光电设备类型：	LOGIC IC OUTPUT OPTOCOUPLER
最小供电电压：	2.7 V
端子面层：	Tin/Lead (Sn/Pb)
Base Number Matches：	1

电子百科

产品导航

产品型号HCPL-263L的概述

产品型号HCPL-263L的Datasheet PDF文件预览

HCPL-263L相关产品

HCPL-263L相关文章

IC37:专业IC行业平台