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产品型号HCPL-3120-560的Datasheet PDF文件预览

sulationꢀvoltageꢀofꢀV  
=ꢀ1414  
                                 
VpeakꢀinꢀtheꢀIEC/EN/DINꢀ  
EN60747-5-2.ꢀTheHCPL-J312hasaninsulationvoltageꢀ  
ofꢀ V =ꢀ891 ꢀ andꢀ theꢀ V =ꢀ630 ꢀ isꢀ alsoꢀ ꢀ ꢀSafetyApproval:  
peak  
                     
V
peak  
                                        
V
                                                                              
Volts  
HCPL-3120/J312, HCNW3120  
2.5 Amp Output Current IGBT Gate Drive Optocoupler  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
TheꢀHCPL-3120ꢀcontainsꢀaꢀGaAsPꢀLEDꢀwhileꢀtheꢀꢀꢀꢀꢀꢀꢀꢀꢀHCPL-  
J312ꢀandꢀtheꢀHCNW3120ꢀcontainꢀanꢀAlGaAsꢀLED.ꢀTheꢀLEDꢀ  
isꢀopticallyꢀcoupledꢀtoꢀanꢀintegratedꢀcircuitꢀwithꢀaꢀpowerꢀ  
outputstage.ꢀTheseoptocouplersareideallysuitedforꢀ  
drivingꢀpowerꢀIGBTsꢀandꢀMOSFETsꢀusedꢀinꢀmotorꢀcontrolꢀ  
ꢀ ꢀ2.5ꢀAꢀmaximumꢀpeakꢀoutputꢀcurrent  
ꢀ ꢀ2.0ꢀAꢀminimumꢀpeakꢀoutputꢀcurrent  
ꢀ ꢀ25ꢀkV/µsꢀminimumꢀCommonꢀModeꢀRejectionꢀ(CMR)ꢀatꢀ  
V
ꢀ=ꢀ1500ꢀV  
CM  
inverterꢀapplications.ꢀTheꢀhighꢀoperatingꢀvoltageꢀrangeꢀ ꢀ ꢀ0.5ꢀ Vꢀ maximumꢀ lowꢀ levelꢀ outputꢀ voltageꢀ (V )ꢀ  
OL  
ofꢀtheꢀoutputꢀstageꢀprovidesꢀtheꢀdriveꢀvoltagesꢀrequiredꢀ  
byꢀ gateꢀ controlledꢀ devices.ꢀ Theꢀ voltageꢀ andꢀ currentꢀ  
suppliedꢀ byꢀ theseꢀ optocouplersꢀ makeꢀ themꢀ ideallyꢀ  
suitedꢀforꢀdirectlyꢀdrivingꢀIGBTsꢀwithꢀratingsꢀupꢀtoꢀ1200ꢀ  
V/100A.Forꢀ IGBTswithꢀ higherratings,theꢀ HCPL-3120ꢀ  
seriesꢀcanꢀbeꢀusedꢀtoꢀdriveꢀaꢀdiscreteꢀpowerꢀstageꢀwhichꢀ ꢀ ꢀWideꢀoperatingꢀV ꢀrange:ꢀ15ꢀtoꢀ30  
drivesꢀtheꢀIGBTꢀgate.ꢀTheꢀHCNW3120ꢀhasꢀtheꢀhighestꢀin-  
Eliminatesꢀneedꢀforꢀnegativeꢀgateꢀdrive  
ꢀ ꢀI ꢀ=ꢀ5ꢀmAꢀmaximumꢀsupplyꢀcurrent  
CC  
ꢀ ꢀUnderꢀ Voltageꢀ Lock-Outꢀ protectionꢀ (UVLO)ꢀ withꢀ  
hysteresis  
CC  
ꢀ ꢀ500ꢀnsꢀmaximumꢀswitchingꢀspeeds  
IORMꢀ  
ꢀ ꢀIndustrialꢀtemperatureꢀrange:ꢀ-40°Cꢀtoꢀ100°C  
IORMꢀ  
IORMꢀ  
availableꢀwithꢀtheꢀHCPL-3120ꢀ(Optionꢀ060).  
UL Recognized  
Functional Diagram  
3750ꢀVrmsꢀforꢀ1ꢀmin.ꢀforꢀHCPL-3120/J312ꢀ  
5000ꢀVrmsꢀforꢀ1ꢀmin.ꢀforꢀHCNW3120ꢀ  
CSA Approvalꢀ  
HCPL-3120/J312  
HCNW3120  
N/C  
ANODE  
CATHODE  
N/C  
VCC  
VO  
N/C  
VC  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VO  
N/C  
VE  
ANODE  
IEC/EN/DIN EN 60747-5-2 Approved  
VO CATHODE  
VEE  
N/C  
V
V
V
ꢀ=ꢀ630ꢀV  
ꢀforꢀHCPL-3120ꢀ(Optionꢀ060)ꢀ  
IORM  
IORM  
IORM  
peak  
peak  
ꢀ=ꢀ891ꢀV  
ꢀforꢀHCPL-J312ꢀ  
SHIELD  
SHIELD  
ꢀ=ꢀ1414ꢀV  
ꢀforꢀHCNW3120  
peak  
TRUTH TABLE  
Applications  
V
- V  
CC EE  
V - V  
CC EE  
ꢀ IGBT/MOSFETꢀgateꢀdrive  
ꢀ AC/BrushlessꢀDCꢀmotorꢀdrives  
ꢀ Industrialꢀinverters  
“POSITIVE GOING” “NEGATIVE GOING”  
LED  
OFFꢀ  
ONꢀ  
ONꢀ  
ONꢀ  
(i.e., TURN-ON)  
(i.e., TURN-OFF)  
V
O
LOWꢀ  
LOWꢀ  
0ꢀ-ꢀ30ꢀVꢀ  
0ꢀ-ꢀ30ꢀVꢀ  
0ꢀ-ꢀ11ꢀVꢀ  
0ꢀ-ꢀ9.5ꢀVꢀ  
ꢀ Switchꢀmodeꢀpowerꢀsupplies  
11ꢀ-ꢀ13.5ꢀVꢀ  
13.5ꢀ-ꢀ30ꢀVꢀ  
9.5ꢀ-ꢀ12ꢀVꢀ  
12ꢀ-ꢀ30ꢀVꢀ  
TRANSITIONꢀ  
HIGHꢀ  
Aꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀmustꢀbeꢀconnectedꢀbetweenꢀpinsꢀ5ꢀandꢀ8.  
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  
Selection Guide  
Part Number  
HCPL-3120  
HCPL-J312  
HCNW3120  
HCPL-3150*  
OutputꢀPeakꢀCurrentꢀ(ꢀIO)ꢀ  
2.5ꢀAꢀ  
2.5ꢀAꢀ  
2.5ꢀAꢀ  
0.6ꢀA  
IEC/EN/DINꢀENꢀꢀꢀ  
VIORMꢀ=ꢀ630ꢀVpeak  
VIORMꢀ=ꢀ891ꢀVpeak  
VIORMꢀ=ꢀ1414ꢀVpeak  
VIORMꢀ=ꢀ630ꢀVpeak  
60747-5-2ꢀApprovalꢀ  
(Optionꢀ060)ꢀ  
(Optionꢀ060)  
*TheꢀHCPL-3150ꢀDataꢀsheetꢀavailable.ꢀContactꢀAvagoꢀsalesꢀrepresentativeꢀorꢀauthorizedꢀdistributor.  
Ordering Information  
HCPL-3120ꢀandꢀHCPL-J312ꢀareꢀULꢀrecognizedꢀwithꢀ3750ꢀVrmsꢀforꢀ1ꢀminuteꢀperꢀUL1577.ꢀHCNW3120ꢀisꢀULꢀRecognizedꢀ  
withꢀ5000ꢀVrmsꢀforꢀ1ꢀminuteꢀperꢀUL1577.  
Option  
Part  
Number  
RoHS  
Compliant  
Non RoHS  
Compliant  
Surface  
Mount  
Gull  
Wing  
Tape  
& Reel  
IEC/EN/DIN  
EN 60747-5-2  
Package  
Quantity  
ꢀ  
-000Eꢀ  
-300Eꢀ  
-500Eꢀ  
-060Eꢀ  
-360Eꢀ  
-560Eꢀ  
-000Eꢀ  
-300Eꢀ  
-500Eꢀ  
-000Eꢀ  
-300Eꢀ  
-500Eꢀ  
Noꢀoptionꢀ  
#300ꢀꢀ  
50ꢀperꢀtubeꢀ  
50ꢀperꢀtubeꢀ  
1000ꢀperꢀreel  
50ꢀperꢀtubeꢀ  
50ꢀperꢀtubeꢀ  
1000ꢀperꢀtube  
50ꢀperꢀtubeꢀ  
50ꢀperꢀtubeꢀ  
1000ꢀperꢀreel  
42ꢀperꢀtubeꢀ  
42ꢀperꢀtubeꢀ  
750ꢀperꢀreel  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
HCPL-3120ꢀ  
#500ꢀ  
Xꢀ  
300mil  
DIP-8  
#060ꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
#360ꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
#560ꢀ  
Xꢀ  
Noꢀoptionꢀ  
#300ꢀꢀ  
300mil  
DIP-8  
HCPL-J312ꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
#500ꢀ  
Xꢀ  
Noꢀoptionꢀ  
#300ꢀꢀ  
400mil  
DIP-8  
HCNW3120ꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
Xꢀ  
#500ꢀ  
Xꢀ  
Toꢀorder,ꢀchooseꢀaꢀpartꢀnumberꢀfromꢀtheꢀpartꢀnumberꢀcolumnꢀandꢀcombineꢀwithꢀtheꢀdesiredꢀoptionꢀfromꢀtheꢀoptionꢀ  
columnꢀtoꢀformꢀanꢀorderꢀentry.ꢀ  
Exampleꢀ1:ꢀ  
ꢀ HCPL-3120-560Eꢀtoꢀorderꢀproductꢀofꢀ300ꢀmilꢀDIPꢀGullꢀWingꢀSurfaceꢀMountꢀpackageꢀinꢀTapeꢀandꢀReelꢀpackagingꢀwithꢀ  
IEC/EN/DINꢀENꢀ60747-5-2ꢀSafetyꢀApprovalꢀinꢀRoHSꢀcompliant.  
Exampleꢀ2:ꢀ  
ꢀ ꢀ HCPL-3120ꢀtoꢀorderꢀproductꢀofꢀ300ꢀmilꢀDIPꢀpackageꢀinꢀtubeꢀpackagingꢀandꢀnonꢀRoHSꢀcompliant.  
Optionꢀdatasheetsꢀareꢀavailable.ꢀContactꢀyourꢀAvagoꢀsalesꢀrepresentativeꢀorꢀauthorizedꢀdistributorꢀforꢀinformation.  
th  
Remarks:ꢀTheꢀnotationꢀ‘#XXX’ꢀisꢀusedꢀforꢀexistingꢀproducts,ꢀwhileꢀ(new)ꢀproductsꢀlaunchedꢀsinceꢀ15 ꢀJulyꢀ2001ꢀandꢀ  
RoHSꢀcompliantꢀoptionꢀwillꢀuseꢀ‘-XXXE.  
2
Package Outline Drawings  
HCPL-3120 Outline Drawing (Standard DIP Package)  
7.63 0.35  
(0.ꢀ00 0.010ꢁ  
9.65 0.35  
(0.ꢀ80 0.010ꢁ  
8
1
7
6
5
6.ꢀ5 0.35  
(0.350 0.010ꢁ  
TYPE NUMBER  
OPTION CODE*  
DATE CODE  
A XXXXZ  
YYWW  
3
4
1.78 (0.070ꢁ MAX.  
1.19 (0.047ꢁ MAX.  
+ 0.076  
- 0.051  
0.354  
5° TYP.  
+ 0.00ꢀꢁ  
- 0.003ꢁ  
ꢀ.56 0.1ꢀ  
(0.140 0.005ꢁ  
(0.010  
4.70 (0.185ꢁ MAX.  
0.51 (0.030ꢁ MIN.  
3.93 (0.115ꢁ MIN.  
DIMENSIONS IN MILLIMETERS AND (INCHESꢁ.  
* MARKING CODE LETTER FOR OPTION NUMBERS.  
"V" = OPTION 060  
1.080 0.ꢀ30  
(0.04ꢀ 0.01ꢀꢁ  
0.65 (0.035ꢁ MAX.  
OPTION NUMBERS ꢀ00 AND 500 NOT MARKED.  
3.54 0.35  
(0.100 0.010ꢁ  
NOTE: FLOATING LEAD PROTRUSION IS 0.35 mm (10 milsꢁ MAX.  
HCPL-3120 Gull Wing Surface Mount Option 300 Outline Drawing  
LAND PATTERN RECOMMENDATION  
1.016 (0.040ꢁ  
9.65 0.35  
(0.ꢀ80 0.010ꢁ  
6
5
8
1
7
6.ꢀ50 0.35  
(0.350 0.010ꢁ  
10.9 (0.4ꢀ0ꢁ  
3
4
3.0 (0.080ꢁ  
1.37 (0.050ꢁ  
9.65 0.35  
1.780  
(0.070ꢁ  
MAX.  
(0.ꢀ80 0.010ꢁ  
1.19  
(0.047ꢁ  
MAX.  
7.63 0.35  
(0.ꢀ00 0.010ꢁ  
+ 0.076  
0.354  
- 0.051  
ꢀ.56 0.1ꢀ  
(0.140 0.005ꢁ  
+ 0.00ꢀꢁ  
- 0.003ꢁ  
(0.010  
1.080 0.ꢀ30  
(0.04ꢀ 0.01ꢀꢁ  
0.6ꢀ5 0.35  
(0.035 0.010ꢁ  
13° NOM.  
0.6ꢀ5 0.1ꢀ0  
(0.035 0.005ꢁ  
3.54  
(0.100ꢁ  
BSC  
DIMENSIONS IN MILLIMETERS (INCHESꢁ.  
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢁ.  
NOTE: FLOATING LEAD PROTRUSION IS 0.35 mm (10 milsꢁ MAX.  
3
Package Outline Drawings  
HCPL-J312 Outline Drawing (Standard DIP Package)  
7.62 0.25  
(0.300 0.010)  
9.80 0.25  
(0.386 0.010)  
8
1
7
6
5
6.35 0.25  
(0.250 0.010)  
TYPE NUMBER  
DATE CODE  
A XXXX  
YYWW  
2
3
4
1.78 (0.070) MAX.  
1.19 (0.047) MAX.  
+ 0.076  
- 0.051  
0.254  
5° TYP.  
+ 0.003)  
- 0.002)  
3.56 0.13  
(0.140 0.005)  
(0.010  
4.70 (0.185) MAX.  
0.51 (0.020) MIN.  
2.92 (0.115) MIN.  
DIMENSIONS IN MILLIMETERS AND (INCHES).  
OPTION NUMBERS 300 AND 500 NOT MARKED.  
1.080 0.320  
0.65 (0.025) MAX.  
(0.043 0.013)  
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.  
2.54 0.25  
(0.100 0.010)  
HCPL-J312 Gull Wing Surface Mount Option 300 Outline Drawing  
LAND PATTERN RECOMMENDATION  
1.016 (0.040)  
9.80 0.25  
(0.386 0.010)  
6
5
8
1
7
6.350 0.25  
(0.250 0.010)  
10.9 (0.430)  
2.0 (0.080)  
2
3
4
1.27 (0.050)  
9.65 0.25  
1.780  
(0.070)  
MAX.  
(0.380 0.010)  
1.19  
(0.047)  
MAX.  
7.62 0.25  
(0.300 0.010)  
+ 0.076  
0.254  
- 0.051  
3.56 0.13  
(0.140 0.005)  
+ 0.003)  
- 0.002)  
(0.010  
1.080 0.320  
(0.043 0.013)  
0.635 0.25  
(0.025 0.010)  
12°  
NOM.  
0.635 0.130  
(0.025 0.005)  
2.54  
(0.100)  
BSC  
DIMENSIONS IN MILLIMETERS (INCHES).  
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).  
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.  
4
HCNW3120 Outline Drawing (8-Pin Wide Body Package)  
11.00  
(0.4ꢀꢀꢁ  
11.15 0.15  
(0.443 0.006ꢁ  
MAX.  
9.00 0.15  
(0.ꢀ54 0.006ꢁ  
7
6
5
8
TYPE NUMBER  
DATE CODE  
A
HCNWXXXX  
YYWW  
1
3
4
10.16 (0.400ꢁ  
TYP.  
1.55  
(0.061ꢁ  
MAX.  
7° TYP.  
+ 0.076  
- 0.0051  
0.354  
+ 0.00ꢀꢁ  
- 0.003ꢁ  
(0.010  
5.10  
(0.301ꢁ  
MAX.  
ꢀ.10 (0.133ꢁ  
ꢀ.90 (0.154ꢁ  
0.51 (0.031ꢁ MIN.  
3.54 (0.100ꢁ  
TYP.  
1.78 0.15  
(0.070 0.006ꢁ  
0.40 (0.016ꢁ  
0.56 (0.033ꢁ  
DIMENSIONS IN MILLIMETERS (INCHESꢁ.  
NOTE: FLOATING LEAD PROTRUSION IS 0.35 mm (10 milsꢁ MAX.  
HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing  
11.15 0.15  
(0.443 0.006ꢁ  
LAND PATTERN RECOMMENDATION  
7
6
5
8
9.00 0.15  
(0.ꢀ54 0.006ꢁ  
1ꢀ.56  
(0.5ꢀ4ꢁ  
1
3
4
3.39  
(0.09ꢁ  
1.ꢀ  
(0.051ꢁ  
13.ꢀ0 0.ꢀ0  
1.55  
(0.061ꢁ  
MAX.  
(0.484 0.013ꢁ  
11.00  
MAX.  
(0.4ꢀꢀꢁ  
4.00  
MAX.  
(0.158ꢁ  
1.78 0.15  
(0.070 0.006ꢁ  
1.00 0.15  
(0.0ꢀ9 0.006ꢁ  
0.75 0.35  
(0.0ꢀ0 0.010ꢁ  
+ 0.076  
- 0.0051  
3.54  
(0.100ꢁ  
BSC  
0.354  
+ 0.00ꢀꢁ  
- 0.003ꢁ  
(0.010  
DIMENSIONS IN MILLIMETERS (INCHESꢁ.  
7° NOM.  
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢁ.  
NOTE: FLOATING LEAD PROTRUSION IS 0.35 mm (10 milsꢁ MAX.  
5
Solder Reflow Temperature Profile  
300  
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.  
REFLOW HEATING RATE 2.5 °C 0.5 °C/SEC.  
PEAK  
TEMP.  
245 °C  
PEAK  
TEMP.  
240 °C  
PEAK  
TEMP.  
230 °C  
200  
100  
0
2.5 C 0.5 °C/SEC.  
SOLDERING  
30  
TIME  
160 °C  
150 °C  
140 °C  
SEC.  
200 °C  
30  
SEC.  
3 °C + 1 °C/–0.5 °C  
PREHEATING TIME  
150 °C, 90 + 30 SEC.  
50 SEC.  
TIGHT  
TYPICAL  
LOOSE  
ROOM  
TEMPERATURE  
0
50  
100  
150  
200  
250  
TIME (SECONDS)  
NOTE: NON-HALIDE FLUX SHOULD BE USED.  
Recommended Pb-Free IR Profile  
TIMEWITHIN 5 °C of ACTUAL  
PEAKTEMPERATURE  
tp  
15 SEC.  
* 260 +0/-5 °C  
RAMP-UP  
Tp  
217 °C  
TL  
RAMP-DOWN  
6 °C/SEC. MAX.  
3 °C/SEC. MAX.  
150 - 200 °C  
Tsmax  
Tsmin  
ts  
tL  
PREHEAT  
60 to 150 SEC.  
60 to 180 SEC.  
25  
t 25 °C to PEAK  
TIME  
NOTES:  
THETIME FROM 25 °C to PEAKTEMPERATURE = 8 MINUTES MAX.  
Tsmax = 200 °C, Tsmin = 150 °C  
NOTE: NON-HALIDE FLUX SHOULD BE USED.  
* RECOMMENDED PEAKTEMPERATURE FORWIDEBODY 400mils PACKAGE IS 245 °C  
6
Regulatory Information  
Agency/Standard  
HCPL-3120  
HCPL-J312  
HCNW3120  
UnderwritersꢀLaboratoryꢀ(UL)ꢀ  
Compliantꢀ  
Compliantꢀ  
Compliantꢀ  
RecognizedꢀunderꢀULꢀ1577,ꢀComponentꢀRecognitionꢀProgram,ꢀ  
Category,ꢀFileꢀE55361  
CanadianꢀStandardsꢀAssociationꢀ(CSA)ꢀFileꢀCA88324,ꢀ  
perꢀComponentꢀAcceptanceꢀNoticeꢀ#5  
Compliantꢀ  
Compliantꢀ  
Compliantꢀ  
Compliantꢀ  
Compliantꢀ  
IEC/EN/DINꢀENꢀ60747-5-2ꢀ  
Compliantꢀ  
Optionꢀ060  
Insulation and Safety Related Specifications  
Value  
HCPL-  
J312  
HCPL-  
3120  
HCNW  
3120  
Parameter  
Symbol  
Units  
Conditions  
MinimumꢀExternalꢀ  
AirꢀGapꢀ(Clearance)ꢀ  
L(101)ꢀ  
7.1ꢀ  
7.4ꢀ  
9.6ꢀ  
mmꢀ  
Measuredꢀfromꢀinputꢀterminalsꢀtoꢀoutputꢀ  
terminals,ꢀshortestꢀdistanceꢀthroughꢀair.  
MinimumꢀExternalꢀ  
ꢀTrackingꢀ(Creepage)ꢀ  
ꢀꢀ  
L(102)ꢀ  
7.4ꢀ  
8.0ꢀ  
10.0ꢀ  
mmꢀ  
Measuredꢀfromꢀinputꢀterminalsꢀtoꢀoutputꢀꢀ  
terminals,ꢀshortestꢀdistanceꢀpathꢀalongꢀ  
body.  
MinimumꢀInternalꢀ  
PlasticꢀGapꢀ  
(InternalꢀClearance)ꢀ  
0.08ꢀ  
0.5ꢀ  
1.0ꢀ  
mmꢀ  
Insulationꢀthicknessꢀbetweenꢀemitterꢀ  
andꢀdetector;ꢀalsoꢀknownꢀasꢀdistanceꢀ  
throughꢀinsulation.  
ꢀTrackingꢀResistanceꢀ  
ꢀ(Comparativeꢀ  
CTIꢀ  
>175ꢀ  
>175ꢀ  
>200ꢀ  
Voltsꢀ  
DINꢀIECꢀ112/VDEꢀ0303ꢀPartꢀ1ꢀ  
ꢀTrackingꢀIndex)  
IsolationꢀGroupꢀ  
ꢀꢀ  
IIIaꢀ  
IIIaꢀ  
IIIaꢀ  
MaterialꢀGroupꢀ(DINꢀVDEꢀ0110,ꢀ1/89,ꢀ  
Tableꢀ1)  
7
AllꢀAvagoꢀdataꢀsheetsꢀreportꢀtheꢀcreepageꢀandꢀclearanceꢀ theꢀsurfaceꢀofꢀaꢀprintedꢀcircuitꢀboardꢀbetweenꢀtheꢀsolderꢀ  
inherentꢀ toꢀ theꢀ optocouplerꢀ componentꢀ itself.ꢀ Theseꢀ filletsꢀofꢀtheꢀinputꢀandꢀoutputꢀleadsꢀmustꢀbeꢀconsidered.ꢀ  
dimensionsꢀ areꢀ neededꢀ asꢀ aꢀ startingꢀ pointꢀ forꢀ theꢀ Thereꢀ areꢀ recommendedꢀ techniquesꢀ suchꢀ asꢀ groovesꢀ  
equipmentꢀdesignerꢀwhenꢀdeterminingꢀtheꢀcircuitꢀinsula- andribswhichmaybeusedonaprintedcircuitboardꢀ  
tionꢀrequirements.ꢀHowever,ꢀonceꢀmountedꢀonꢀaꢀprintedꢀ toachievedesiredcreepageandclearances.Creepageꢀ  
circuitꢀboard,ꢀminimumꢀcreep-ageꢀandꢀclearanceꢀrequire- andꢀclearanceꢀdistancesꢀwillꢀalsoꢀchangeꢀdependingꢀonꢀ  
mentsꢀmustꢀbeꢀmetꢀasꢀspecifiedꢀforꢀindividualꢀequipmentꢀ factorsꢀsuchꢀasꢀpollutionꢀdegreeꢀandꢀinsulationꢀlevel.  
standards.ꢀForꢀcreepage,ꢀtheꢀshortestꢀdistanceꢀpathꢀalongꢀ  
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics  
HCPL-3120  
Description  
Symbol  
Option 060  
HCPL-J312  
HCNW3120  
Unit  
InstallationꢀclassificationꢀperꢀDINꢀVDEꢀ0110/1.89,ꢀ  
Tableꢀ1ꢀ  
ꢀ ꢀ  
forꢀratedꢀmainsꢀvoltageꢀ≤150ꢀVꢀrmsꢀ  
forꢀratedꢀmainsꢀvoltageꢀ≤300ꢀVꢀrmsꢀ  
forꢀratedꢀmainsꢀvoltageꢀ≤450ꢀVꢀrmsꢀ  
forꢀratedꢀmainsꢀvoltageꢀ≤600ꢀVꢀrmsꢀ  
forꢀratedꢀmainsꢀvoltageꢀ≤1000ꢀVꢀrmsꢀ  
I-IVꢀ  
I-IVꢀ  
I-IIIꢀ  
I-IVꢀ  
I-IVꢀ  
I-IIIꢀ  
I-IIIꢀ  
I-IVꢀ  
I-IVꢀ  
I-IVꢀ  
I-IVꢀ  
I-III  
ClimaticꢀClassificationꢀ  
55/100/21ꢀ  
2ꢀ  
55/100/21ꢀ  
2ꢀ  
55/100/21  
2
PollutionꢀDegreeꢀ(DINꢀVDEꢀ0110/1.89)ꢀ  
MaximumꢀWorkingꢀInsulationꢀVoltageꢀ  
InputꢀtoꢀOutputꢀTestꢀVoltage,ꢀMethodꢀb*ꢀ  
VIORM  
630ꢀ  
891ꢀ  
1414ꢀ  
2652ꢀ  
Vpeak  
Vpeak  
VPR  
1181ꢀ  
1670ꢀ  
VIORMꢀxꢀ1.875ꢀ=ꢀVPR,ꢀ100%ꢀProductionꢀTest,ꢀ  
tmꢀ=ꢀ1ꢀsec,ꢀPartialꢀDischargeꢀ<ꢀ5pCꢀ  
InputꢀtoꢀOutputꢀTestꢀVoltage,ꢀMethodꢀa*ꢀ  
VPR  
945ꢀ  
1336ꢀ  
2121ꢀ  
Vpeak  
VIORMꢀxꢀ1.5ꢀ=ꢀVPR,ꢀTypeꢀandꢀSampleꢀTest,ꢀ  
tmꢀ=ꢀ60ꢀsec,ꢀPartialꢀDischargeꢀ<ꢀ5pC  
HighestꢀAllowableꢀOvervoltage*ꢀ  
(TransientꢀOvervoltage,ꢀtiniꢀ=ꢀ10ꢀsec)ꢀ  
VIOTM  
6000ꢀ  
6000ꢀ  
8000ꢀ  
Vpeak  
SafetyꢀLimitingꢀValuesꢀ–ꢀmaximumꢀvaluesꢀallowedꢀ  
inꢀtheꢀeventꢀofꢀaꢀfailure,ꢀalsoꢀseeꢀFigureꢀ37.ꢀ  
ꢀ ꢀ  
ꢀꢀꢀꢀCaseꢀTemperatureꢀ  
ꢀꢀꢀꢀInputꢀCurrentꢀ  
ꢀꢀꢀꢀOutputꢀPowerꢀ  
TSꢀ  
175ꢀ  
230ꢀ  
600ꢀ  
175ꢀ  
400ꢀ  
600ꢀ  
150ꢀ  
400ꢀ  
700ꢀ  
°Cꢀ  
mAꢀ  
mW  
ISꢀINPUT  
PSꢀOUTPUT  
RSꢀ  
InsulationꢀResistanceꢀatꢀTS,ꢀVIOꢀ=ꢀ500ꢀVꢀ  
≥109ꢀ  
≥109ꢀ  
≥109ꢀ  
Ω
*ReferꢀtoꢀtheꢀIEC/EN/DINꢀENꢀ60747-5-2ꢀsectionꢀ(pageꢀ1-6/8)ꢀofꢀtheꢀIsolationꢀControlꢀComponentꢀDesigner’sꢀCatalogꢀforꢀaꢀdetailedꢀdescriptionꢀofꢀ  
Methodꢀa/bꢀpartialꢀdischargeꢀtestꢀprofiles.  
Note:ꢀTheseꢀoptocouplersꢀareꢀsuitableꢀforꢀ“safeꢀelectricalꢀisolation”ꢀonlyꢀwithinꢀtheꢀsafetyꢀlimitꢀdata.ꢀMaintenanceꢀofꢀtheꢀsafetyꢀdataꢀshallꢀbeꢀen-  
suredꢀbyꢀmeansꢀofꢀprotectiveꢀcircuits.ꢀSurfaceꢀmountꢀclassificationꢀisꢀClassꢀAꢀinꢀaccordanceꢀwithꢀCECCꢀ00802.  
8
Absolute Maximum Ratings  
Parameter  
Symbol  
Min.  
Max.  
125ꢀ  
100ꢀ  
25ꢀ  
Units  
°C  
Note  
StorageꢀTemperatureꢀ  
OperatingꢀTemperatureꢀ  
AverageꢀInputꢀCurrentꢀ  
TSꢀ  
-55ꢀ  
TAꢀ  
-40ꢀ  
°C  
IF(AVG)  
mAꢀ  
Aꢀ  
1
PeakꢀTransientꢀInputꢀCurrentꢀ  
(<1ꢀµsꢀpulseꢀwidth,ꢀ300ꢀpps)  
IF(TRAN)  
1.0ꢀ  
ReverseꢀInputꢀVoltageꢀ  
HCPL-3120ꢀ  
VRꢀ  
5ꢀ  
5ꢀ  
Volts  
HCPL-J312ꢀ  
HCNW3120  
“High”ꢀPeakꢀOutputꢀCurrentꢀ  
“Low”ꢀPeakꢀOutputꢀCurrentꢀ  
SupplyꢀVoltageꢀ  
IOH(PEAK)  
2.5ꢀ  
2.5ꢀ  
35ꢀ  
Aꢀ  
2
2
IOL(PEAK)  
Aꢀ  
(VCCꢀ-ꢀVEE)ꢀ  
tr(IN)ꢀ/tf(IN)ꢀ  
0ꢀ  
Volts  
ns  
InputꢀCurrentꢀ(Rise/FallꢀTime)ꢀ  
OutputꢀVoltageꢀ  
500ꢀ  
VO(PEAK)  
0ꢀ  
VCC  
Volts  
mWꢀ  
mWꢀ  
OutputꢀPowerꢀDissipationꢀ  
TotalꢀPowerꢀDissipationꢀ  
POꢀ  
250ꢀ  
295ꢀ  
3
4
PTꢀ  
LeadꢀSolderꢀTemperatureꢀ  
HCPL-3120ꢀ  
HCPL-J312  
260°Cꢀforꢀ10ꢀsec.,ꢀ1.6ꢀmmꢀbelowꢀseatingꢀplaneꢀ  
HCNW3120ꢀ  
ꢀ 260°Cꢀforꢀ10ꢀsec.,ꢀupꢀtoꢀseatingꢀplane  
ꢀ SeeꢀPackageꢀOutlineꢀDrawingsꢀsection  
SolderꢀReflowꢀTemperatureꢀProfileꢀ  
ꢀ ꢀ ꢀ  
Recommended Operating Conditions  
Parameter  
Symbol  
Min.  
Max.  
Units  
PowerꢀSupplyꢀVoltageꢀ  
(VCCꢀ-ꢀVEE)ꢀ  
15ꢀ  
30ꢀ  
Volts  
InputꢀCurrentꢀ(ON)ꢀ  
HCPL-3120ꢀ  
HCPL-J312ꢀ  
7ꢀ  
IF(ON)  
VF(OFF)  
TAꢀ  
16ꢀ  
mA  
HCNW3120ꢀ  
10  
InputꢀVoltageꢀ(OFF)ꢀ  
-3.6ꢀ  
-40ꢀ  
0.8ꢀ  
V
OperatingꢀTemperatureꢀ ꢀ  
100ꢀ  
°C  
9
Electrical Specifications (DC)  
Overꢀ recommendedꢀ operatingꢀ conditionsꢀ (T ꢀ =ꢀ -40ꢀ toꢀ 100°C,ꢀ forꢀ HCPL-3120,ꢀ HCPL-J312ꢀ I  
ꢀ =ꢀ 7ꢀ toꢀ 16mA,ꢀ forꢀ  
F(ON)  
A
HCNW3120ꢀI  
ꢀ=ꢀ10ꢀtoꢀ16mA,ꢀV  
ꢀ=ꢀ-3.6ꢀtoꢀ0.8ꢀV,ꢀV ꢀ=ꢀ15ꢀtoꢀ30ꢀV,ꢀV ꢀ=ꢀGround)ꢀunlessꢀotherwiseꢀspecified.  
F(ON)  
F(OFF)  
CC  
EE  
Parameter  
Symbol  
Device  
Min.  
0.5ꢀ  
2.0ꢀ  
0.5ꢀ  
2.0ꢀ  
Typ.*  
Max.  
Units  
Aꢀ  
Test Conditions  
Fig.  
Note  
HighꢀLevelꢀOutputꢀ IOHꢀ  
Current  
1.5ꢀ  
VOꢀ=ꢀ(VCCꢀ-ꢀ4ꢀV)ꢀ  
VOꢀ=ꢀ(VCCꢀ-ꢀ15ꢀV)ꢀ  
VOꢀ=ꢀ(VEEꢀ+ꢀ2.5ꢀV)ꢀ  
VOꢀ=ꢀ(VEEꢀ+ꢀ15ꢀV)ꢀ  
2,ꢀ3,ꢀ  
5
2
5
2
17  
Aꢀ  
LowꢀLevelꢀOutputꢀ  
Current  
IOLꢀ  
2.0ꢀ  
Aꢀ  
5,ꢀ6,ꢀ  
18  
Aꢀ  
HighꢀLevelꢀOutputꢀ VOH  
(VCCꢀ-ꢀ4)ꢀ (VCCꢀ-ꢀ3)ꢀ  
Vꢀ  
IOꢀ=ꢀ-100ꢀmAꢀ  
1,ꢀ3,ꢀ 6,ꢀ7ꢀ  
19  
Voltageꢀ  
LowꢀLevelꢀOutputꢀ  
Voltageꢀ  
VOLꢀ  
0.1ꢀ  
0.5ꢀ  
Vꢀ  
IOꢀ=ꢀ100ꢀmAꢀ  
4,ꢀ6,ꢀ  
20  
HighꢀLevelꢀSupplyꢀ  
Currentꢀ  
ICCH  
ICCL  
2.5ꢀ  
5.0ꢀ  
mAꢀ  
OutputꢀOpen,ꢀ  
IFꢀ=ꢀ7ꢀtoꢀ16ꢀmA  
7,ꢀ8ꢀ  
LowꢀLevelꢀSupplyꢀ  
Currentꢀ  
2.5ꢀ  
5.0ꢀ  
mAꢀ  
OutputꢀOpen,ꢀ  
VFꢀ=ꢀ-3.0ꢀtoꢀ+0.8ꢀV  
ThresholdꢀInputꢀ  
IFLH  
HCPL-3120ꢀ  
HCPL-J312ꢀ  
HCNW3120ꢀ  
2.3ꢀ  
5.0ꢀ  
mAꢀ  
IOꢀ=ꢀ0ꢀmA,ꢀ  
VOꢀ>ꢀ5ꢀVꢀ  
9,ꢀ15,  
21  
CurrentꢀLowꢀto  
1.0  
High  
2.3ꢀ  
8.0  
ThresholdꢀInputꢀ  
VoltageꢀHighꢀtoꢀ  
Low  
VFHL  
0.8ꢀ  
Vꢀ  
Vꢀ  
InputꢀForwardꢀ  
VFꢀ  
HCPL-3120ꢀ  
1.2ꢀ  
1.5ꢀ  
1.6ꢀ  
1.8ꢀ  
IFꢀ=ꢀ10ꢀmAꢀ  
16  
Voltage  
HCPL-J312ꢀ  
HCNW3120  
1.95ꢀ  
Temperatureꢀ  
∆VF/∆TAꢀ HCPL-3120ꢀ  
-1.6ꢀ  
-1.3ꢀ  
mV/°Cꢀ IFꢀ=ꢀ10ꢀmA  
Coefficientꢀof  
ForwardꢀVoltage  
HCPL-J312ꢀ  
HCNW3120  
InputꢀReverseꢀ  
BVRꢀ  
HCPL-3120ꢀ  
5ꢀ  
3ꢀ  
Vꢀ  
IRꢀ=ꢀ10ꢀµA  
Breakdown  
Voltage  
HCPL-J312ꢀ  
HCNW3120  
IRꢀ=ꢀ100ꢀµAꢀ  
InputꢀCapacitanceꢀ  
CINꢀ  
HCPL-3120ꢀ  
60ꢀ  
70ꢀ  
pFꢀ  
fꢀ=ꢀ1ꢀMHz,  
VFꢀ=ꢀ0ꢀV  
HCPL-J312ꢀ  
HCNW3120  
UVLOꢀThresholdꢀ  
VUVLO+  
VUVLO–  
UVLOHYS  
11.0ꢀ  
12.3ꢀ  
13.5ꢀ  
Vꢀ  
VOꢀ>ꢀ5ꢀV,ꢀ  
IFꢀ=ꢀ10ꢀmAꢀ  
22,ꢀ  
34  
9.5ꢀ  
10.7ꢀ  
1.6  
12.0ꢀ  
UVLOꢀHysteresisꢀ  
*AllꢀtypicalꢀvaluesꢀatꢀT ꢀ=ꢀ25°CꢀandꢀV ꢀ-ꢀV ꢀ=ꢀ30ꢀV,ꢀunlessꢀotherwiseꢀnoted.  
A
CC  
EE  
10  
Switching Specifications (AC)  
Overꢀ recommendedꢀ operatingꢀ conditionsꢀ (T ꢀ =ꢀ -40ꢀ toꢀ 100°C,ꢀ forꢀ HCPL-3120,HCPL-J312ꢀ I  
ꢀ =ꢀ 7ꢀ toꢀ 16mA,ꢀ forꢀ  
F(ON)  
A
HCNW3120ꢀI  
ꢀ=ꢀ10ꢀtoꢀ16mA,ꢀV  
ꢀ=ꢀ-3.6ꢀtoꢀ0.8ꢀV,ꢀV ꢀ=ꢀ15ꢀtoꢀ30ꢀV,ꢀꢀV ꢀ=ꢀGround)ꢀunlessꢀotherwiseꢀspecified.  
F(ON)  
F(OFF)  
CC  
EE  
Parameter  
Symbol  
Min.  
Typ.*  
Max.  
Units  
Test Conditions  
Fig.  
Note  
PropagationꢀDelayꢀTimeꢀ  
toꢀHighꢀOutputꢀLevelꢀ  
tPLH  
0.10ꢀ  
0.30ꢀ  
0.50ꢀ  
µsꢀ  
Rgꢀ=ꢀ10ꢀΩ,ꢀ  
Cgꢀ=ꢀ10ꢀnF,ꢀ  
10,ꢀ11,ꢀ 16ꢀ  
12,ꢀ13,ꢀ  
fꢀ=ꢀ10ꢀkHz,ꢀ  
DutyꢀCycleꢀ=ꢀ50%  
14,ꢀ23  
PropagationꢀDelayꢀTimeꢀ  
toꢀLowꢀOutputꢀLevelꢀ  
tPHL  
0.10ꢀ  
0.30ꢀ  
0.50ꢀ  
µsꢀ  
PulseꢀWidthꢀDistortionꢀ  
PWDꢀ  
0.3ꢀ  
µsꢀ  
µsꢀ  
17  
PropagationꢀDelayꢀ  
DifferenceꢀBetweenꢀAnyꢀ  
TwoꢀParts  
PDDꢀ  
(tPHLꢀ-ꢀtPLH)ꢀ  
-0.35ꢀ  
0.35ꢀ  
35,ꢀ36ꢀ 12ꢀ  
RiseꢀTimeꢀ  
trꢀ  
tfꢀ  
0.1ꢀ  
0.1ꢀ  
0.8ꢀ  
0.6ꢀ  
µsꢀ  
µs  
µsꢀ  
23  
22  
FallꢀTimeꢀ  
UVLOꢀTurnꢀOnꢀDelayꢀ  
UVLOꢀTurnꢀOffꢀDelayꢀ  
tUVLOꢀON  
VOꢀ>ꢀ5ꢀV,ꢀIFꢀ=ꢀ10ꢀmAꢀ  
VOꢀ<ꢀ5ꢀV,ꢀIFꢀ=ꢀ10ꢀmA  
tUVLOꢀOFF  
OutputꢀHighꢀLevelꢀCommonꢀ |CMH|ꢀ  
25ꢀ  
35ꢀ  
kV/µsꢀ  
TAꢀ=ꢀ25°C,ꢀ  
24ꢀ  
13,ꢀ14ꢀ  
ModeꢀTransientꢀImmunityꢀ  
IFꢀ=ꢀ10ꢀtoꢀ16ꢀmA,ꢀ  
VCMꢀ=ꢀ1500ꢀV,ꢀ  
VCCꢀ=ꢀ30ꢀV  
OutputꢀLowꢀLevelꢀCommonꢀ  
|CML|ꢀ  
25ꢀ  
35ꢀ  
kV/µsꢀ  
TAꢀ=ꢀ25°C,ꢀ  
VCMꢀ=ꢀ1500ꢀV,ꢀ  
VFꢀ=ꢀ0ꢀV,ꢀVCCꢀ=ꢀ30ꢀV  
13,ꢀ15ꢀ  
ModeꢀTransientꢀImmunityꢀ  
*AllꢀtypicalꢀvaluesꢀatꢀT ꢀ=ꢀ25°CꢀandꢀV ꢀ-ꢀV ꢀ=ꢀ30ꢀV,ꢀunlessꢀotherwiseꢀnoted.  
A
CC  
EE  
11  
                                             
                                                  
Package Characteristics  
Overꢀrecommendedꢀtemperatureꢀ(T ꢀ=ꢀ-40ꢀtoꢀ100°C)ꢀunlessꢀotherwiseꢀspecified.  
A
Parameter  
Symbol  
Device  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Fig. Note  
Input-OutputꢀMomentaryꢀ  
VISO  
HCPL-3120ꢀ  
HCPL-J312ꢀ  
3750ꢀ  
3750ꢀ  
VRMS  
RHꢀ<ꢀ50%,ꢀ  
8,ꢀ11  
9,ꢀ11  
10,ꢀ11  
11ꢀ  
tꢀ=ꢀ1ꢀmin.,  
TAꢀ=ꢀ25°C  
WithstandꢀVoltage**  
HCNW3120ꢀ 5000ꢀ  
Resistanceꢀ  
(Input-Output)ꢀ  
RI-O  
HCPL-3120ꢀ  
HCPL-J312  
1012  
Ωꢀ  
VI-Oꢀ=ꢀ500ꢀVDCꢀ  
HCNW3120ꢀ 1012  
1013  
TAꢀ=ꢀ25°C  
TAꢀ=ꢀ100°C  
fꢀ=ꢀ1ꢀMHz  
1011ꢀ  
Capacitanceꢀ  
CI-O  
HCPL-3120ꢀ  
HCPL-J312ꢀ  
HCNW3120ꢀ  
0.6ꢀ  
0.8  
0.5ꢀ  
pFꢀ  
(Input-Output)ꢀ  
0.6  
LED-to-CaseꢀThermalꢀ  
Resistanceꢀ  
q
LCꢀ  
467ꢀ  
°C/Wꢀ  
Thermocoupleꢀ  
locatedꢀatꢀcenter  
28ꢀ  
LED-to-DetectorꢀThermalꢀ  
Resistanceꢀ  
q
LDꢀ  
442ꢀ  
°C/Wꢀ  
undersideꢀofꢀ  
package  
Detector-to-Caseꢀ  
ThermalꢀResistance  
qDCꢀ  
126ꢀ  
°C/Wꢀ  
*AllꢀtypicalsꢀatꢀT ꢀ=ꢀ25°C.  
A
**TheꢀInput-OutputꢀMomentaryꢀWithstandꢀVoltageꢀisꢀaꢀdielectricꢀvoltageꢀratingꢀthatꢀshouldꢀnotꢀbeꢀinterpretedꢀasꢀanꢀinput-outputꢀcontinuousꢀ  
voltageꢀrating.ꢀForꢀtheꢀcontinuousꢀvoltageꢀratingꢀreferꢀtoꢀyourꢀequipmentꢀlevelꢀsafetyꢀspecificationꢀorꢀAvagoꢀApplicationꢀNoteꢀ1074ꢀentitledꢀ“Op-  
tocouplerꢀInput-OutputꢀEnduranceꢀVoltage.”  
Notes:  
ꢀ 1.ꢀDerateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ0.3ꢀmA/°C.  
ꢀ 2.ꢀMaximumꢀpulseꢀwidthꢀ=ꢀ10ꢀµs,ꢀmaximumꢀdutyꢀcycleꢀ=ꢀ0.2%.ꢀThisꢀvalueꢀisꢀintendedꢀtoꢀallowꢀforꢀcomponentꢀtolerancesꢀforꢀdesignsꢀwithꢀI ꢀpeakꢀ  
O
minimumꢀ=ꢀ2.0ꢀA.ꢀSeeꢀApplicationsꢀsectionꢀforꢀadditionalꢀdetailsꢀonꢀlimitingꢀI ꢀpeak.  
OH  
ꢀ 3.ꢀDerateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ4.8ꢀmW/°C.  
ꢀ 4.ꢀDerateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ5.4ꢀmW/°C.ꢀTheꢀmaximumꢀLEDꢀjunctionꢀtem-peratureꢀshouldꢀnotꢀexceedꢀ125°C.  
ꢀ 5.ꢀMaximumꢀpulseꢀwidthꢀ=ꢀ50ꢀµs,ꢀmaximumꢀdutyꢀcycleꢀ=ꢀ0.5%.  
ꢀ 6.ꢀInꢀthisꢀtestꢀV ꢀisꢀmeasuredꢀwithꢀaꢀdcꢀloadꢀcurrent.ꢀWhenꢀdrivingꢀcapacitiveꢀloadsꢀV ꢀwillꢀapproachꢀV ꢀasꢀI ꢀapproachesꢀzeroꢀamps.  
OH  
OH  
CC  
OH  
ꢀ 7.ꢀMaximumꢀpulseꢀwidthꢀ=ꢀ1ꢀms,ꢀmaximumꢀdutyꢀcycleꢀ=ꢀ20%.  
ꢀ 8.ꢀInꢀaccordanceꢀwithꢀUL1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥4500ꢀVrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetec-  
tionꢀcurrentꢀlimit,ꢀI ꢀ≤ꢀ5ꢀµA).ꢀ  
I-O  
ꢀ 9.ꢀInꢀaccordanceꢀwithꢀUL1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥4500ꢀVrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetec-  
tionꢀcurrentꢀlimit,ꢀI ꢀ≤ꢀ5ꢀµA).  
I-O  
10.ꢀInꢀaccordanceꢀwithꢀUL1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥6000ꢀVrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetec-  
tionꢀcurrentꢀlimit,ꢀI ꢀ≤ꢀ5ꢀµA).  
I-O  
11.ꢀDeviceꢀconsideredꢀaꢀtwo-terminalꢀdevice:ꢀpinsꢀ1,ꢀ2,ꢀ3,ꢀandꢀ4ꢀshortedꢀtogetherꢀandꢀpinsꢀ5,ꢀ6,ꢀ7,ꢀandꢀ8ꢀshortedꢀtogether.  
12.ꢀTheꢀdifferenceꢀbetweenꢀt ꢀandꢀt ꢀbetweenꢀanyꢀtwoꢀHCPL-3120ꢀpartsꢀunderꢀtheꢀsameꢀtestꢀcondition.  
PHL  
PLH  
13.ꢀPinsꢀ1ꢀandꢀ4ꢀneedꢀtoꢀbeꢀconnectedꢀtoꢀLEDꢀcommon.  
14.ꢀCommonꢀmodeꢀtransientꢀimmunityꢀinꢀtheꢀhighꢀstateꢀisꢀtheꢀmaximumꢀtolerableꢀdV /dtꢀofꢀtheꢀcommonꢀmodeꢀpulse,ꢀV ,ꢀtoꢀassureꢀthatꢀtheꢀ  
CM  
CM  
outputꢀwillꢀremainꢀinꢀtheꢀhighꢀstateꢀ(i.e.,ꢀV ꢀ>ꢀ15.0  
V).  
O
15.ꢀCommonꢀmodeꢀtransientꢀimmunityꢀinꢀaꢀlowꢀstateꢀisꢀtheꢀmaximumꢀtolerableꢀdV /dtꢀofꢀtheꢀcommonꢀmodeꢀpulse,ꢀV ,ꢀtoꢀassureꢀthatꢀtheꢀout-  
CM  
CM  
putꢀwillꢀremainꢀinꢀaꢀlowꢀstateꢀ(i.e.,ꢀV ꢀ<ꢀ1.0  
V).  
O
16.ꢀThisꢀloadꢀconditionꢀapproximatesꢀtheꢀgateꢀloadꢀofꢀaꢀ1200ꢀV/75AꢀIGBT.  
17.ꢀPulseꢀWidthꢀDistortionꢀ(PWD)ꢀisꢀdefinedꢀasꢀ|t -t |ꢀforꢀanyꢀgivenꢀdevice.  
PHL PLH  
12  
0
-1  
-3  
3.0  
1.8  
1.6  
1.4  
-1  
-3  
-ꢀ  
-4  
I
I
V
V
= 7 to 16 mA  
I = 7 to 16 mA  
F
F
= -100 mA  
= 15 to ꢀ0 V  
= 0 V  
V
V
V
= (V  
- 4 Vꢁ  
CC  
OUT  
CC  
EE  
OUT  
CC  
EE  
100 °C  
35 °C  
-40 °C  
= 15 to ꢀ0 V  
= 0 V  
I
V
V
= 7 to 16 mA  
= 15 to ꢀ0 V  
-ꢀ  
-4  
F
CC  
1.3  
1.0  
-5  
-6  
= 0 V  
EE  
-40 -30  
0
30 40 60 80 100  
-40 -30  
0
30 40 60 80 100  
0
0.5  
1.0  
1.5  
3.0  
3.5  
T
– TEMPERATURE – °C  
T
– TEMPERATURE – °C  
I
– OUTPUT HIGH CURRENT – A  
OH  
A
A
Figure 1. VOH vs. temperature.  
Figure 2. IOH vs. temperature.  
Figure 3. VOH vs. IOH.  
0.35  
4
4
V
V
V
= -ꢀ.0 to 0.8 V  
= 15 to ꢀ0 V  
= 0 V  
F(OFFꢁ  
CC  
EE  
V
(OFFꢁ = -ꢀ.0 TO 0.8 V  
V
V
V
V
(OFFꢁ = -ꢀ.0 TO 0.8 V  
F
F
I
= 100 mA  
= 15 TO ꢀ0 V  
= 0 V  
= 3.5 V  
OUT  
OUT  
0.30  
0.15  
0.10  
V
V
= 15 TO ꢀ0 V  
= 0 V  
CC  
EE  
CC  
EE  
3
3
1
0
1
0
0.05  
0
100 °C  
35 °C  
-40 °C  
-40 -30  
0
30 40 60 80 100  
-40 -30  
0
30 40 60 80 100  
T – TEMPERATURE – °C  
A
0
0.5  
1.0  
1.5  
3.0  
3.5  
T
– TEMPERATURE – °C  
I
– OUTPUT LOW CURRENT – A  
A
OL  
Figure 4. VOL vs. temperature.  
Figure 5. IOL vs. temperature.  
Figure 6. VOL vs. IOL.  
ꢀ.5  
ꢀ.0  
3.5  
ꢀ.5  
ꢀ.0  
3.5  
I
I
I
I
CCH  
CCL  
CCH  
CCL  
V
V
= ꢀ0 V  
= 0 V  
= 10 mA for I  
CC  
EE  
I
I
T
= 10 mA for I  
CCH  
F
F
3.0  
1.5  
3.0  
1.5  
= 0 mA for I  
CCL  
I
I
F
F
CCH  
CCL  
= 35 °C  
A
EE  
= 0 mA for I  
V
= 0 V  
-40 -30  
0
30 40 60 80 100  
15  
30  
35  
ꢀ0  
T
– TEMPERATURE – °C  
V
CC  
– SUPPLY VOLTAGE – V  
A
Figure 7. ICC vs. temperature.  
Figure 8. ICC vs. VCC.  
13  
HCPL-Jꢀ13  
HCNWꢀ130  
HCPL-ꢀ130  
5
4
5
4
5
4
3
V
V
= 15 TO ꢀ0 V  
= 0 V  
OUTPUT = OPEN  
CC  
EE  
V
V
= 15 TO ꢀ0 V  
= 0 V  
OUTPUT = OPEN  
V
V
= 15 TO ꢀ0 V  
= 0 V  
OUTPUT = OPEN  
CC  
EE  
CC  
EE  
3
1
0
3
1
0
1
0
-40 -30  
0
30 40 60 80 100  
-40 -30  
0
30 40 60 80 100  
-40 -30  
0
30 40 60 80 100  
T
– TEMPERATURE – °C  
T
– TEMPERATURE – °C  
T
– TEMPERATURE – °C  
A
A
A
Figure 9. IFLH vs. temperature.  
500  
400  
ꢀ00  
500  
400  
ꢀ00  
500  
I
V
= 10 mA  
I
T
= 10 mA  
= 35 °C  
V
= ꢀ0 V, V  
= 0 V  
EE  
F
F
A
CC  
Rg = 10 , Cg = 10 nF  
= 35 °C  
T
T
PLH  
PHL  
= ꢀ0 V, V  
= 0 V  
EE  
CC  
Rg = 10 Ω  
Cg = 10 nF  
DUTY CYCLE = 50%  
f = 10 kHz  
T
Rg = 10 , Cg = 10 nF  
DUTY CYCLE = 50%  
f = 10 kHz  
A
400  
ꢀ00  
DUTY CYCLE = 50%  
f = 10 kHz  
300  
100  
300  
100  
300  
100  
T
T
T
T
PLH  
PHL  
PLH  
PHL  
6
8
10  
13  
14  
16  
15  
30  
35  
ꢀ0  
-40 -30  
0
30 40 60 80 100  
T – TEMPERATURE – °C  
A
I
– FORWARD LED CURRENT – mA  
V
– SUPPLY VOLTAGE – V  
F
CC  
Figure 10. Propagation delay vs. VCC.  
Figure 11. Propagation delay vs. IF.  
Figure 12. Propagation delay vs. temperature.  
500  
500  
V
T
= ꢀ0 V, V  
= 35 °C  
= 10 mA  
= 0 V  
EE  
= ꢀ0 V, V  
= 35 °C  
= 10 mA  
= 0 V  
EE  
CC  
A
CC  
A
I
F
400  
ꢀ00  
Cg = 10 nF  
400  
ꢀ00  
DUTY CYCLE = 50%  
f = 10 kHz  
300  
100  
300  
100  
T
T
T
T
PLH  
PHL  
PLH  
PHL  
0
10  
30  
ꢀ0  
40  
50  
0
30  
40  
60  
80  
100  
Rg – SERIES LOAD RESISTANCE – Ω  
Cg – LOAD CAPACITANCE – nF  
Figure 13. Propagation delay vs. Rg.  
Figure 14. Propagation delay vs. Cg.  
14  
HCPL-Jꢀ13  
ꢀ0  
ꢀ5  
35  
30  
15  
10  
ꢀ0  
35  
30  
15  
10  
5
5
0
0
0
I
1
3
4
5
0
1
3
4
5
– FORWARD LED CURRENT – mA  
F
I
– FORWARD LED CURRENT – mA  
F
Figure 15. Transfer characteristics.  
HCPL-Jꢀ13/HCNWꢀ130  
= 35°C  
HCPL-ꢀ130  
1000  
1000  
T
= 35°C  
A
T
A
100  
10  
100  
10  
I
I
F
F
+
+
V
F
V
F
1.0  
1.0  
0.1  
0.1  
0.01  
0.01  
0.001  
0.001  
1.10 1.30  
1.ꢀ0  
1.40  
1.50  
1.60  
1.3  
1.ꢀ  
1.4  
1.5  
1.6  
1.7  
V
– FORWARD VOLTAGE – VOLTS  
F
V
– FORWARD VOLTAGE – VOLTS  
F
Figure 16. Input current vs. forward voltage.  
1
3
8
0.1 µF  
+
4 V  
7
6
5
I
= 7 to  
F
V
= 15  
+
CC  
to ꢀ0 V  
16 mA  
4
I
OH  
Figure 17. IOH test circuit.  
15  
1
3
4
8
1
3
4
8
0.1 µF  
0.1 µF  
I
OL  
V
OH  
7
6
5
7
6
5
V
= 15  
+
CC  
to ꢀ0 V  
I
= 7 to  
F
V
= 15  
+
CC  
to ꢀ0 V  
16 mA  
3.5 V  
+
100 mA  
Figure 18. IOL Test circuit.  
Figure 19. VOH Test circuit.  
1
3
4
8
1
3
8
0.1 µF  
0.1 µF  
7
100 mA  
7
6
5
V
= 15  
V
= 15  
+
+
CC  
to ꢀ0 V  
CC  
I
F
V
> 5 V  
to ꢀ0 V  
O
4
6
5
V
OL  
Figure 20. VOL Test circuit.  
Figure 21. IFLH Test circuit.  
1
3
8
0.1 µF  
7
+
I
= 10 mA  
V
F
CC  
V
> 5 V  
O
4
6
5
Figure 22. UVLO test circuit.  
16  
1
3
4
8
7
6
5
I
0.1 µF  
F
I
= 7 to 16 mA  
F
V
= 15  
CC  
to ꢀ0 V  
+
t
t
f
r
500 Ω  
+
V
O
90%  
10 KHz  
50% DUTY  
CYCLE  
10 Ω  
10 nF  
50%  
10%  
V
OUT  
t
t
PHL  
PLH  
Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms.  
V
CM  
δV  
V
CM  
1
8
7
6
5
=
δt  
t  
I
F
0.1 µF  
A
B
0 V  
3
4
t  
+
+
V
5 V  
O
V
= ꢀ0 V  
CC  
V
V
OH  
OL  
V
O
SWITCH AT A: I = 10 mA  
F
V
O
SWITCH AT B: I = 0 mA  
F
+
V
= 1500 V  
CM  
Figure 24. CMR test circuit and waveforms.  
17  
lowꢀmaximumꢀV ꢀspecificationꢀofꢀ0.5V.ꢀTheꢀHCPL-3120ꢀ  
                                     
Applications Information  
3120onasmallPCboarddirectlyabovetheIGBT)ꢀcanꢀ  
eliminateꢀtheꢀneedꢀforꢀnegativeꢀIGBTꢀgateꢀdriveꢀinꢀmanyꢀ  
applicationsꢀasꢀshownꢀinꢀFigureꢀ25.ꢀCareꢀshouldꢀbeꢀtakenꢀ  
withsuchaPCboarddesigntoavoidroutingtheIGBTꢀ  
collectorꢀorꢀemitterꢀtracesꢀcloseꢀtoꢀtheꢀHCPL-3120ꢀinputꢀ  
asꢀ thisꢀ canꢀ resultꢀ inꢀ unwantedꢀ couplingꢀ ofꢀ transientꢀ  
signalsꢀintoꢀtheꢀHCPL-3120ꢀandꢀdegradeꢀperformance.ꢀ(Ifꢀ  
theꢀIGBTꢀdrainꢀmustꢀbeꢀroutedꢀnearꢀtheꢀHCPL-3120ꢀinput,ꢀ  
thenꢀtheꢀLEDꢀshouldꢀbeꢀreverse-biasedꢀwhenꢀinꢀtheꢀo ꢀ  
state,ꢀtoꢀpreventꢀtheꢀtransientꢀsignalsꢀcoupledꢀfromꢀtheꢀ  
IGBTꢀdrainꢀfromꢀturningꢀonꢀtheꢀHCPL-3120.)ꢀ  
EliminatingꢀNegativeꢀIGBTꢀGateꢀDriveꢀ(Discussionꢀappliesꢀ  
toꢀHCPL-3120,ꢀHCPL-J312,ꢀandꢀHCNW3120)  
Toꢀ keepꢀ theꢀ IGBTꢀ firmlyꢀ off,ꢀ theꢀ HCPL-3120ꢀ hasꢀ aꢀ veryꢀ  
OL  
realizesꢀ thisꢀ veryꢀ lowV byꢀ usingꢀ aꢀ DMOSꢀ transistorꢀ  
OL  
with1ꢀΩ(typical)onresistanceinitspulldowncircuit.ꢀ  
WhentheHCPL-3120isinthelowstate,theIGBTgateꢀ  
isꢀ shortedꢀ toꢀ theꢀ emitterꢀ byꢀ Rgꢀ +ꢀ 1ꢀΩ.ꢀ Minimizingꢀ Rgꢀ  
andꢀ theꢀ leadꢀ inductanceꢀ fromꢀ theꢀ HCPL-3120ꢀ toꢀ theꢀ  
IGBTꢀgateꢀandꢀemitterꢀ(possiblyꢀbyꢀmountingꢀtheꢀHCPL-  
HCPL-ꢀ130  
+5 V  
1
3
4
8
V
= 18 V  
CC  
+ HVDC  
370 Ω  
0.1 µF  
+
7
6
5
Rg  
Q1  
ꢀ-PHASE  
AC  
CONTROL  
INPUT  
74XXX  
OPEN  
COLLECTOR  
Q3  
- HVDC  
Figure 25. Recommended LED drive and application circuit.  
18  
TheꢀV ꢀvalueꢀofꢀ2Vꢀinꢀtheꢀpreviousꢀequationꢀisꢀaꢀcon-  
                       
Selectingꢀ theꢀ Gateꢀ Resistorꢀ (Rg)ꢀ toꢀ Minimizeꢀ IGBTꢀ Forꢀ theꢀ circuitꢀ inꢀ Figureꢀ 26ꢀ withꢀ I ꢀ (worstꢀ case)ꢀ =ꢀ  
F
Switchingꢀ Losses.ꢀ (Discussionꢀ appliesꢀ toꢀ HCPL-3120,ꢀ 16ꢀmA,Rg=8ꢀΩ,MaxDutyCycle=80%,Qg=500nC,ꢀ  
HCPL-J312ꢀandꢀHCNW3120)  
fꢀ=ꢀ20ꢀkHzꢀandꢀT ꢀmaxꢀ=ꢀ85ꢀ°C:  
A
Stepꢀ1:ꢀCalculateꢀRgꢀMinimumꢀfromꢀtheꢀI ꢀPeakꢀSpecifica- P ꢀ=ꢀ16ꢀmA1.8ꢀVꢀ0.8ꢀ=ꢀ23ꢀmW  
OL  
E
tion.ꢀTheꢀIGBTꢀandꢀRgꢀinꢀFigureꢀ26ꢀcanꢀbeꢀanalyzedꢀasꢀaꢀ  
simpleRCcircuitwithavoltagesuppliedbytheHCPL-  
3120.  
P ꢀ=ꢀ4.25ꢀmAꢀ20ꢀVꢀ+ꢀ5.2ꢀµꢀJꢀ20ꢀkHz  
O
ꢀ ꢀ=ꢀ85ꢀmWꢀ+ꢀ104ꢀmW  
(V ꢀ–ꢀV ꢀ-ꢀV )ꢀ  
ꢀ ꢀ=ꢀ189ꢀmWꢀ>ꢀ178ꢀmWꢀ(P  
ꢀ@ꢀ85°C  
CC  
EE  
OL  
O(MAX)  
Rgꢀ ≥ꢀ ———————ꢀꢀ  
ꢀ ꢀ I  
OLPEAKꢀ  
ꢀ ꢀ=ꢀ250ꢀmW-15C*4.8ꢀmW/C)  
(V ꢀ–ꢀV ꢀ-ꢀ2ꢀV)ꢀ  
CC  
EE  
=ꢀ ———————ꢀꢀ  
ꢀ ꢀ  
Theꢀvalueꢀofꢀ4.25ꢀmAꢀforꢀI ꢀinꢀtheꢀpreviousꢀequationꢀwasꢀ  
CC  
ꢀꢀꢀꢀꢀ I  
OLPEAKꢀ  
obtainedꢀbyꢀderatingꢀtheꢀI ꢀmaxꢀofꢀ5ꢀmAꢀ(whichꢀoccursꢀ  
CC  
(15ꢀVꢀ+ꢀ5ꢀVꢀ-ꢀ2ꢀV)ꢀ  
atꢀ-40°C)ꢀtoꢀI ꢀmaxꢀatꢀ85Cꢀ(seeꢀFigureꢀ7).  
CC  
=ꢀ ———————ꢀꢀ  
ꢀ ꢀ ꢀꢀꢀ  
ꢀꢀꢀ2.5ꢀAꢀ  
SinceꢀP ꢀforꢀthisꢀcaseꢀisꢀgreaterꢀthanꢀP  
,ꢀRgꢀmustꢀbeꢀ  
O(MAX)  
O
=ꢀ 7.2ꢀΩꢀ@ꢀ8ꢀΩ  
increasedꢀtoꢀreduceꢀtheꢀHCPL-3120ꢀpowerꢀdissipation.  
OL  
P
ꢀ ꢀ  
O(SWITCHINGꢀMAX)  
servativeꢀvalueꢀofꢀV ꢀatꢀtheꢀpeakꢀcurrentꢀofꢀ2.5Aꢀ(seeꢀ  
OL  
Figureꢀ6).ꢀAtꢀlowerꢀRgꢀvaluesꢀtheꢀvoltageꢀsuppliedꢀbyꢀ  
theꢀHCPL-3120ꢀisꢀnotꢀanꢀidealꢀvoltageꢀstep.ꢀThisꢀresultsꢀ  
inꢀlowerꢀpeakꢀcurrentsꢀ(moreꢀmargin)ꢀthanꢀpredictedꢀbyꢀ  
=ꢀP  
ꢀ-ꢀP  
O(MAX) O(BIAS)  
ꢀ ꢀ=ꢀ178ꢀmWꢀ-ꢀ85ꢀmW  
=ꢀ93ꢀmW  
thisꢀanalysis.ꢀWhenꢀnegativeꢀgateꢀdriveꢀisꢀnotꢀusedꢀV ꢀinꢀ  
EE  
theꢀpreviousꢀequationꢀisꢀequalꢀtoꢀzeroꢀvolts.  
ꢀ ꢀ  
ꢀP  
O(SWITCHINGMAX)  
E
=ꢀ ———————ꢀ  
SW(MAX)  
ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀfꢀ  
Stepꢀ2:ꢀCheckꢀtheꢀHCPL-3120ꢀPowerꢀDissipationꢀandꢀ  
IncreaseꢀRgꢀifꢀNecessary.ꢀTheꢀHCPL-3120ꢀtotalꢀpowerꢀ  
ꢀ ꢀ  
93ꢀmWꢀ  
ꢀ ꢀ  
=————ꢀ=ꢀ4.65ꢀµWꢀ  
dissipationꢀ(P )ꢀisꢀequalꢀtoꢀtheꢀsumꢀofꢀtheꢀemitterꢀpowerꢀ  
T
20ꢀkHz  
ꢀ ꢀ  
ꢀ ꢀ  
(P )ꢀandꢀtheꢀoutputꢀpowerꢀ(P ):  
E
O
P ꢀ=ꢀP ꢀ+ꢀP  
O
T
E
ForꢀQgꢀ=ꢀ500ꢀnC,ꢀfromꢀFigureꢀ27,ꢀaꢀvalueꢀofꢀE ꢀ=ꢀ4.65ꢀµWꢀ  
givesꢀaꢀꢀꢀRgꢀ=ꢀ10.3ꢀΩ.  
SW  
PEꢀ=ꢀI ꢀV ·ꢀDutyꢀCycle  
Fꢀ Fꢀ  
P ꢀ=ꢀP  
ꢀ+ꢀP  
O(BIAS) Oꢀ(SWITCHING)  
O
ꢀ ꢀ =ꢀI ꢀꢀ(V ꢀ-ꢀV )+ꢀE (R ,ꢀQ )ꢀꢀf  
CC  
CC  
EE  
SW  
G
G
HCPL-ꢀ130  
+5 V  
1
8
V
= 15 V  
CC  
+ HVDC  
370 Ω  
0.1 µF  
+
3
4
7
6
5
Rg  
Q1  
= -5 V  
ꢀ-PHASE  
AC  
CONTROL  
INPUT  
V
EE  
+
74XXX  
OPEN  
COLLECTOR  
Q3  
- HVDC  
Figure 26. HCPL-3120 typical application circuit with negative IGBT gate drive.  
19  
Thermal Model (Discussion applies to HCPL-3120, HCPL-  
J312 and HCNW3120)  
Theꢀ steadyꢀ stateꢀ thermalꢀ modelꢀ forꢀ theꢀ HCPL-3120ꢀ isꢀ  
shownꢀinꢀFigureꢀ28.ꢀTheꢀthermalꢀresistanceꢀvaluesꢀgivenꢀ  
inꢀthisꢀmodelꢀcanꢀbeꢀusedꢀtoꢀcalculateꢀtheꢀtemperaturesꢀ  
atꢀeachꢀnodeꢀforꢀaꢀgivenꢀoperatingꢀcondition.ꢀAsꢀshownꢀ  
P Parameter  
Description  
E
IFꢀ  
LEDꢀCurrent  
VFꢀ  
LEDꢀOnꢀVoltage  
MaximumꢀLEDꢀDutyꢀCycle  
byꢀtheꢀmodel,ꢀallꢀheatꢀgeneratedꢀflowsꢀthroughꢀq whichꢀ  
CAꢀ  
DutyꢀCycleꢀ  
raisesꢀ theꢀ caseꢀ temperatureꢀ T ꢀ accordingly.ꢀ Theꢀ valueꢀ  
C
ofq dependsontheconditionsoftheboarddesignꢀ  
CA  
andꢀis,ꢀtherefore,ꢀdeterminedꢀbyꢀtheꢀdesigner.ꢀTheꢀvalueꢀ  
P Parameter  
Description  
O
ofꢀ q ꢀ=ꢀ83°C/Wꢀ wasꢀ obtainedꢀ fromꢀ thermalꢀ measure-  
CA  
ICC  
SupplyꢀCurrent  
mentsꢀusingꢀaꢀ2.5ꢀxꢀ2.5ꢀinchꢀPCꢀboard,ꢀwithꢀsmallꢀtracesꢀ  
(noꢀgroundꢀplane),ꢀaꢀsingleꢀHCPL-3120ꢀsolderedꢀintoꢀtheꢀ  
centerꢀofꢀtheꢀboardꢀandꢀstillꢀair.ꢀTheꢀabsoluteꢀmaximumꢀ  
powerꢀ dissipationꢀ deratingꢀ specificationsꢀ assumeꢀ aꢀ  
VCC  
PositiveꢀSupplyꢀVoltage  
NegativeꢀSupplyꢀVoltage  
EnergyꢀDissipatedꢀinꢀtheꢀHCPL-3120ꢀ  
forꢀeachꢀIGBTꢀSwitchingꢀCycleꢀꢀ  
(SeeꢀFigureꢀ27)  
VEEꢀ  
ESW(Rg,Qg)ꢀ  
q valueꢀofꢀ83°C/W.  
CA  
FromꢀtheꢀthermalꢀmodeꢀinꢀFigureꢀ28ꢀtheꢀLEDꢀandꢀdetectorꢀ  
ICꢀjunctionꢀtemperaturesꢀcanꢀbeꢀexpressedꢀas:  
fꢀ  
SwitchingꢀFrequency  
@ꢀ  
T ꢀ=ꢀP (q ||(q ꢀ+ꢀq )ꢀ+ꢀq  
)
CA  
JE  
Eꢀ  
LC LD  
DC  
ꢀ ꢀ ꢀ ꢀ ꢀꢀq ꢀ*ꢀq  
LC  
DC  
14  
13  
10  
Qg = 100 nC  
Qg = 500 nC  
Qg = 1000 nC  
+ꢀP (———————ꢀꢀ+ꢀq )ꢀ+ꢀT  
A
D
CA  
ꢀ ꢀ ꢀꢀꢀ q ꢀ+ꢀq ꢀ+ꢀq  
LD  
LC  
DC  
V
V
= 19 V  
= -9 V  
CC  
EE  
ꢀ ꢀ ꢀ ꢀ ꢀ q q  
LC  
DC  
8
6
4
3
T ꢀ= P ꢀ(———————ꢀꢀ+ꢀq  
)
CA  
JD ꢀ E  
ꢀ ꢀ ꢀ ꢀꢀ ꢀ q ꢀ+ꢀq ꢀ+ꢀq  
LD  
LC  
DC  
+ꢀP (q ||(q ꢀ+ꢀq )ꢀ+ꢀq )ꢀ+ꢀT  
A
Dꢀ  
DC LD  
LC  
CA  
Insertingꢀtheꢀvaluesꢀforꢀq ꢀandꢀq ꢀshownꢀinꢀFigureꢀ28ꢀ  
gives:  
LC  
DC  
0
0
10  
30  
ꢀ0  
40  
50  
Rg – GATE RESISTANCE Ω  
T ꢀ=ꢀP (256°C/Wꢀ+ꢀq )ꢀ  
JE  
Eꢀ  
CA  
ꢀ ꢀꢀ+ꢀP (57°C/Wꢀ+ꢀq )ꢀ+ꢀT  
Dꢀ  
CA  
Aꢀ  
T ꢀ=ꢀP (57°C/Wꢀ+ꢀq )ꢀ  
JD  
Eꢀ  
CA  
Figure 27. Energy dissipated in the HCPL-3120 for each IGBT switching  
cycle.  
ꢀ ꢀꢀ+ꢀP (111°C/Wꢀ+ꢀq )ꢀ+ꢀT  
A
Dꢀ  
CA  
Forꢀexample,ꢀgivenꢀP ꢀ=ꢀ45ꢀmW,ꢀP ꢀ=ꢀ250ꢀmW,ꢀT ꢀ=ꢀ70°Cꢀ  
E
O
A
andꢀ q ꢀ=ꢀ83°C/W:  
CA  
TJEꢀ=ꢀPEꢀ339°C/Wꢀ+ꢀPDꢀ140°C/Wꢀ+ꢀTAꢀ  
ꢀ ꢀꢀ=ꢀ45ꢀmWꢀ339°C/Wꢀ+ꢀ250ꢀmWꢀ  
ꢀ ꢀ ꢀ  
140°C/Wꢀ+ꢀ70°Cꢀ=ꢀ120°C  
TJDꢀ=ꢀPEꢀ140°C/Wꢀ+ꢀPDꢀ194°C/Wꢀ+ꢀTAꢀ  
ꢀ ꢀꢀ=ꢀ45ꢀmWꢀ140°C/Wꢀ+ꢀ250ꢀmW194°C/Wꢀ+ꢀ70°Cꢀ=ꢀ125°C  
T ꢀ andꢀ T ꢀ shouldꢀ beꢀ limitedꢀ toꢀ 125°Cꢀ basedꢀ onꢀ theꢀ  
JE  
JD  
boardꢀlayoutꢀandꢀpartꢀplacementꢀ(q )ꢀspecificꢀtoꢀtheꢀap-  
CA  
plication.  
20  
θ
= 443 °C/W  
LD  
ꢀ T ꢀ =ꢀ LEDꢀjunctionꢀtemperatureꢀ  
ꢀ T ꢀ =ꢀ detectorꢀICꢀjunctionꢀtemperatureꢀ  
JD  
JE  
T
T
JD  
JE  
ꢀ T ꢀ =ꢀ caseꢀtemperatureꢀmeasuredꢀatꢀtheꢀcenterꢀofꢀtheꢀpackageꢀbottomꢀ  
C
θ
= 467 °C/W  
θ
= 136 °C/W  
DC  
LC  
q ꢀ =ꢀ LED-to-caseꢀthermalꢀresistanceꢀ  
LC  
T
C
q ꢀ =ꢀ LED-to-detectorꢀthermalꢀresistanceꢀ  
LD  
q ꢀ =ꢀ detector-to-caseꢀthermalꢀresistanceꢀ  
DC  
θ
= 8ꢀ °C/W*  
CA  
q ꢀ =ꢀ case-to-ambientꢀthermalꢀresistanceꢀ  
CA  
ꢀꢀꢀ*q ꢀwillꢀdependꢀonꢀtheꢀboardꢀdesignꢀandꢀtheꢀplacementꢀofꢀtheꢀpart.  
CA  
T
A
Figure 28. Thermal model.  
LED Drive Circuit Considerations for Ultra High CMR Per-  
formance. (Discussion applies to HCPL-3120, HCPL-J312,  
and HCNW3120)  
perturbationsꢀinꢀtheꢀLEDꢀcurrentꢀduringꢀcommonꢀmodeꢀ  
transientsꢀandꢀbecomesꢀtheꢀmajorꢀsourceꢀofꢀCMRꢀfailuresꢀ  
forꢀaꢀshieldedꢀoptocoupler.ꢀTheꢀmainꢀdesignꢀobjectiveꢀofꢀ  
aꢀhighꢀCMRꢀLEDꢀdriveꢀcircuitꢀbecomesꢀkeepingꢀtheꢀLEDꢀ  
inꢀ theꢀ properꢀ stateꢀ (onꢀ orꢀ o)ꢀ duringꢀ commonꢀ modeꢀ  
transients.Forexample,therecommendedapplicationꢀ  
circuitꢀ(Figureꢀ25),ꢀcanꢀachieveꢀ25ꢀkV/µsꢀCMRꢀwhileꢀmini-  
mizingꢀcomponentꢀcomplexity.  
Withoutꢀ aꢀ detectorꢀ shield,ꢀ theꢀ dominantꢀ causeꢀ ofꢀ op-  
tocouplerꢀ CMRꢀ failureꢀ isꢀ capacitiveꢀ couplingꢀ fromꢀ theꢀ  
inputsideoftheoptocoupler,throughthepackage,toꢀ  
theꢀdetectorꢀICꢀasꢀshownꢀinꢀFigureꢀ29.ꢀTheꢀꢀꢀꢀꢀHCPL-3120ꢀ  
improvesꢀCMRꢀperform-anceꢀbyꢀusingꢀaꢀdetectorꢀICꢀwithꢀ  
anꢀopticallyꢀtransparentꢀFaradayꢀshield,ꢀwhichꢀdivertsꢀtheꢀ  
capacitivelyꢀcoupledꢀcurrentꢀawayꢀfromꢀtheꢀsensitiveꢀICꢀ  
circuitry.ꢀHowever,ꢀthisꢀshieldꢀdoesꢀnotꢀeliminateꢀtheꢀca-  
pacitiveꢀcouplingꢀbetweenꢀtheꢀLEDꢀandꢀoptocouplerꢀpinsꢀ  
5-8ꢀasꢀshownꢀinꢀFigureꢀ30.ꢀThisꢀcapacitiveꢀcouplingꢀcausesꢀ  
Techniquesꢀ toꢀ keepꢀ theꢀ LEDꢀ inꢀ theꢀ properꢀ stateꢀ areꢀ  
discussedꢀinꢀtheꢀnextꢀtwoꢀsections.  
C
1
3
4
8
7
6
5
1
3
4
8
7
6
5
LEDO1  
C
C
C
C
LEDP  
LEDP  
C
LEDO3  
LEDN  
LEDN  
SHIELD  
Figure 29. Optocoupler input to output capacitance model for unshielded  
optocouplers.  
Figure 30. Optocoupler input to output capacitance model for shielded  
optocouplers.  
21  
(V ≤  
F
              
V
)ꢀ duringꢀ commonꢀ modeꢀ transients.ꢀ Forꢀ  
F(OFF)  
CMR with the LED On (CMR ).  
H
AꢀhighꢀCMRꢀLEDꢀdriveꢀcircuitꢀmustꢀkeepꢀtheꢀLEDꢀonꢀduringꢀ  
commonꢀmodeꢀtransients.ꢀThisꢀisꢀachievedꢀbyꢀoverdriv-  
ingꢀtheꢀLEDꢀcurrentꢀbeyondꢀtheꢀinputꢀthresholdꢀsoꢀthatꢀ  
itisnotpulledbelowthethresholdduringatransient.ꢀ  
Aꢀ minimumꢀ LEDꢀ currentꢀ ofꢀ 10ꢀ mAꢀ providesꢀ adequateꢀ  
R
ꢀandꢀV ꢀofꢀtheꢀlogicꢀgate.ꢀAsꢀlongꢀasꢀtheꢀlowꢀstateꢀ  
SAT  
SAT  
voltageꢀ developedꢀ acrossꢀ theꢀ logicꢀ gateꢀ isꢀ lessꢀ thanꢀ  
,theLEDwillremainoandnocommonmodeꢀ  
V
F(OFF)  
failureꢀwillꢀoccur.  
Theꢀ openꢀ collectorꢀ driveꢀ circuit,ꢀ shownꢀ inꢀ Figureꢀ 32,ꢀ  
cannotkeeptheLEDoduringa+dVcm/dttransient,ꢀ  
sinceꢀ allꢀ theꢀ currentꢀ flowingꢀ throughꢀ C  
marginꢀoverꢀtheꢀmaximumꢀI ꢀofꢀ5ꢀmAꢀtoꢀachieveꢀ25ꢀkV/  
FLH  
µsꢀCMR.  
ꢀ mustꢀ beꢀ  
LEDN  
suppliedꢀ byꢀ theꢀ LED,ꢀ andꢀ itꢀ isꢀ notꢀ recommendedꢀ forꢀ  
CMR with the LED Off (CMR ).  
L
applica-tionsꢀ requiringꢀ ultraꢀ highꢀ CMR ꢀ performance.ꢀ  
L
Aꢀ highꢀ CMRꢀ LEDꢀ driveꢀ circuitꢀ mustꢀ keepꢀ theꢀ LEDꢀ o ꢀ  
Figureꢀ33ꢀisꢀanꢀalternativeꢀdriveꢀcircuitꢀwhich,ꢀlikeꢀtheꢀrec-  
ommendedꢀapplica-tionꢀcircuitꢀ(Figureꢀ25),ꢀdoesꢀachieveꢀ  
ultraꢀhighꢀCMRꢀperformanceꢀbyꢀshuntingꢀtheꢀLEDꢀinꢀtheꢀ  
offꢀstate.  
example,duringa-dV /dttransientinFigure31,theꢀ  
cm  
currentꢀ flowingꢀ throughꢀ C  
ꢀ alsoꢀ flowsꢀ throughꢀ theꢀ  
LEDP  
+5 V  
1
8
0.1  
µF  
+
C
LEDP  
V
= 18 V  
CC  
3
7
6
5
+
1
3
4
8
7
6
5
I
LEDP  
V
SAT  
+5 V  
Q1  
C
LEDP  
4
• • •  
• • •  
C
LEDN  
Rg  
SHIELD  
C
I
LEDN  
LEDN  
* THE ARROWS INDICATE THE DIRECTION  
OF CURRENT FLOW DURING –dV /dt.  
SHIELD  
CM  
+
V
CM  
Figure 31. Equivalent circuit for figure 25 during common mode transient.  
Figure 32. Not recommended open collector drive circuit.  
14  
13  
(13.ꢀ, 10.8ꢁ  
1
3
4
8
7
6
5
10  
(10.7, 9.3ꢁ  
+5 V  
C
C
8
6
4
3
LEDP  
LEDN  
(10.7, 0.1ꢁ  
(13.ꢀ, 0.1ꢁ  
0
SHIELD  
0
5
10  
15  
30  
(V  
- V  
EE  
ꢁ – SUPPLY VOLTAGE – V  
CC  
Figure 33. Recommended LED drive circuit for ultra-high CMR.  
Figure 34. Under voltage lock out.  
22  
                      
                               
IPM Dead Time and Propagation Delay Specifications.  
(Discussion applies to HCPL-3120, HCPL-J312, and  
HCNW3120)  
Under Voltage Lockout Feature. (Discussion applies to  
HCPL-3120, HCPL-J312, and HCNW3120)  
TheꢀHCPL-3120ꢀcontainsꢀanꢀunderꢀvoltageꢀlockoutꢀ(UVLO)ꢀ  
featureꢀthatꢀisꢀdesignedꢀtoꢀprotectꢀtheꢀIGBTꢀunderꢀfaultꢀ  
conditionswhichꢀ causetheꢀ HCPL-3120supplyvoltageꢀ  
(equivalentꢀ toꢀ theꢀ fully-chargedꢀ IGBTꢀ gateꢀ voltage)ꢀ toꢀ  
dropꢀbelowꢀaꢀlevelꢀnecessaryꢀtoꢀkeepꢀtheꢀIGBTꢀinꢀaꢀlowꢀre-  
sistanceꢀstate.ꢀWhenꢀtheꢀHCPL-3120ꢀoutputꢀisꢀinꢀtheꢀhighꢀ  
stateꢀandꢀtheꢀsupplyꢀvoltageꢀdropsꢀbelowꢀtheꢀꢀꢀꢀꢀHCPL-  
TheꢀHCPL-3120ꢀincludesꢀaꢀPropagationꢀDelayꢀDifferenceꢀ  
(PDD)ꢀspecificationꢀintendedꢀtoꢀhelpꢀdesignersꢀminimizeꢀ  
“deadtime”intheirpowerinverterdesigns.Deadtimeꢀ  
isꢀtheꢀtimeꢀperiodꢀduringꢀwhichꢀbothꢀtheꢀhighꢀandꢀlowꢀ  
sidepowertransistors(Q1andQ2inFigure25)areoff.ꢀ  
AnyꢀoverlapꢀinꢀQ1ꢀandꢀQ2ꢀconductionꢀwillꢀresultꢀinꢀlargeꢀ  
currentsꢀ flowingꢀ throughꢀ theꢀ powerꢀ devicesꢀ betweenꢀ  
theꢀhighꢀandꢀlowꢀvoltageꢀmotorꢀrails.  
3120ꢀ V ꢀ thresholdꢀ (9.5ꢀ<  
UVLO–  
V
<ꢀ 12.0)ꢀ theꢀ opto-  
UVLO–ꢀ  
coupleroutputwillgointothelowstatewithatypicalꢀ  
delay,ꢀUVLOꢀTurnꢀOffꢀDelay,ꢀofꢀ0.6ꢀµs.  
Whenꢀ theꢀ HCPL-3120ꢀ outputꢀ isꢀ inꢀ theꢀ lowꢀ stateꢀ andꢀ  
theꢀ supplyꢀ voltageꢀ risesꢀ aboveꢀ theꢀ HCPL-3120ꢀ V  
UVLO+  
thresholdꢀ(11.0ꢀ<  
V
ꢀ<ꢀ13.5)ꢀtheꢀoptocouplerꢀoutputꢀ  
UVLO+  
willꢀgoꢀintoꢀtheꢀhighꢀstateꢀ(assumesꢀLEDꢀisꢀ“ON”)ꢀwithꢀaꢀ  
typicalꢀdelay,ꢀUVLOꢀTurnꢀOnꢀDelayꢀofꢀ0.8ꢀµs.  
I
LED1  
I
LED1  
V
OUT1  
V
Q1 ON  
OUT1  
Q1 ON  
Q1 OFF  
Q3 ON  
Q1 OFF  
Q3 ON  
Q3 OFF  
V
Q3 OFF  
OUT3  
V
OUT3  
I
LED3  
I
LED3  
t
PHL MAX  
t
PHL MIN  
t
PLH MIN  
t
PHL MAX  
t
PLH  
MIN  
PDD* MAX = (t - t  
= t  
- t  
PHL MAX PLH MIN  
PHL PLH MAX  
*PDD = PROPAGATION DELAY DIFFERENCE  
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS  
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.  
t
PLH MAX  
(t  
t
PHL- PLH MAX  
PDD* MAX  
MAXIMUM DEAD TIME  
Figure 35. Minimum LED skew for zero dead time.  
(DUE TO OPTOCOUPLERꢁ  
= (t  
= (t  
- t  
ꢁ + (t  
- t  
PHL MAX PHL MIN  
PLH MAX PLH MIN  
- t ꢁ – (t  
- t ꢁ  
PHL MAX PLH MIN  
PHL MIN PLH MAX  
= PDD* MAX – PDD* MIN  
*PDD = PROPAGATION DELAY DIFFERENCE  
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION  
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.  
Figure 36. Waveforms for dead time.  
23  
Toꢀminimizeꢀdeadꢀtimeꢀinꢀaꢀgivenꢀdesign,ꢀtheꢀturnꢀonꢀofꢀ deadꢀtimeꢀwillꢀbe.ꢀTheꢀmaximumꢀdeadꢀtimeꢀisꢀequivalentꢀ  
LED2ꢀshouldꢀbeꢀdelayedꢀ(relativeꢀtoꢀtheꢀturnꢀoffꢀofꢀLED1)ꢀ toꢀtheꢀdifferenceꢀbetweenꢀtheꢀmaximumꢀandꢀminimumꢀ  
sothatunderworst-casecon-ditions,transistorQ1hasꢀ propagationꢀdelayꢀdifferenceꢀspecificationsꢀasꢀshownꢀinꢀ  
justꢀturnedꢀoffꢀwhenꢀtransistorꢀQ2ꢀturnsꢀon,ꢀasꢀshownꢀinꢀ Figureꢀ36.ꢀTheꢀmaximumꢀdeadꢀtimeꢀforꢀtheꢀHCPL-3120ꢀisꢀ  
Figureꢀ35.ꢀTheꢀamountꢀofꢀdelayꢀnecessaryꢀtoꢀachieveꢀthisꢀ 700ꢀns(=350ꢀns-ꢀ(-350ꢀns))overanoperatingtempera-  
conditionsꢀisꢀequalꢀtoꢀtheꢀmaximumꢀvalueꢀofꢀtheꢀpropa- tureꢀrangeꢀofꢀ-40°Cꢀtoꢀ100°C.  
gationdelaydifferencespecification,PDD  
specifiedtobe350ꢀnsovertheoperatingtemperatureꢀ  
rangeꢀofꢀ-40°Cꢀtoꢀ100°C.  
,whichisꢀ  
MAX  
NoteꢀthatꢀtheꢀpropagationꢀdelaysꢀusedꢀtoꢀcalculateꢀPDDꢀ  
andꢀdeadꢀtimeꢀareꢀtakenꢀatꢀequalꢀtemperaturesꢀandꢀtestꢀ  
conditionssincetheoptocouplersunderconsiderationꢀ  
DelayingtheLEDsignalbythemaximumpropagationꢀ aretypicallymountedincloseproximitytoeachotherꢀ  
delayꢀdifferenceꢀensuresꢀthatꢀtheꢀminimumꢀdeadꢀtimeꢀisꢀ andꢀareꢀswitchingꢀidenticalꢀIGBTs.  
zero,ꢀbutꢀitꢀdoesꢀnotꢀtellꢀaꢀdesignerꢀwhatꢀtheꢀmaximumꢀ  
HCNWꢀ130  
(mWꢁ  
HCPL-ꢀ130 OPTION 060éHCPL-Jꢀ13  
1000  
800  
700  
600  
500  
400  
ꢀ00  
P
I
(mWꢁ  
P
I
S
S
900  
800  
700  
600  
500  
400  
ꢀ00  
300  
(mAꢁ  
(mAꢁ FOR HCPL-ꢀ130  
S
S
OPTION 060  
I
(mAꢁ FOR HCPL-Jꢀ13  
S
300  
100  
0
100  
0
0
35 50 75 100 135 150 175 300  
– CASE TEMPERATURE – °C  
0
35  
50 75 100 135 150 175  
T
T
– CASE TEMPERATURE – °C  
S
S
Figure 37. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-2.  
For product information and a complete list of distributors, please go to our website: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.  
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes AV01-0622EN  
AV02-0161EN - July 4, 2008  
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