HCPL-3120应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

H

2.0 Amp Output Current IGBT

Gate Drive Optocoupler

Technical Data

HCPL-3120

Features

• 2.0 A Minimum Peak Output

Current

• 15 kV/µs Minimum Common

Mode Rejection (CMR) at

V_CM= 1500 V

• 0.5 V Maximum Low Level

Output Voltage (V_OL)

Eliminates Need for

Negative Gate Drive

• I_CC= 5 mA Maximum Supply

Current

• Under Voltage Lock-Out

Protection (UVLO) with

Hysteresis

• Industrial Inverters

• Switch Mode Power Supplies

(SMPS)

motor control inverter applica-

tions. The high operating voltage

range of the output stage pro-

vides the drive voltages required

by gate controlled devices. The

voltage and current supplied by

this optocoupler makes it ideally

suited for directly driving IGBTs

with ratings up to 1200 V/100 A.

For IGBTs with higher ratings,

the HCPL-3120 can be used to

drive a discrete power stage

Description

The HCPL-3120 consists of a

GaAsP LED optically coupled to

an integrated circuit with a power

output stage. This optocoupler is

ideally suited for driving power

IGBTs and MOSFETs used in

which drives the IGBT gate.

Functional Diagram

• Wide Operating V_CCRange:

15 to 30 Volts

• 500 ns Maximum Switching

Speeds

• Industrial Temperature

Range: -40°C to 100°C

• Safety Approval

UL Recognized - 2500 V rms

for 1 minute per UL1577

CSA Approval

N/C

ANODE

CATHODE

N/C

1

8

V

CC

2

3

4

7

6

5

O

EE

SHIELD

VDE 0884 Approved with

TRUTH TABLE

V_IORM= 630 V peak

V_CC- V_EE

(Option 060 only)

“POSITIVE GOING” “NEGATIVE GOING”

LED

OFF

ON

(i.e., TURN-ON)

0 - 30 V

(i.e., TURN-OFF)

0 - 30 V

V_O

LOW

Applications

• Isolated IGBT/MOSFET

Gate Drive

• AC and Brushless DC Motor

Drives

0 - 11 V

0 - 9.5 V

LOW

ON

11 - 13.5 V

13.5 - 30 V

9.5 - 12 V

12 - 30 V

TRANSITION

HIGH

ON

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component

to prevent damage and/or degradation which may be induced by ESD.

5965-4779E

1-182

Ordering Information

Specify Part Number followed by Option Number (if desired)

Example

HCPL-3120#XXX

No Option = Standard DIP Package, 50 per tube.

060 = VDE 0884 V_IORM= 630 Vpeak Option, 50 per tube.

300 = Gull Wing Surface Mount Option, 50 per tube.

500 = Tape and Reel Packaging Option, 1000 per reel.

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.

9.40 (0.370)

9.90 (0.390)

Package Outline Drawings

Standard DIP Package

8

1

7

6

5

0.20 (0.008)

0.33 (0.013)

OPTION CODE*

DATE CODE

6.10 (0.240)

6.60 (0.260)

HP 3120Z

YYWW

7.36 (0.290)

7.88 (0.310)

5° TYP.

2

3

4

PIN ONE

1.78 (0.070) MAX.

1.19 (0.047) MAX.

4.70 (0.185) MAX.

DIMENSIONS IN MILLIMETERS AND (INCHES).

PIN DIAGRAM

*MARKING CODE LETTER FOR OPTION NUMBERS.

PIN ONE

0.51 (0.020) MIN.

2.92 (0.115) MIN.

"V" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

1

V

8

DD1

DD2

2

V

7

IN+

IN–

OUT+

OUT–

0.76 (0.030)

1.40 (0.055)

0.65 (0.025) MAX.

3

4

6

5

2.28 (0.090)

2.80 (0.110)

GND1 GND2

Gull Wing Surface Mount Option 300

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25

(0.380 ± 0.010)

1.016 (0.040)

1.194 (0.047)

7

6

5

8

4.826

TYP.

(0.190)

HP 3120Z

YYWW

6.350 ± 0.25

(0.250 ± 0.010)

9.398 (0.370)

9.906 (0.390)

1

3

2

4

MOLDED

0.381 (0.015)

0.635 (0.025)

1.194 (0.047)

1.778 (0.070)

9.65 ± 0.25

(0.380 ± 0.010)

1.780

(0.070)

MAX.

1.19

7.62 ± 0.25

(0.047)

MAX.

(0.300 ± 0.010)

0.20 (0.008)

0.33 (0.013)

4.19

MAX.

(0.165)

0.635 ± 0.25

(0.025 ± 0.010)

1.080 ± 0.320

(0.043 ± 0.013)

0.635 ± 0.130

(0.025 ± 0.005)

12° NOM.

2.540

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01

xx.xxx = 0.005

LEAD COPLANARITY

MAXIMUM: 0.102 (0.004)

1-183

Reflow Temperature Profile

Regulatory Information

The HCPL-3120 has been

approved by the following

organizations:

260

240

220

∆T = 145°C, 1°C/SEC

∆T = 115°C, 0.3°C/SEC

200

180

160

140

120

100

UL

Recognized under UL 1577,

Component Recognition

Program, File E55361.

80

∆T = 100°C, 1.5°C/SEC

60

40

20

0

CSA

Approved under CSA Component

Acceptance Notice #5, File CA

88324.

0

1

2

3

4

5

6

7

8

9

10

11

12

TIME – MINUTES

VDE (Option 060 Only)

MAXIMUM SOLDER REFLOW THERMAL PROFILE

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

Approved under VDE 0884/06.92

with V_IORM= 630 V peak.

VDE 0884 Insulation Characteristics (Option 060 Only)

Description

Symbol

Characteristic Unit

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 V rms

for rated mains voltage ≤ 450 V rms

I-IV

I-III

Climatic Classification

Pollution Degree (DIN VDE 0110/1.89)

55/100/21

2

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

V

630

Vpeak

IORM

V

IORM

x 1.875 = V , 100% Production Test with t = 1 sec,

V

PR

1181

PR

m

Partial discharge <5 pC

Input to Output Test Voltage, Method a*

V

x 1.5 = V , Type and Sample Test, t = 60 sec,

V

PR

945

Vpeak

IORM

PR

m

Partial discharge <5 pC

Highest Allowable Overvoltage*

V

IOTM

6000

(Transient Overvoltage t = 10 sec)

ini

Safety Limiting Values–Maximum Values Allowed in the Event

of a Failure, Also See Figure 37, Thermal Derating Curve.

Case Temperature

Input Current

Output Power

T

175

230

600

°C

mA

mW

S

I

P

S, INPUT

S, OUTPUT

9

Insulation Resistance at T , V = 500 V

R

S

≥ 10

Ω

S

IO

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884) for a

detailed description of Method a and Method b partial discharge test profiles.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in

application.

1-184

Insulation and Safety Related Specifications

Parameter

Symbol Value Units

Conditions

Minimum External Air

Gap (External

Clearance)

Minimum External

Tracking (External

Creepage)

Minimum Internal Plastic

Gap (Internal Clearance)

L(101)

7.1

mm

Measured from input terminals to output terminals,

shortest distance through air.

L(102)

7.4

Measured from input terminals to output terminals,

shortest distance path along body.

0.08

200

Insulation thickness between emitter and detector;

also known as distance through insulation.

Tracking Resistance

(Comparative Tracking

Index)

CTI

Volts DIN IEC 112/VDE 0303 Part 1

Isolation Group

IIIa

Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter

Storage Temperature

Operating Temperature

Average Input Current

Symbol

T_S

T_A

I_F(AVG)

Min.

-55.

-40

Max.

125

100

25

Units

°C

Note

mA

1

Peak Transient Input Current

(<1 µs pulse width, 300 pps)

Reverse Input Voltage

“High” Peak Output Current

“Low” Peak Output Current

Supply Voltage

I_F(TRAN)

V_R

I_OH(PEAK)

I_OL(PEAK)

(V_CC- V_EE)

V_O

1.0

5

2.5

35

V_CC

250

295

A

Volts

A

2

A

0

Volts

mW

Output Voltage

Output Power Dissipation

Total Power Dissipation

Lead Solder Temperature

Solder Reflow Temperature Profile

P_O

P_T

3

4

260°C for 10 sec., 1.6 mm below seating plane

See Package Outline Drawings section

Recommended Operating Conditions

Parameter

Symbol

(V_CC- V_EE)

I_F(ON)

V_F(OFF)

T_A

Min.

15

7

-3.0

-40

Max.

30

16

0.8

100

Units

Volts

mA

V

Power Supply Voltage

Input Current (ON)

Input Voltage (OFF)

Operating Temperature

°C

1-185

Electrical Specifications (DC)

Over recommended operating conditions (T_A= -40 to 100°C, I_F(ON)= 7 to 16 mA, V_F(OFF)= -3.0 to 0.8 V,

V_CC= 15 to 30 V, V_EE= Ground) unless otherwise specified.

Parameter

High Level

Output Current

Symbol

Min.

0.5

2.0

0.5

2.0

Typ.* Max. Units

Test Conditions

V_O= (V_CC- 4 V)

V_O= (V_CC- 15 V)

V_O= (V_EE+ 2.5 V)

V_O= (V_EE+ 15V)

I_O= -100 mA

Fig.

2, 3,

17

5, 6,

18

1, 3,

19

4, 6,

20

Note

5

2

5

2

I_OH

1.5

A

V

Low Level

Output Current

I_OL

2.0

High Level Output

Voltage

Low Level Output

Voltage

High Level Supply

Current

Low Level Supply

Current

V_OH

V_OL

(V_CC- 4) (V_CC- 3)

6, 7

0.1

2.0

2.3

0.5

5.0

V

I_O= 100 mA

I_CCH

I_CCL

I_FLH

mA

Output Open,

I_F= 7 to 16 mA

Output Open,

V_F= -3.0 to +0.8 V

I_O= 0 mA,

V_O> 5 V

7, 8

Threshold Input

Current Low to High

9, 15,

21

Threshold Input

Voltage High to Low

Input Forward

Voltage

V_FHL

V_F

0.8

1.2

V

1.5

1.8

I_F= 10 mA

16

Temperature

∆V_F/∆T_A

-1.6

mV/°C I_F= 10 mA

Coefficient

of Forward Voltage

Input Reverse

BV_R

5

V

Ir = 10 µA

Breakdown Voltage

Input Capacitance

UVLO Threshold

C_IN

V_UVLO+

V_UVLO–

60

pF

V

f = 1 MHz, V_F= 0 V

V_O> 5 V, I_F= 10 mA 22, 36

11.0

9.5

12.3

10.7

1.6

13.5

12.0

UVLO Hysteresis

UVLO_HYS

* All typical values at T_A= 25°C and V_CC- V_EE= 30 V, unless otherwise noted.

1-186

Switching Specifications (AC)

Over recommended operating conditions (T_A= -40 to 100°C, I_F(ON)= 7 to 16 mA, V_F(OFF)= -3.0 to 0.8 V,

V_CC= 15 to 30 V, V_EE= Ground) unless otherwise specified.

Parameter

Symbol

Min. Typ.* Max. Units

Test Conditions

Fig.

Note

Propagation Delay

Time to High

Output Level

t_PLH

0.10

0.30

0.50

µs

Rg = 10 Ω,

Cg = 10 nF,

f = 10 kHz,

10, 11,

12, 13

14, 23

14

Duty Cycle = 50%

Propagation Delay

Time to Low

t_PHL

0.10

0.27

0.50

µs

Output Level

Pulse Width

Distortion

Propagation Delay (t_PHL- t_PLH) -0.35

PWD

0.3

µs

15

10

0.35

34,35

Difference Between

Any Two Parts

PDD

Rise Time

Fall Time

UVLO Turn On

Delay

UVLO Turn Off

Delay

Output High Level

Common Mode

Transient

t_r

t_f

0.1

0.8

µs

23

22

t_{UVLO ON}

V_O> 5 V, I_F= 10 mA

V_O< 5 V, I_F= 10 mA

t_{UVLO OFF}

|CM_H|

0.6

30

15

kV/µs T_A= 25°C,

I_F= 10 to 16 mA,

24

11, 12

11, 13

V_CM= 1500 V,

V_CC= 30 V

Immunity

Output Low Level

Common Mode

Transient

|CM_L|

30

kV/µs T_A= 25°C,

V_CM= 1500 V,

V_F= 0 V,

Immunity

V_CC= 30 V

*All typical values at T_A= 25°C and V_CC- V_EE= 30 V, unless otherwise noted.

Package Characteristics

Parameter

Symbol

Min.

Typ.

Max. Units

Test Conditions

Fig.

Note

Input-Output

V

ISO

2500

V_RMSRH < 50%,

8, 9

Momentary

t = 1 min.,

Withstand Voltage**

Resistance

(Input - Output)

Capacitance

(Input - Output)

LED-to-Case

Thermal Resistance

LED-to-Detector

T_A= 25°C

R_I-O

C_I-O

θ_LC

θ_LD

θ_DC

10¹²

0.6

Ω

V_I-O= 500 V_DC

9

pF

f = 1 MHz

467

442

126

°C/W Thermocoupler

28

located at center

underside of

package

°C/W

Thermal Resistance

Detector-to-Case

Thermal Resistance

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note

1074 entitled “Optocoupler Input-Output Endurance Voltage.”

1-187

Notes:

loads V_OHwill approach V_CCas I_OH

approaches zero amps.

10. The difference between t_PHLand t_PLH

between any two HCPL-3120 parts

under the same test condition.

11. Pins 1 and 4 need to be connected to

LED common.

12. Common mode transient immunity in

the high state is the maximum

tolerable dV_CM/dt of the common

mode pulse, V_CM, to assure that the

output will remain in the high state

(i.e., V_O> 15.0 V).

13. Common mode transient immunity in

a low state is the maximum tolerable

dV_CM/dt of the common mode pulse,

V_CM, to assure that the output will

remain in a low state (i.e., V_O< 1.0 V).

14. This load condition approximates the

gate load of a 1200V/75A IGBT.

15. Pulse Width Distortion (PWD) is

defined as |t_PHL-t_PLH| for any given

device.

1. Derate linearly above 70°C free-air

temperature at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 µs,

maximum duty cycle = 0.2%. This

value is intended to allow for

component tolerances for designs

with I_Opeak minimum = 2.0 A. See

Applications section for additional

details on limiting I_OHpeak.

3. Derate linearly above 70°C free-air

temperature at a rate of 4.8 mW/°C.

4. Derate linearly above 70°C free-air

temperature at a rate of 5.4 mW/°C.

The maximum LED junction tempera-

ture should not exceed 125°C.

5. Maximum pulse width = 50 µs,

maximum duty cycle = 0.5%.

7. Maximum pulse width = 1 ms,

maximum duty cycle = 20%.

8. In accordance with UL1577, each

optocoupler is proof tested by

applying an insulation test voltage

≥ 3000 Vrms for 1 second (leakage

detection current limit, I_I-O≤ 5 µA).

This test is performed before the

100% production test for partial

discharge (method b) shown in the

VDE 0884 Insulation Characteristic

Table, if applicable.

9. Device considered a two-terminal

device: pins 1, 2, 3, and 4 shorted

together and pins 5, 6, 7, and 8

shorted together.

6. In this test V_OHis measured with a dc

load current. When driving capacitive

0

-1

2.0

I

V

= 7 to 16 mA

= -100 mA

I

= 7 to 16 mA

F

OUT

F

V

= (V

- 4 V)

OUT

CC

100 °C

25 °C

-40 °C

= 15 to 30 V

= 0 V

= 15 to 30 V

= 0 V

CC

EE

CC

EE

1.8

1.6

1.4

-2

-3

-4

-1

-2

I

V

= 7 to 16 mA

= 15 to 30 V

F

CC

-3

-4

1.2

1.0

-5

-6

= 0 V

EE

-40 -20

0

20 40 60 80 100

-40 -20

0

20 40 60 80 100

0

0.5

1.0

1.5

2.0

2.5

T

– TEMPERATURE – °C

T

– TEMPERATURE – °C

I

– OUTPUT HIGH CURRENT – A

OH

A

Figure 1. V_OHvs. Temperature.

Figure 2. I_OHvs. Temperature.

Figure 3. V_OHvs. I_OH

.

0.25

4

V

I

= -3.0 to 0.8 V

V

= -3.0 to 0.8 V

V

= -3.0 to 0.8 V

= 15 to 30 V

= 0 V

F(OFF)

= 100 mA

F(OFF)

= 2.5 V

F(OFF)

CC

EE

OUT

V

= 15 to 30 V

= 0 V

= 15 to 30 V

= 0 V

CC

EE

0.20

0.15

0.10

CC

EE

V

3

2

3

2

1

0

1

0

0.05

0

100 °C

25 °C

-40 °C

-40 -20

0

20 40 60 80 100

0

0.5

1.0

1.5

2.0

2.5

-40 -20

0

20 40 60 80 100

T

– TEMPERATURE – °C

I

– OUTPUT LOW CURRENT – A

T

– TEMPERATURE – °C

A

OL

A

Figure 4. V_OLvs. Temperature.

Figure 5. I_OLvs. Temperature.

Figure 6. V_OLvs. I_OL.

1-188

3.5

3.0

2.5

3.5

3.0

2.5

5

4

3

2

V

= 15 TO 30 V

= 0 V

CC

EE

I

CCH

CCL

CCH

CCL

OUTPUT = OPEN

V

= 30 V

= 0 V

= 10 mA for I

CC

EE

I

T

= 10 mA for I

CCH

F

2.0

1.5

2.0

1.5

= 0 mA for I

CCL

1

0

I

F

CCH

= 25 °C

A

EE

= 0 mA for I

CCL

V

= 0 V

15

20

– SUPPLY VOLTAGE – V

25

30

-40 -20

0

20 40 60 80 100

-40 -20

0

20 40 60 80 100

– TEMPERATURE – °C

T

– TEMPERATURE – °C

T

V

A

CC

Figure 7. I_CCvs. Temperature.

Figure 8. I_CCvs. V_CC

.

Figure 9. I_FLHvs. Temperature.

500

I

T

= 10 mA

V

= 30 V, V

= 0 V

I = 10 mA

F

CC

Rg = 10 Ω, Cg = 10 nF

DUTY CYCLE = 50%

f = 10 kHz

F

CC

Rg = 10 Ω, Cg = 10 nF

= 25 °C

EE

T

PLH

PHL

= 25 °C

V

= 30 V, V

= 0 V

EE

A

Rg = 10 W

Cg = 10 nF

DUTY CYCLE = 50%

f = 10 kHz

T

A

400

300

400

300

400

300

DUTY CYCLE = 50%

f = 10 kHz

200

100

200

100

200

100

T

PLH

PHL

PLH

PHL

6

8

10

12

14

16

15

20

25

30

-40 -20

0

20 40 60 80 100

I

– FORWARD LED CURRENT – mA

V

– SUPPLY VOLTAGE – V

T

– TEMPERATURE – °C

F

CC

A

Figure 10. Propagation Delay vs. V_CC

.

Figure 11. Propagation Delay vs. I_F.

Figure 12. Propagation Delay vs.

Temperature.

500

30

V

T

= 30 V, V

= 25 °C

= 10 mA

= 0 V

EE

V

T

= 30 V, V

= 25 °C

= 10 mA

= 0 V

EE

CC

A

CC

A

25

20

15

10

I

F

400

300

Cg = 10 nF

400

300

Rg = 10 Ω

DUTY CYCLE = 50%

f = 10 kHz

DUTY CYCLE = 50%

f = 10 kHz

200

100

200

100

5

0

T

PLH

PHL

PLH

PHL

0

20

40

60

80

100

0

I

1

2

3

4

5

0

10

20

30

40

50

Cg – LOAD CAPACITANCE – nF

– FORWARD LED CURRENT – mA

Rg – SERIES LOAD RESISTANCE – Ω

F

Figure 13. Propagation Delay vs. Rg.

Figure 14. Propagation Delay vs. Cg.

Figure 15. Transfer Characteristics.

1-189

1000

T

= 25°C

A

100

10

I

F

1

2

3

4

8

+

V

F

0.1 µF

–

+

–

1.0

0.1

4 V

7

6

5

I

= 7 to

16 mA

F

V

= 15

+

–

CC

to 30 V

0.01

I

OH

0.001

1.10 1.20

1.30

1.40

1.50

1.60

V

– FORWARD VOLTAGE – VOLTS

F

Figure 16. Input Current vs. Forward

Voltage.

Figure 17. I_OHTest Circuit.

1

2

3

4

8

1

8

0.1 µF

I

OL

V

OH

2

7

6

5

7

6

5

V

= 15

+

–

CC

to 30 V

I

= 7 to

16 mA

F

V

= 15

+

–

CC

to 30 V

2.5 V

+

3

4

–

100 mA

Figure 18. I_OLTest Circuit.

Figure 19. V_OHTest Circuit.

1

2

3

4

8

1

2

8

0.1 µF

100 mA

7

6

5

7

6

5

V

= 15

V

= 15

+

–

+

–

CC

to 30 V

CC

I

F

V

> 5 V

to 30 V

O

3

4

V

OL

Figure 21. I_FLHTest Circuit.

Figure 20. V_OLTest Circuit.

1

2

8

0.1 µF

7

+

I

= 10 mA

V

F

CC

–

V

> 5 V

O

3

4

6

5

Figure 22. UVLO Test Circuit.

1-190

1

2

3

4

8

7

6

5

I

0.1 µF

F

I

= 7 to 16 mA

F

V

= 15

CC

to 30 V

+

–

t

f

r

500 Ω

+

V

O

–

90%

10 KHz

50% DUTY

CYCLE

10 Ω

10 nF

50%

10%

V

OUT

t

PHL

PLH

Figure 23. t_PLH, t_PHL, t_r, and t_fTest Circuit and Waveforms.

V

CM

δV

δt

V

CM

1

2

3

4

8

7

6

5

=

∆t

I

F

0.1 µF

A

B

0 V

∆t

+

–

+

–

V

O

5 V

V

= 30 V

CC

V

OH

V

O

SWITCH AT A: I = 10 mA

F

V

O

OL

SWITCH AT B: I = 0 mA

F

+

V

= 1500 V

CM

Figure 24. CMR Test Circuit and Waveforms.

IGBT collector or emitter traces

close to the HCPL-3120 input as

this can result in unwanted

coupling of transient signals into

the HCPL-3120 and degrade

performance. (If the IGBT drain

must be routed near the HCPL-

3120 input, then the LED should

be reverse-biased when in the off

state, to prevent the transient

signals coupled from the IGBT

drain from turning on the

Applications Information

Eliminating Negative IGBT

Gate Drive

To keep the IGBT firmly off, the

HCPL-3120 has a very low

maximum V_OLspecification of

0.5 V. The HCPL-3120 realizes

this very low V_OLby using a

DMOS transistor with 1 Ω

gate is shorted to the emitter by

Rg + 1 Ω. Minimizing Rg and the

lead inductance from the HCPL-

3120 to the IGBT gate and

emitter (possibly by mounting the

HCPL-3120 on a small PC board

directly above the IGBT) can

eliminate the need for negative

IGBT gate drive in many applica-

tions as shown in Figure 25. Care

should be taken with such a PC

board design to avoid routing the

(typical) on resistance in its pull

down circuit. When the HCPL-

3120 is in the low state, the IGBT

HCPL-3120.)

HCPL-3120

+5 V

1

2

3

4

8

V

= 18 V

CC

+ HVDC

270 Ω

0.1 µF

+

–

7

Rg

Q1

3-PHASE

AC

CONTROL

INPUT

6

5

74XXX

OPEN

COLLECTOR

Q2

- HVDC

Figure 25. Recommended LED Drive and Application Circuit.

1-191

Selecting the Gate Resistor

(Rg) to Minimize IGBT

Switching Losses.

Step 1: Calculate Rg Minimum

from the I_OLPeak Specifica-

tion. The IGBT and Rg in Figure

26 can be analyzed as a simple

RC circuit with a voltage supplied

by the HCPL-3120.

The V_OLvalue of 2 V in the pre-

vious equation is a conservative

value of V_OLat the peak current

of 2.5A (see Figure 6). At lower

Rg values the voltage supplied by

the HCPL-3120 is not an ideal

voltage step. This results in lower

peak currents (more margin)

than predicted by this analysis.

When negative gate drive is not

used V_EEin the previous equation

is equal to zero volts.

P_T= P_E+ P_O

•

P_E= I_FV Duty Cycle

F

P_O= P_O(BIAS)+ P_{O (SWITCHING)}

•

= I_CC(V_CC- V_EE)

•

+ E_SW(R_G, Q_G) f

For the circuit in Figure 26 with I_F

(worst case) = 16 mA, Rg = 8 Ω,

Max Duty Cycle = 80%, Qg = 500

nC, f = 20 kHz and T_Amax = 85C:

(V – V_EE- V )

Rg ≥ ––^C–^C–––––––––^O–^L––

I_OLPEAK

•

P_E= 16 mA 1.8 V 0.8 = 23 mW

(V – V_EE- 2 V)

= ––^C–^C––––––––––––

I_OLPEAK

Step 2: Check the HCPL-3120

Power Dissipation and

•

P_O= 4.25 mA 20 V

•

+ 5.2 µJ 20 kHz

= 85 mW + 104 mW

= 189 mW

Increase Rg if Necessary. The

HCPL-3120 total power dissipa-

tion (P_T) is equal to the sum of

the emitter power (P_E) and the

output power (P_O):

(15 V + 5 V - 2 V)

= ––––––––––––––––––

2.5 A

> 178 mW (P_O(MAX)@ 85C

= 250 mW−15C*4.8 mW/C)

= 7.2 Ω 8 Ω

HCPL-3120

+5 V

1

2

3

4

8

V

= 15 V

CC

+ HVDC

270 Ω

0.1 µF

+

–

7

Rg

Q1

= -5 V

3-PHASE

AC

CONTROL

INPUT

6

5

V

EE

–

+

74XXX

OPEN

COLLECTOR

Q2

- HVDC

Figure 26. HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive.

P_OParameter

Description

Supply Current

Positive Supply Voltage

Negative Supply Voltage

P_E

Parameter

Description

LED Current

LED On Voltage

I_CC

V_CC

V_EE

I_F

V_F

Duty Cycle

Maximum LED

Duty Cycle

E_SW(Rg,Qg)

Energy Dissipated in the HCPL-3120 for each

IGBT Switching Cycle (See Figure 27)

f

Switching Frequency

1-192

The value of 4.25 mA for I_CCin

the previous equation was

obtained by derating the I_CCmax

of 5 mA (which occurs at -40°C)

to I_CCmax at 85C (see Figure 7).

shown in Figure 29. The HCPL-

3120 improves CMR performance

by using a detector IC with an

optically transparent Faraday

shield, which diverts the capaci-

tively coupled current away from

the sensitive IC circuitry. How

From the thermal mode in Figure

28 the LED and detector IC

junction temperatures can be

expressed as:

•

T_JE= P (θ_LC||(θ_LD+ θ_DC) + θ_CA)

E

Since P_Ofor this case is greater

than P_O(MAX), Rg must be

increased to reduce the HCPL-

3120 power dissipation.

θ_LC* θ_DC

θ_LC+ θ_DC+ θ_LD

•

+ P_D

(

–––––––––––––––– + θ_CA

)

+ T

^Aever, this shield does not

eliminate the capacitive coupling

between the LED and optocoup-

ler pins 5-8 as shown in

•

θ_LC

θ

T_JD= P_E

(

–––––––––^D–^C––––– + θ_CA

)

θ_LC+ θ_DC+ θ_LD

P_{O(SWITCHING MAX)}

= P_O(MAX)- P_O(BIAS)

= 178 mW - 85 mW

= 93 mW

Figure 30. This capacitive

•

coupling causes perturbations in

the LED current during common

mode transients and becomes the

major source of CMR failures for

a shielded optocoupler. The main

design objective of a high CMR

LED drive circuit becomes

keeping the LED in the proper

state (on or off) during common

mode transients. For example,

the recommended application

circuit (Figure 25), can achieve

15 kV/µs CMR while minimizing

component complexity.

+ P (θ_DC||(θ_LD+ θ_LC) + θ_CA) + T

D

A

Inserting the values for θ_LCand

θ_DCshown in Figure 28 gives:

P_{O(SWITCHINGMAX)}

E_SW(MAX)= –––––––––––––––

f

•

93 mW

T_JE= P (256°C/W + θ_CA)

E

= ––––––– = 4.65 µW

•

+ P (57°C/W + θ_CA) + T_A

D

20 kHz

•

T_JD= P (57°C/W + θ_CA)

E

•

+ P (111°C/W + θ_CA) + T_A

D

For Qg = 500 nC, from Figure

27, a value of E_SW= 4.65 µW

gives a Rg = 10.3 Ω.

For example, given P_E= 45 mW,

P_O= 250 mW, T_A= 70°C and θ_CA

= 83°C/W:

Thermal Model

The steady state thermal model

for the HCPL-3120 is shown in

Figure 28. The thermal resistance

values given in this model can be

used to calculate the tempera-

tures at each node for a given

operating condition. As shown by

the model, all heat generated

flows through θ_CAwhich raises

the case temperature T_C

accordingly. The value of θ_CA

depends on the conditions of the

board design and is, therefore,

determined by the designer. The

value of θ_CA= 83°C/W was

obtained from thermal measure-

ments using a 2.5 x 2.5 inch PC

board, with small traces (no

ground plane), a single HCPL-

3120 soldered into the center of

the board and still air. The

absolute maximum power

dissipation derating specifications

assume a θ_CAvalue of 83°C/W.

•

T_JE= P_E339°C/W + P_D140°C/W + T

A

Techniques to keep the LED in

the proper state are discussed in

the next two sections.

= 45 mW^•339°C/W + 250 mW

^•140°C/W + 70°C = 120°C

•

T_JD= P_E140°C/W + P_D194°C/W + T

A

= 45 mW^•140C/W + 250 mW

^•194°C/W + 70°C = 125°C

14

Qg = 100 nC

12

T_JEand T_JDshould be limited to

125C based on the board layout

and part placement (θ_CA) specific

to the application.

Qg = 500 nC

Qg = 1000 nC

10

V

= 19 V

= -9 V

CC

EE

8

6

4

LED Drive Circuit

Considerations for Ultra

2

0

High CMR Performance.

Without a detector shield, the

dominant cause of optocoupler

CMR failure is capacitive

coupling from the input side of

the optocoupler, through the

package, to the detector IC as

0

10

20

30

40

50

Rg – GATE RESISTANCE – Ω

Figure 27. Energy Dissipated in the

HCPL-3120 for Each IGBT Switching

Cycle.

1-193

θ

= 442 °C/W

LD

T_JE= LED junction temperature

T_JD= detector IC junction temperature

T

JD

JE

T_C= case temperature measured at the center of the package bottom

θ_LC= LED-to-case thermal resistance

θ_LD= LED-to-detector thermal resistance

θ

= 467 °C/W

θ

= 126 °C/W

DC

LC

T

C

θ_DC= detector-to-case thermal resistance

θ

= 83 °C/W*

CA

θ_CA= case-to-ambient thermal resistance

θ_CAwill depend on the board design and the placement of the part.

T

A

Figure 28. Thermal Model.

CMR with the LED On

(CMR_H).

A high CMR LED drive circuit

must keep the LED on during

common mode transients. This is

achieved by overdriving the LED

current beyond the input

threshold so that it is not pulled

below the threshold during a

transient. A minimum LED cur-

rent of 10 mA provides adequate

margin over the maximum I_FLHof

5 mA to achieve 15 kV/µs CMR.

The open collector drive circuit,

shown in Figure 32, cannot keep

the LED off during a +dVcm/dt

transient, since all the current

flowing through C_LEDNmust be

supplied by the LED, and it is not

recommended for applications

requiring ultra high CMR_L

performance. Figure 33 is an

alternative drive circuit which,

like the recommended application

circuit (Figure 25), does achieve

ultra high CMR performance by

shunting the LED in the off state.

coupler output will go into the

low state with a typical delay,

UVLO Turn Off Delay, of 0.6 µs.

When the HCPL-3120 output is in

the low state and the supply

voltage rises above the HCPL-

3120 V_UVLO+threshold (11.0 <

V_UVLO+< 13.5) the optocoupler

output will go into the high state

(assumes LED is “ON”) with a

typical delay, UVLO Turn On

Delay of 0.8 µs.

CMR with the LED Off

(CMR_L).

IPM Dead Time and

Propagation Delay

Specifications.

Under Voltage Lockout

Feature.

The HCPL-3120 contains an

A high CMR LED drive circuit

must keep the LED off (V_F≤

V_F(OFF)) during common mode

transients. For example, during a

-dV_cm/dt transient in Figure 31,

the current flowing through C_LEDP

also flows through the R_SATand

V_SATof the logic gate. As long as

the low state voltage developed

across the logic gate is less than

V_F(OFF), the LED will remain off

and no common mode failure will

occur.

The HCPL-3120 includes a

under voltage lockout (UVLO)

feature that is designed to protect

the IGBT under fault conditions

which cause the HCPL-3120

supply voltage (equivalent to the

fully-charged IGBT gate voltage)

to drop below a level necessary to

keep the IGBT in a low resistance

state. When the HCPL-3120

output is in the high state and the

supply voltage drops below the

HCPL-3120 V_UVLO–threshold

(9.5 < V_UVLO–< 12.0) the opto-

Propagation Delay Difference

(PDD) specification intended to

help designers minimize “dead

time” in their power inverter

designs. Dead time is the time

period during which both the

high and low side power

transistors (Q1 and Q2 in Figure

25) are off. Any overlap in Q1

and Q2 conduction will result in

large currents flowing through

the power devices between the

high and low voltage motor rails.

1-194

C

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

LEDO1

C

LEDP

C

LEDO2

LEDN

SHIELD

Figure 29. Optocoupler Input to Output

Capacitance Model for Unshielded Optocouplers.

Figure 30. Optocoupler Input to Output

Capacitance Model for Shielded Optocouplers.

+5 V

1

2

3

4

8

7

6

5

0.1

µF

+

–

C

I

LEDP

V

= 18 V

CC

+

1

2

3

4

8

7

6

5

LEDP

V

SAT

+5 V

–

C

LEDP

• • •

C

LEDN

Rg

SHIELD

C

I

LEDN

Q1

LEDN

* THE ARROWS INDICATE THE DIRECTION

OF CURRENT FLOW DURING –dV /dt.

SHIELD

CM

+

–

V

CM

Figure 31. Equivalent Circuit for Figure 25 During

Common Mode Transient.

Figure 32. Not Recommended Open

Collector Drive Circuit.

which is specified to be 350 ns

over the operating temperature

range of -40°C to 100°C.

To minimize dead time in a given

design, the turn on of LED2

should be delayed (relative to the

turn off of LED1) so that under

worst-case conditions, transistor

Q1 has just turned off when

transistor Q2 turns on, as shown

in Figure 34. The amount of delay

necessary to achieve this condi-

tions is equal to the maximum

value of the propagation delay

1

2

3

4

8

7

6

5

+5 V

C

LEDP

Delaying the LED signal by the

maximum propagation delay

difference ensures that the

minimum dead time is zero, but it

does not tell a designer what the

maximum dead time will be. The

maximum dead time is equivalent

to the difference between the

LEDN

SHIELD

difference specification, PDD_MAX

,

Figure 33. Recommended LED Drive

Circuit for Ultra-High CMR.

1-195

Note that the propagation delays

used to calculate PDD and dead

time are taken at equal tempera-

tures and test conditions since

the optocouplers under consider-

ation are typically mounted in

close proximity to each other and

are switching identical IGBTs.

maximum and minimum propaga-

tion delay difference specifica-

tions as shown in Figure 35. The

maximum dead time for the

HCPL-3120 is 700 ns (= 350 ns -

(-350 ns)) over an operating

temperature range of -40°C to

100°C.

14

12

I

LED1

V

OUT1

(12.3, 10.8)

Q1 ON

10

8

(10.7, 9.2)

Q1 OFF

Q2 ON

6

Q2 OFF

V

OUT2

4

I

LED2

2

0

t

PHL MAX

(10.7, 0.1)

(12.3, 0.1)

15

t

PLH MIN

0

5

10

20

PDD* MAX = (t - t

)

= t

- t

PHL MAX PLH MIN

PHL PLH MAX

(V

- V

) – SUPPLY VOLTAGE – V

EE

CC

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS

ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Figure 34. Minimum LED Skew for Zero Dead Time.

Figure 36. Under Voltage Lock Out.

I

800

LED1

P

(mW)

(mA)

S

700

600

500

400

300

I

S

V

OUT1

Q1 ON

Q1 OFF

Q2 ON

Q2 OFF

V

OUT2

200

100

0

I

LED2

t

PHL MIN

t

PHL MAX

t

PLH

MIN

0

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

T

S

t

PLH MAX

(t

t

)

PHL- PLH MAX

Figure 37. Thermal Derating Curve,

Dependence of Safety Limiting Value

with Case Temperature per VDE 0884.

PDD* MAX

MAXIMUM DEAD TIME

(DUE TO OPTOCOUPLER)

= (t

- t

) + (t

- t )

PLH MAX PLH MIN

PHL MAX PHL MIN

= (t

- t

) – (t

- t

)

PHL MAX PLH MIN PHL MIN PLH MAX

= PDD* MAX – PDD* MIN

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION

DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Figure 35. Waveforms for Dead Time.

1-196

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