HCPL-3180应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

Agilent HCPL-3180 2 Amp Output

Current, High Speed IGBT/MOSFET Gate

Drive Optocoupler

Data Sheet

Features

• 2 A minimum peak output current

• 250 KHz maximum switching

speed

Description

• High speed response: 200 ns max

This family of devices consists of

a GaAsP LED. The LED is

optically coupled to an

integrated circuit with a power

stage. These optocouplers are

ideally suited for high frequency

driving of power IGBT and

MOSFETs used in Plasma

Display Panels, high

Propagation delay over

temperature range

V_CC

V_O

N/C

1

2

3

4

8

7

6

5

ANODE

• 10 KV/us minimum common mode

rejection (CMR) at V =1500 V

CM

CATHODE

• Under voltage lockout protection

V_O

(UVLO) with hysteresis

V_EE• Wide operating temperature

N/C

°

range: -40 °C to +100 C

• Wide V operating range:

CC

performance DC/DC convertors

and motor control invertor

applications.

Functional Diagram

10 V to 20 V

• 20 ns typ pulse width distortion

• Safety Approvals:

UL approval pending

Ordering Information

Specify part number followed by

option number (if desired):

3750 V

CSA approval

for 1 minute.

RMS

DIN EN 60747-5-2 approval

pending

Example : HCPL-3180-XXX

No option = Standard DIP

package, 50 per tube.

Applications

300 = Gull Wing Surface Mount

Option, 50 per tube.

• Plasma Display Panel (PDP)

• Distributed power architecture

(DPA)

• Switch mode rectifier (SMR)

• High performance DC/DC

convertor

• High performance switch mode

power supply (SMPS)

• High performance uninterruptible

power supply (UPS)

500 = Tape and Reel Packaging

Option.

060 = DIN EN 60747-5-2 Option,

VIORM=630 Vpeak (pending

approval)

• Isolated IGBT/Power MOSFET

gate drive

A 0.1 uF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/

or degradation which may be induced by ESD.

HCPL-3180 Standard DIP Package

HCPL-3180 Gull Wing Surface Mount Option 300

2

Solder Reflow Temperature Profile

300

PREHEATING RATE 3˚C + 1˚C/–0.5˚C/SEC.

REFLOW HEATING RATE 2.5˚C 0.5˚C/SEC.

PEAK

TEMP.

245˚C

PEAK

TEMP.

240˚C

PEAK

TEMP.

230˚C

200

100

2.5˚C 0.5˚C/SEC.

SOLDERING

TIME

30

160˚C

150˚C

140˚C

200˚C

SEC.

30

SEC.

3˚C + 1˚C/–0.5˚C

PREHEATING TIME

150˚C, 90 + 30 SEC.

50 SEC.

TIGHT

TYPICAL

LOOSE

ROOM

TEMPERATURE

0

50

100

150

200

250

TIME (SECONDS)

Regulatory Information

The HCPL-3180 is pending

approval by the following

organizations:

DIN EN 60747-5-2

Pending approval under DIN

EN-60747-5-2 with V

= 630

IORM

V

PEAK

UL

Approval under UL 1577,

component recognition program

up to V = 2500 V Pending

ISO

RMS.

3750 V

RMS.

CSA

Approval under CSA

Component.

3

DIN EN 60747-5-2 Insulation Characteristics (HCPL-3180 Option 060)

Description

Symbol

HCPL-3180

Unit

Installation classification per DIN EN 0110 1997-04

for rated mains voltage 150 Vrms

for rated mains voltage 300 Vrms

for rated mains voltage 600 Vrms

Climatic Classification

I - IV

I - III

I - II

55/100/21

2

Pollution Degree (DIN EN 0110 1997 -04)

Maximum Working Insulation Voltage

V_IORM

V_PR

630

Vpeak

Input to Output Test Voltage, Method b*

1181

VIORM x 1.875=VPR, 100% Production Test withtm=1 sec, Partial discharge < 5 pC

Input to Output Test Voltage, Method a*

VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,Partial discharge < 5 pC

V_PR

945

Vpeak

Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec)

Safety-limiting values - maximum values allowed in the event of a failure.

Case Temperature

V_IOTM

6000

T_S

175

230

600

>10⁹

°C

Input Current**

I_{S, INPUT}

P_{S, OUTPUT}

R_S

mA

mW

W

Output Power**

Insulation Resistance at TS, VIO = 500 V

*

Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (DIN) for a

detailed description of Method A and Method B partial discharge test profiles.

** Refer to the following figure for dependence of P and I on ambient temperature.

S

800

700

600

500

400

300

P

(mW)

S

I

S

(mA)

200

100

0

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – ˚C

T

S

4

Insulation and Safety Related Specifications

Parameter

Symbol HCPL-3180 Units Conditions

Minimum External Air Gap (Clearance)

L(101)

7.1

mm

Measured from input terminals to output terminals, shortest

distance through air.

Minimum External Tracking (Creepage)

L(102)

7.4

Measured from input terminals to output terminals, shortest

distance path along body.

Minimum Internal Plastic Gap

(Internal Clearance)

0.08

Through insulation distance conductor to conductor, usually

the straight line distance thickness between the emitter and

detector.

Tracking Resistance

(Comparative Tracking Index)

CTI

>175

IIIa

V

DIN IEC 112/VDE 0303 Part 1

Isolation Group

Material Group (DIN VDE 0110, 1/89, Table 1)

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Units Note

Storage Temperature

T_S

-55

+125

°C

Junction Temperature

Average Input Current

Tj

-40

+125

25

°C

I_F(AVG)

I_F(TRAN)

V_R

mA

A

1

Peak Transient Input Current (<1s pulse width, 300 pps)

Reverse Input Voltage

1.0

5

V

"High" Peak Output Current

"Low" Peak Output Current

Supply Voltage

I_OH(PEAK)

I_OL(PEAK)

V_CC- V_EE

V_O(PEAK)

P_O

2.5

25

A

2

A

-0.5

0

V

Output Voltage

V_CC

250

295

V

Output Power Dissipation

Total Power Dissipation

mW

3

4

P_T

Lead Solder Temperature

Solder Reflow Temperature Profile

+260 °C for 10 sec., 1.6 mm below seating plane

See Package Outline Drawings section

Recommended Operating Conditions

Parameter

Symbol

Min

Max

Units Note

Power Supply

V_CC- V_EE

10

20

V

Input Current (ON)

Input Voltage (OFF)

Operating Temperature

I_F(ON)

V_F(OFF)

T_A

10

16

mA

V

- 3.0

- 40

0.8

100

°C

5

Electrical Specifications (DC)

Over recommended operating conditions unless otherwise specified.

Parameter

Symbol

Min

0.5

Typ

Max Units Test Conditions Fig Note

High Level Output Current

I_OH

A

V

V_O= (V_CC-4 V)

V_O= (V_CC-10 V)

V_O= (V_EE+2.5 V)

V_O= (V_EE+ 10 V)

I_O= -100 mA

2, 3

17

5

2

5

2

2.0

Low Level Output Current

I_OL

0.5

5, 6

18

2.0

High Level Output Voltage

Low Level Output Voltage

High Level Supply Current

Low Level Supply Current

V_OH

V_OL

I_CCH

I_CCL

V_CC- 4

1, 3 6, 7

19

0.5

6.0

V

I_O= 100 mA

4, 6

20

3.0

mA

Output Open

I_F= 10 to 16 mA

7, 8

Output Open

9,

VI_F= -3.0 to 0.8 V

15,

21

Threshold Input Current Low to High

I_FLH

8.0

1.8

mA

I_O= 0 mA

V_O> 5 V

Threshold Input Voltage High to Low

Input Forward Voltage

V_FHL

0.8

1.2

V

I_F- 10 mA

16

∇

V_F

1.5

-1.6

7.9

7.4

0.5

V

D V_F/ T_A

V_UVLO+

Temperature Coefficient of Forward Voltage

UVLO Threshold

mV/°C

V

V_O> 5 V

I_F= 10 mA

22,

34

V_UVLO-

UVLO Hysteresis

UVLO_HYST

BV_R

V

Input Reverse Breakdown Voltage

Input Capacitance

5

V

I_R= 10 uA

C_IN

60

pF

f = 1 MHz,

V_F= 0 V

6

Switching Specifications (AC)

Over recommended operating conditions unless otherwise specified.

Parameter

Symbol

Min

Typ

Max Units Test Conditions Fig Note

Propagation Delay Time to High Output Level

t_PLH

50

150

200

ns

I_F= 10 mA

R_g= 10 W

f = 250 kHz

Duty Cycle = 50%

C_g= 10 nF

10,

11,

12,

13,

14,

23

16

Propagation Delay Time to Low Output Level

Pulse Width Distortion

t_PHL

50

150

20

200

ns

PWD

PDD

65

90

ns

12

17

Propagation Delay Difference Between Any Two

Parts

-90

ms

35,

36

(t_PHL- t_PLH

)

Rise Time

t_r

25

ns

C_L= 1 nF

23

R_g= 0 W

Fall Time

t_f

25

ns

UVLO Turn On Delay

UVLO Turn Off Delay

t_{UVLO ON}

t_{UVLO OFF}

|CM_H|

2.0

0.3

us

22

24

us

Output High Level Common Mode Transient

Immunity

10

kV/µs

T_A= +25 °C

I_f= 10 to 16 mA

V_CM= 1.5 kV

V_CC= 20 V

13, 14

13, 15

Output Low Level Common Mode Transient

Immunity

|CM_L|

kV/µs

T_A= +25 °C

V_f= 0 V

V_CM= 1.5 kV

V_CC= 20 V

V_CM= 1.5 kV

Package Characteristics

Parameter

Symbol

Min

Typ

Max Units Test Conditions Fig Note

Input-Output Momentary Withstand Voltage

V_ISO

2500

V_rms

T_A= +25 °C,

RH < 50%

8, 9

W

Input-Output Resistance

Input-Output Capacitance

R_I-O

C_I-O

1011

1

V_I-O= 500 V

9

pF

Freq = 1 MHz

Notes:

1. Derate linearly above +70 °C free air temperature at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 us, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I peak

O

minimum = 2.0 A. See Application section for additional details on limiting I peak.

OL

3. Derate linearly above +70 °C, free air temperature at the rate of 4.8 mW/°C.

4. Derate linearly above +70 °C, free air temperature at the rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed +125 °C.

5. Maximum pulse width = 50 us, maximum duty cycle = 0.5%.

6. In this test, V is measured with a dc load current. When driving capacitive load V will approach V as I approaches zero amps.

OH

CC

OH

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 3000 V for 1 second (leakage detection

rms

current limit I < 5 uA).

I-O

9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.

10. t

propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the V signal. t

O PLH

PHL

propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the V signal

O

11. t is equal to the magnitude of the worst case difference in t

and/or t

that will be seen between units at any given temperature within the

PLH

PSK

PHL

recommended operating conditions

12. PWD is defined as |t

- t

| for any given device.

PHL PLH

13. Pin 1 and 4 need to be connected to LED common.

7

14. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse V to assure that the output will

CM

remain in the high state (i.e. V > 10.0 V).

O

15. Common mode transient immunity in a low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the output will

CM

remain in a low state (i.e. V < 1.0 V).

O

16. t

propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the V signal. t

O PLH

PHL

propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the V signal

O

17. The difference between t

and t

between any two HCPL-3180 parts under same test conditions.

PLH

PHL

0

-1

-2

-3

-4

I_F=10 to 16mA

_OUT=-100mA

100 C

-0.5

-1

I

-40 C

25 C

V_CC=10 to 20V

V

_EE

=0V

-1.5

-2

-2.5

-3

I_F=10mA to 16mA

-5

-6

V_CC=10 to 20 V

V_EE=0V

-40

-20

0

20

40

60

80

100

0

1

2

3

4

T_A

I_OH- OUTPUT HIGH CURRENT - A

Figure 1. V Vs Temperature

OH

Figure 3. V Vs I

OH

2.5

2

0.3

V_F(OFF)= -3.0 TO 0.8V

I_OUT= 100mA

V_CC= 10 to 20V

V_EE= 0

0.25

0.2

1.5

1

0.15

0.1

I_F= 10 to16mA

V_OUT=(V_CC-4)

V_CC=10 to 20V

0.5

0

V_EE=0V

60

0.05

0

-40

10

T_A

-40

-20

0

20

40

60

80

100

T_A- TEMPERATURE - °C

Figure 2. I Vs Temperature

OH

Figure 4. V Vs Temperature

OL

8

3.5

3.3

3.1

2.9

2.7

2.5

3

2.5

2

V_F(OFF) = -3.0 TO 0.8V

ICCL

ICCH

V_OUT= 2.5V

V_CC= 10 to 20V

V_EE= 0

1.5

1

I_F=10mA for I_CC

H

I_F=0mA for I_CC

T_A=25°C

L

0.5

0

V_EE=0V

10

12

14

16

18

20

-40

-20

0

20

40

60

80

100

V

_CC- SUPPLY VOLTAGE - V

T_A

Figure 8. I Vs V

Figure 5. I Vs Temperature

CC

OL

4

5

V_F(OFF)= -3 to0.8V

V_CC=10 to 20 V

V_CC= 10 to20V

V_EE= 0V

Output= Open

3

4

3

2

1

0

V_EE=0V

2

1

0

25 C

0 C

100 C

-40

-20

0

20

40

60

80

100

0

0.5

1

1.5

2

2.5

T_A- TEMPERATURE - °C

I_OL- OUTPUT LOW CURRENT - A

Figure 9. IFLH Vs Temperature

Figure 6. V Vs I

OL

250

4

3.5

3

I_F=10mA

T_A=25°C

200

Rg=10ohm

Cg=10nF

Duty Cycle=50%

f=250KHZ

2.5

2

150

1.5

V_CC=20V

V_EE=0V

100

50

1

0.5

0

ICCH

TPLH

TPHL

I_F=10mA for I_CC

I_F=0mA for I_CC

H

ICCL

L

10

15

20

25

-40

-20

0

20

40

60

80

100

V_CC- SUPPLY VOLTAGE -V

T_A- TEMPERATURE - oC

Figure 10. Propagation Delay Vs V

Figure 7. I Vs Temperature

CC

9

250

200

150

100

50

250

200

150

100

50

V_CC=20V, V_EE=0V

Rg=10 ohm,

Cg=10nF

Duty Cycle = 50%

f=250KHz

I_F=10mA

T_A=25°C

Rg=10ohm

Duty Cycle=50%

f=250KHZ

T_A=25°C

TPLH

TPHL

Tplh

Tphl

6

8

10

12

14

16

5

10

15

20

25

I_F- FORWARD LED CURRENT - mA

Cg - LOAD CAPACITANCE - nF

Figure 11. Propagation Delay Vs IF

Figure 14. Propagation Delay Vs Cg

250

20

15

10

5

I_F=10mA

V_CC=20V, V_EE=0V

200 Rg=10 ohm, Cg=10nF

Duty Cycle = 50%

f=250KHz

150

100

50

TPHL

TPLH

0

1

2

3

4

5

-40

-20

0

20

40

60

80

100

I_F- FORWARD LED CURRENT - mA

T_A- TEMPERATURE - °C

Figure 12. Propagation Delay Vs Temperature

Figure 15. Transfer Characteristics

1000

100

250

T

= 25˚C

A

I_F=10mA

T_A=25°C

Cg=10nF

200

I

F

Duty Cycle=50%

f=250KHZ

+

10

1.0

0.1

V

F

–

150

100

50

TPLH

TPHL

0.01

10

20

30

40

50

0.001

1.10

1.20

1.30

1.40

1.50

1.60

Rg - SERIES LOAD RESISTANCE - ohm

V

– FORWARD VOLTAGE – VOLTS

F

Figure 13. Propagation Delay Vs Rg

Figure 16. Input Current Vs Forward Voltage

10

1

2

3

4

8

7

4V/10V

V_CC=10 to 20V

+

-

+

-

I_F=10mA to

16mA

0,1 µF

6

IoH

5

Shield

Figure 17. IOH Test Circuit

1

8

V_CC=10 to 20V

+

-

2

3

7

0,1 µF

6

IoL

+

-

2.5V/10V

4

5

Shield

Figure 18. IOL Test Circuit

1

2

3

4

8

7

V_CC=10 to 20V

+

-

I_F=10mA to

16mA

0,1 µF

6

V_OH

100mA

5

Shield

Figure 19. VOH Test Circuit

11

1

2

3

4

8

7

+

-

100mA

0,1 µF

6

VOL

5

Shield

Figure 20. VOL Test Circuit

1

2

3

4

8

7

V_CC=10 to 20V

+

-

0,1 µF

IF

V_O> 5V

6

5

Shield

Figure 21. IFLH Test Circuit

1

8

7

V_CC

+

-

2

3

4

+-

0,1 µF

I_F=10mA

V_O> 5V

6

5

Shield

Figure 22. UVLO Test Circuit

12

If= 10 to 16mA

1

2

3

4

8

7

Vcc=+20V

500 Ω

If

+

-

+

Tf

Tr

-

250KHz

50% Duty

Cycle

0,1 µF

6

90%

50%

10%

10Ω

10nF

Vout

5

GND

Shield

Tplh

Tphl

Figure 23. TPLH, TPHL, Tr and Tf Test Circuit and Waveform

IF

VCM

1

8

7

dv/dt= Vcm/dt

Vcc =+20V

0V

+

-

5V

+

dt

-

2

3

4

0,1

µF

VO

VOH

6

5

Switching at A

IF=10mA

VO

Shield

VOL

Switching at B

IF=0mA

+

-

Vcm =1500V

Figure 24. CMR Test Circuit and Waveform

13

Applications Information Eliminating

Negative IGBT Gate Drive

case) = 16 mA, R ~ 10 W, Max

Selecting the Gate Resistor (R ) for

HCPL-3180

g

Duty Cycle = 80%, Q = 100 nC, f

g

To keep the IGBT firmly off, the

HCPL-3180 has a very low

= 200 kHz and T

= +75 °C:

Step 1: Calculate R minimum

g

AMAX

from the I peak specification.

OL

maximum V specification of

0.4 V. The HCPL-3180 realizes

The IGBT and R in Figure 25

OL

g

P_E=16mA •1.8V • 0.8 = 23mW

P_O= 4.5mA • 20V + 0.85µJ •

200kHz

can be analyzed as a simple RC

circuit with a voltage supplied

by the HCPL-3180.

the very low V by using a

OL

DMOS transistor with 1 W

P

@









O

(

MAX

)

(typical) on resistance in its pull

down circuit. When the HCPL-

3180 is in the low state, the

IGBT gate is shorted to the

emitter by Rg + 1 W. Minimizing

Rg and the lead inductance from

the HCPL-3180 to the IGBT gate

and emitter (possibly by

75°C





= 260mW ≥ 226mW = 250mW

V_CC− V_OL

R_g≥



− (5°C *









I_OLPEAK

4.8mW /°C)

20 − 3

=

2

= 8.5Ω

The value of 4.5 mA for I in

CC

the previous equation was

obtained by derating the I max

The V value of 3 V in the

CC

OL

mounting HCPL-3180 on a small

PC board directly above the

IGBT) can eliminate the need for

negative IGBT gate drive in

many applications as shown in

Figure 25. Care should be taken

with such a PC board design to

avoid routing the IGBT collector

or emitter traces close to the

HCPL-3180 input as this can

result in unwanted coupling of

transient signals into the input

of HCPL-3180 and degrade

performance.

of 6 mA to I max at +75 °C.

previous equation is the V at

the peak current of 2 A. (See

Figure 6).

CC

OL

Since P for this case is greater

O

than the P

, Rg must be

O(max)

increased to reduce the HCPL-

3180 power dissipation.

Step 2: Check the HCPL-3180

power dissipation and increase

R if necessary. The HCPL-3180

g

P_o(SwitchingMAx)

= P₀(Max) − P_O(Bias)

= 226mW − 90mW

=136mW

total power dissipation (P ) is

T

equal to the sum of the emitter

power (P ) and the output

E

power (P ).

O

E_SW(Max)

= P_{O(Sitching Max)}/ f

=136mW /200KHz

= 0.68µW

P_T= P_E+ P_O

P_E= I_F• V_F• DutyCycle

P_O= P_O(BIAS)+ P_O(SWITCHING)

(If the IGBT drain must be

routed near the HCPL-3180

input, then the LED should be

reverse biased when in the off

state, to prevent the transient

signals coupled from the IGBT

drain from turning on the HCPL-

3180)

= I_CC• V_CC+ E_SW

I_CC

(

R_g;Q_g

)

• f

=

(

)

• V_CC+ E_SW

(R_g;Q_g

)

• f

For Qg = 100 nC a Value of Esw =

0.68 UW gives a Rg = 15 ohm

For the circuit in Figure 25 with

the circuit in with I (worst

F

+HVDC

+5 V

1

8

V_CC=+15V

270 Ω

+

-

GND

2

7

Rg

0,1 µF

3

6

74XXX

Open

Collector

5

4

Shield

GND

- HVDC

Figure 25. Recommended LED Drive and Application Circuit for HCPL-3180

14

2

1.8

1.6

1.4

1.2

1

θ

= 442 ˚C/W

LD

Qg = 100nC

T

JD

JE

θ

= 467 ˚C/W

θ

= 126 ˚C/W

DC

LC

T

C

θ

= 83 ˚C/W*

CA

0.8

0.6

0.4

0.2

0

T

A

Figure 28. Thermal Model

0

10

20

30

40

50

Rg(ohm)

Figure 27. Energy Dissipated in the HCPL-3180 for each IGBT

Thermal Model

(Discussion applies to HCPL-3180)

The steady state thermal model for the HCPL-3180 is shown in Figure 28. The thermal resistance values

given in this model can be used to calculate the temperatures at each node for a given operating

condition. As shown by the model, all heat generated flows through Q which raises the case

CA

temperature T accordingly. The value of Q depends on the conditions of the board design and is,

C

CA

therefore, determined by the designer. The value of Q = +83 °C/W was obtained from thermal

CA

measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL- 3180

soldered into the center of the board and still air. The absolute maximum power dissipation derating

specifications assume a Q value of +83 °C/W From the thermal mode in Figure 28 the LED and

CA

detector IC junction temperatures can be expressed as:

θ_LC*θ_DC

θ_LC+θ_DC+θ_LD

T_JE= P_E*(θ_LC//(θ_LD+θ_DC) +θ_CA+ P_D*(

+θ_CA) +T_A

θ

_LC*θ_DC

T_JD= P_E*(

+θ_CA) + P_D*(θ_DC//(θ_LD+θ_LC) +θ_CA) +T_A

θ_LC+θ_DC+θ_LD

Inserting the values for Q and Q shown in Figure 28 gives:

LC

DC

T

= PE·(+256 °C/W + Q )+ PD·(+57 °C/W + Q ) + T

CA CA A

JE

JD

= PE·(+57 °C/W + Q )+ PD·(+111 °C/W + Q ) + T

CA

A

For example, given P = 45 mW,

E

P = 250 mW, T = +70 °C and QCA= +83 °C/W:

O

A

T

= PE·(+339 °C/W + PD·(+140 °C/W +T

JE

A

= 45 mW·+339 °C/W + 250 mW·+140 °C/W + +70 °C

= +120 °C

T

= PE·(+140 °C/W + PD·+194 °C/W +T

JD

A

= 45 mW·+140 °C/W + 250 mW·+194 °C/W + +70 °C

= +125 °C

T

and T should be limited to +125 °C based on the board layout and part placement (QCA) specific

JD

JE

to the application.

TJE = LED junction temperature

TJD = detector IC junction temperature

TC = case temperature measured at the center of the package bottom

Q

= LED-to-case thermal resistance

= LED-to-detector thermal resistance

= detector-to-case thermal resistance

= case-to-ambient thermal resistance

LC

LD

DC

CA

*Q will depend on the board design and the placement of the part.

CA

15

LED Drive Circuit Considerations for

Ultra High CMR Performance

Without a detector shield, the

dominant cause of optocoupler

CMR failure is capacitive

coupling from the input side of

the optocoupler, through the

package, to the detector IC as

shown in Figure 29. The HCPL-

3180 improves CMR

performance by using a detector

IC with an optically transparent

Faraday shield, which diverts

the capacitively coupled current

away from the sensitive IC

Figure 29. Optocoupler Input to Output

Capacitance Model for Unshielded

Optocouplers.

Figure 30. Optocoupler Input to Output

Capacitance Model for Shielded

Optocouplers.

circuitry. However, this shield

does not eliminate the capacitive

coupling between the LED and

optocoupler pins 5-8 as shown

in Figure 30. This capacitive

coupling causes perturbations in

the LED current during common

mode transients and becomes

the major source of CMR failures

for a shielded optocoupler. The

main design objective of a high

CMR LED drive circuit becomes

keeping the LED in the proper

state (on or off ) during common

mode transients. For example,

the recommended application

circuit (Figure 25), can achieve

10 kV/us CMR while minimizing

component complexity.

Vcc= 20V

Figure 31. Equivalent Circuit for Figure 25

During Common Mode Transient.

Techniques to keep the LED in

the proper state are discussed in

the next two sections.

Figure 32. Not Recommended Open Collector

Drive Circuit.

Figure 33. Recommended LED Drive Circuit for

Ultra-High CMR

16

CMR with the LED On (CMR )

in the high state and the supply

voltage drops below the HCPL-

IPM Dead Time and Propagation

Delay Specifications

H

A high CMR LED drive circuit

must keep the LED on during

common mode transients. This

is achieved by over-driving the

LED current beyond the input

threshold so that it is not pulled

below the threshold during a

transient. A minimum LED

current of 10 mA provides

3180 U

threshold (typ 7.5 V)

The HCPL-3180 includes a

Propagation Delay Difference

(PDD) specification intended to

help designers minimize “dead

time” in their power invertor

designs. Dead time is the time

during which the high and low

side power transistors are off.

Any overlap in Q1 and Q2

conduction will result in large

currents flowing through the

power devices from the high

voltage to the low-voltage motor

rails.

VLO-

the optocoupler output will go

into the low state. When the

HCPL-3180 output is in the low

state and the supply voltage

rises above the HCPL-3180

V

threshold (typ 8.5 V) the

UVLO+

optocoupler output will go into

the high state (assume LED is

“ON”).

adequate margin over the

maximum I

of 8 mA to

FLH

achieve 10 kV/us CMR.

CMR with the LED Off (CMR )

L

A high CMR LED drive circuit

must keep the LED off (V ≤

F

V ) during common mode

F(OFF)

transients. For example, during

20

18

16

14

12

10

8

a -dV /dt transient in Figure

31, the current flowing through

CM

C

R

also flows through the

LEDP

and V

of the logic gate.

SAT

As long as the low state voltage

developed across the logic gate

is less than V

the LED will

F(OFF)

remain off and no common

mode failure will occur.

6

4

The open collector drive circuit,

shown in Figure 32, cannot keep

2

0

the LED off during a +dV /dt

CM

0

5

10

15

20

transient, since all the current

(V_CC-V_EE) - SUPPLY VOLTAGE - V

flowing through C

must be

LEDN

supplied by the LED, and it is

not recommended for

Figure 34. Under Voltage Lock Out

applications requiring ultra high

CMR performance. Figure 33 is

L

an alternative drive circuit,

which like the recommended

application circuit (Figure 25),

does achieve ultra high CMR

performance by shunting the

LED in the off state.

Under Voltage Lockout Feature

The HCPL-3180 contains an

under voltage lockout (UVLO)

feature that is designed to

protect the IGBT under fault

conditions which cause the

HCPL-3180 supply voltage

(equivalent to the fully charged

IGBT gate voltage) to drop below

a level necessary to keep the

IGBT in a low resistance state.

When the HCPL-3180 output is

Figure 35. Minimum LED Skew for Zero Dead

Time

17

To minimize dead time in a

given design, the turn on of

LED2 should be delayed

(relative to the turn off of LED1)

so that under worst-case

conditions, transistor Q1 has

just turned off when transistor

Q2 turns on, as shown in Figure

35. The amount of delay

necessary to achieve this

condition is equal to the

maximum value of the

propagation delay difference

specification, PDD

, which is

MAX

specified to be 90 ns over the

operating temperature range of

-40 °C to +100 °C.

Delaying the LED signal by the

maximum propagation delay

difference ensures that the

minimum dead time is zero, but

it does not tell a designer what

the maximum dead time will be.

The maximum dead time is

equivalent to the difference

between the maximum and

minimum propagation delay

difference specification as

shown in Figure 36. The

Figure 36. Waveforms for Dead Time

maximum dead time for the

HCPL-3180 is 180 ns (= 90 ns-(-

90 ns)) over the operating

temperature range of –40 °C to

+100 °C.

Note that the propagation delays

used to calculate PDD and dead

time are taken at equal

temperatures and test

conditions since the

optocouplers under

consideration are typically

mounted in close proximity to

each other and are switching

identical IGBTs.

18

www.agilent.com/

semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(916)788-6763

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (+65) 6756 2394

India, Australia, New Zealand: (+65) 6755 1939

Japan: (+81 3) 3335-8152(Domestic/International), or

0120-61-1280(DomesticOnly)

Korea: (+65) 6755 1989

Singapore, Malaysia, Vietnam, Thailand, Philippines,

Indonesia: (+65) 6755 2044

Taiwan: (+65) 6755 1843

Data subject to change.

August 11, 2003

5988-9921EN

电子百科

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