HCPL-4661应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

H

High CMR, High Speed TTL

Compatible Optocouplers

6N137

HCNW137

HCNW2601

HCNW2611

HCPL-0600

HCPL-0601

HCPL-0611

HCPL-0630

HCPL-0631

HCPL-0661

HCPL-2601

HCPL-2611

HCPL-2630

HCPL-2631

HCPL-4661

Technical Data

Features

Applications

• Isolated Line Receiver

• Computer-Peripheral

Interfaces

• Microprocessor System

Interfaces

• Digital Isolation for A/D,

D/A Conversion

• Switching Power Supply

• Instrument Input/Output

Isolation

• Ground Loop Elimination

• Power Transistor Isolation

in Motor Drives

• Isolation of High Speed

Logic Systems

• 5 kV/µs Minimum Common

Mode Rejection (CMR) at

V_CM= 50 V for HCPL-X601/

X631, HCNW2601 and

10 kV/µs Minimum CMR at

V_CM= 1000 V for HCPL-

X611/X661, HCNW2611

• High Speed: 10 MBd Typical

• LSTTL/TTL Compatible

• Low Input Current

Capability: 5 mA

• Guaranteed ac and dc

Performance over Temper-

ature: -40°C to +85°C

• Available in 8-Pin DIP,

SOIC-8, Widebody Packages

Description

The 6N137, HCPL-26XX/06XX/

4661, HCNW137/26X1 are

optically coupled gates that

combine a GaAsP light emitting

diode and an integrated high gain

photo detector. An enable input

allows the detector to be strobed.

The output of the detector IC is

• Pulse Transformer

Replacement

• Strobable Output (Single

Channel Products Only)

• Safety Approval

Functional Diagram

6N137, HCPL-2601/2611

HCPL-0600/0601/0611

HCNW137/2601/2611

HCPL-2630/2631/4661

HCPL-0630/0631/0661

UL Recognized - 2500 V rms

for 1 minute and 5000 V rms*

for 1 minute per UL1577

CSA Approved

1

2

V

ANODE

CATHODE

ANODE

1

2

V

8

7

8

7

NC

CC

O1

O2

1

ANODE

E

VDE 0884 Approved with

V

CATHODE

NC

3

4

6

5

3

4

6

5

O

2

V_IORM= 630 V peak for

GND

HCPL-2611 Option 060 and

_IORM= 1414 V peak for

SHIELD

V

HCNW137/26X1

BSI Certified

TRUTH TABLE

(POSITIVE LOGIC)

TRUTH TABLE

(POSITIVE LOGIC)

(HCNW137/26X1 Only)

LED ENABLE OUTPUT

LED OUTPUT

ON

OFF

ON

OFF

ON

OFF

H

L

NC

L

H

L

ON

L

• MIL-STD-1772 Version

Available (HCPL-56XX/

66XX)

OFF

H

*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this

component to prevent damage and/or degradation which may be induced by ESD.

1-146

5965-3594E

an open collector Schottky-

clamped transistor. The internal

shield provides a guaranteed

common mode transient

immunity specification of 5,000

V/µs for the HCPL-X601/X631

and HCNW2601, and 10,000 V/µs

for the HCPL-X611/X661 and

HCNW2611.

This unique design provides

maximum ac and dc circuit

isolation while achieving TTL

compatibility. The optocoupler ac

and dc operational parameters

are guaranteed from -40°C to

+85°C allowing troublefree

system performance.

The 6N137, HCPL-26XX, HCPL-

06XX, HCPL-4661, HCNW137,

and HCNW26X1 are suitable for

high speed logic interfacing,

input/output buffering, as line

receivers in environments that

conventional line receivers

cannot tolerate and are recom-

mended for use in extremely high

ground or induced noise

environments.

Selection Guide

Widebody

Minimum CMR

Input

8-Pin DIP (300 Mil)

Small-Outline SO-8

(400 Mil)

Hermetic

Single

On-

Single

Channel

Package

Dual

Channel

Package

Single

Channel

Package

Dual

Channel

Package

Single

Channel

Package

and Dual

Channel

Packages

dV/dt

V

CM

Current Output

(mA)

(V/µs)

(V)

Enable

YES

NO

NA

5

6N137

HCPL-0600

HCPL-0601

HCPL-0611

HCNW137

HCNW2601

HCNW2611

HCPL-2630

HCPL-2631

HCPL-4661

HCPL-0630

HCPL-0631

HCPL-0661

5,000

50

YES

NO

HCPL-2601

HCPL-2611

10,000 1,000

YES

NO

[1]

1,000

3, 500

1,000

50

300

50

YES

NO

HCPL-2602

HCPL-2612

HCPL-261A

[1]

3

HCPL-061A

[1]

HCPL-263A

HCPL-063A

[2]

[1]

1,000

50

YES

HCPL-261N

HCPL-061N

[1]

NO

[3]

HCPL-263N

HCPL-063N

[1]

1,000

12.5

HCPL-193X

HCPL-56XX

HCPL-66XX

[1]

Notes:

1. Technical data are on separate HP publications.

2. 15 kV/µs with V_CM= 1 kV can be achieved using HP application circuit.

3. Enable is available for single channel products only, except for HCPL-193X devices.

1-147

Ordering Information

Specify Part Number followed by Option Number (if desired).

Example:

HCPL-2611#XXX

020 = 5000 V rms/1 minute UL Rating Option*

060 = VDE 0884 V_IORM= 630 Vpeak Option**

300 = Gull Wing Surface Mount Option†

500 = Tape and Reel Packaging Option

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor for

information.

*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only.

**For HCPL-2611 only. Combination of Option 020 and Option 060 is not available.

†Gull wing surface mount option applies to through hole parts only.

Schematic

HCPL-2630/2631/4661

HCPL-0630/0631/0661

6N137, HCPL-2601/2611

I

CC

I

HCPL-0600/0601/0611

HCNW137, HCNW2601/2611

V

CC

O1

8

7

I

F

1

+

I

F1

CC

V

O1

CC

O

8

6

2+

I

O

V

F1

–

2

V

F

SHIELD

–

3

GND

3

–

I

F2

5

SHIELD

I

O2

V

E

7

E

O2

6

5

V

F2

USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED

BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).

+

4

GND

SHIELD

1-148

Package Outline Drawings

8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)

7.62 ± 0.25

(0.300 ± 0.010)

9.65 ± 0.25

(0.380 ± 0.010)

8

1

7

6

5

6.35 ± 0.25

(0.250 ± 0.010)

TYPE NUMBER

OPTION CODE*

DATE CODE

HP XXXXZ

YYWW

U R

4

UL

2

3

RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076

- 0.051

0.254

5° TYP.

+ 0.003)

- 0.002)

(0.010

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

1.080 ± 0.320

0.65 (0.025) MAX.

(0.043 ± 0.013)

*MARKING CODE LETTER FOR OPTION NUMBERS

"L" = OPTION 020

"V" = OPTION 060

2.54 ± 0.25

(0.100 ± 0.010)

OPTION NUMBERS 300 AND 500 NOT MARKED.

**JEDEC Registered Data (for 6N137 only).

8-pin DIP Package with Gull Wing Surface Mount Option 300

(6N137, HCPL-2601/11/30/31, HCPL-4661)

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25

(0.380 ± 0.010)

1.016 (0.040)

1.194 (0.047)

6

5

8

1

7

4.826

(0.190)

TYP.

6.350 ± 0.25

(0.250 ± 0.010)

9.398 (0.370)

9.906 (0.390)

2

3

4

0.381 (0.015)

0.635 (0.025)

1.194 (0.047)

1.778 (0.070)

9.65 ± 0.25

(0.380 ± 0.010)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

7.62 ± 0.25

(0.300 ± 0.010)

+ 0.076

- 0.051

0.254

4.19

+ 0.003)

- 0.002)

MAX.

(0.165)

(0.010

1.080 ± 0.320

(0.043 ± 0.013)

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

0.635 ± 0.130

(0.025 ± 0.005)

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

1-149

Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)

8

7

6

5

5.842 ± 0.203

(0.236 ± 0.008)

XXX

3.937 ± 0.127

(0.155 ± 0.005)

YWW

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

1

2

3

4

0.381 ± 0.076

(0.016 ± 0.003)

1.270

(0.050)

BSG

0.432

(0.017)

7°

5.080 ± 0.127

(0.200 ± 0.005)

45° X

3.175 ± 0.127

(0.125 ± 0.005)

0.228 ± 0.025

(0.009 ± 0.001)

1.524

(0.060)

0.152 ± 0.051

(0.006 ± 0.002)

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.305

(0.012)

MIN.

8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)

11.00

(0.433)

11.15 ± 0.15

(0.442 ± 0.006)

MAX.

9.00 ± 0.15

(0.354 ± 0.006)

7

6

5

8

TYPE NUMBER

DATE CODE

HP

HCNWXXXX

YYWW

1

3

2

4

10.16 (0.400)

TYP.

1.55

(0.061)

MAX.

7° TYP.

+ 0.076

- 0.0051

0.254

+ 0.003)

- 0.002)

(0.010

5.10

(0.201)

MAX.

3.10 (0.122)

3.90 (0.154)

0.51 (0.021) MIN.

2.54 (0.100)

TYP.

1.78 ± 0.15

(0.070 ± 0.006)

0.40 (0.016)

0.56 (0.022)

DIMENSIONS IN MILLIMETERS (INCHES).

1-150

8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300

(HCNW137, HCNW2601/11)

11.15 ± 0.15

(0.442 ± 0.006)

PAD LOCATION (FOR REFERENCE ONLY)

7

6

5

8

6.15

TYP.

(0.242)

9.00 ± 0.15

(0.354 ± 0.006)

12.30 ± 0.30

(0.484 ± 0.012)

1

3

2

4

0.9

(0.035)

1.3

(0.051)

12.30 ± 0.30

(0.484 ± 0.012)

1.55

(0.061)

MAX.

11.00

MAX.

(0.433)

4.00

MAX.

(0.158)

1.78 ± 0.15

(0.070 ± 0.006)

1.00 ± 0.15

(0.039 ± 0.006)

0.75 ± 0.25

(0.030 ± 0.010)

+ 0.076

- 0.0051

2.54

(0.100)

BSC

0.254

+ 0.003)

- 0.002)

(0.010

DIMENSIONS IN MILLIMETERS (INCHES).

7° NOM.

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

Solder Reflow Temperature Profile (HCPL-06XX and

Gull Wing Surface Mount Option 300 Parts)

260

240

∆T = 145°C, 1°C/SEC

220

∆T = 115°C, 0.3°C/SEC

200

180

160

140

120

100

80

∆T = 100°C, 1.5°C/SEC

60

40

20

0

1

2

3

4

5

6

7

8

9

10

11

12

TIME – MINUTES

Note: Use of nonchlorine activated fluxes is highly recommended.

1-151

Regulatory Information

BSI

CSA

The 6N137, HCPL-26XX/06XX/

46XX, and HCNW137/26XX have

been approved by the following

organizations:

Certification according to

BS415:1994

(BS EN60065:1994),

BS7002:1992

Approved under CSA Component

Acceptance Notice #5, File CA

88324.

(BS EN60950:1992) and

EN41003:1993 for Class II

applications. (HCNW137/26X1

only)

VDE

UL

Approved according to VDE

0884/06.92. (HCPL-2611 Option

060 and HCNW137/26X1 only)

Recognized under UL 1577,

Component Recognition

Program, File E55361.

Insulation and Safety Related Specifications

8-pin DIP

Widebody

(300 Mil) SO-8 (400 Mil)

Parameter

Symbol

Value

Units

Conditions

Minimum External

Air Gap (External

Clearance)

L(101)

7.1

4.9

9.6

mm

Measured from input terminals

to output terminals, shortest

distance through air.

Minimum External

Tracking (External

Creepage)

Minimum Internal

Plastic Gap

L(102)

7.4

4.8

10.0

1.0

mm

Measured from input terminals

to output terminals, shortest

distance path along body.

Through insulation distance,

conductor to conductor, usually

the direct distance between the

photoemitter and photodetector

inside the optocoupler cavity.

0.08

(Internal Clearance)

Minimum Internal

Tracking (Internal

Creepage)

Tracking Resistance

(Comparative

Tracking Index)

Isolation Group

NA

200

IIIa

NA

200

IIIa

4.0

200

IIIa

mm

Measured from input terminals

to output terminals, along

internal cavity.

CTI

Volts DIN IEC 112/VDE 0303 Part 1

Material Group

(DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

1-152

VDE 0884 Insulation Related Characteristics

(HCPL-2611 Option 060 Only)

Description

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 V rms

Symbol Characteristic Units

I-IV

I-III

for rated mains voltage ≤ 450 V rms

Climatic Classification

55/85/21

2

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

V

630

V_peak

IORM

V

_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

V_PR

1181

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V_IORMx 1.5 = V_PR, Type and sample test,

945

V_peak

t_m= 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*

(Transient Overvoltage, t_ini= 10 sec)

V

6000

V_peak

IOTM

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Figure 16, Thermal Derating curve.)

Case Temperature

Input Current

Output Power

T_S

I_S,INPUT

P_S,OUTPUT

R_S

175

230

600

≥ 10⁹

°C

mA

mW

Ω

Insulation Resistance at T_S, V = 500 V

IO

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in

application.

VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only)

Description

Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 600 V rms

for rated mains voltage ≤ 1000 V rms

I-IV

I-III

Climatic Classification (DIN IEC 68 part 1)

55/100/21

2

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

V

1414

V_peak

IORM

V

_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

V_PR

2651

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V_IORMx 1.5 = V_PR, Type and sample test,

2121

8000

V_peak

t_m= 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*

(Transient Overvoltage, t_ini= 10 sec)

Safety Limiting Values

V

V_peak

IOTM

(Maximum values allowed in the event of a failure,

also see Figure 16, Thermal Derating curve.)

Case Temperature

Input Current

Output Power

T_S

I_S,INPUT

P_S,OUTPUT

R_S

150

400

700

≥ 10⁹

°C

mA

mW

Ω

Insulation Resistance at T_S, V = 500 V

IO

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in

application.

1-153

Absolute Maximum Ratings* (No Derating Required up to 85°C)

Parameter

Storage Temperature

Operating Temperature†

Average Forward Input Current

Symbol

Package**

Min.

-55

-40

Max.

125

85

Units

°C

Note

T

S

T

A

I

Single 8-Pin DIP

Single SO-8

Widebody

20

mA

2

F

Dual 8-Pin DIP

Dual SO-8

8-Pin DIP, SO-8

Widebody

15

1, 3

1

Reverse Input Voltage

V

R

5

3

V

Input Power Dissipation

Supply Voltage

P

V

CC

Widebody

40

7

mW

V

I

(1 Minute Maximum)

Enable Input Voltage (Not to

V

E

Single 8-Pin DIP

Single SO-8

Widebody

V

CC

+ 0.5

V

Exceed V by more than

CC

500 mV)

Enable Input Current

Output Collector Current

Output Collector Voltage

I

V

O

5

50

7

mA

V

E

1

O

(Selection for Higher Output

Voltages up to 20 V is Available.)

Output Collector Power

Dissipation

P

O

Single 8-Pin DIP

Single SO-8

Widebody

Dual 8-Pin DIP

Dual SO-8

85

60

mW

1, 4

Lead Solder Temperature

(Through Hole Parts Only)

T

8-Pin DIP

260°C for 10 sec.,

1.6 mm below seating plane

LS

Widebody

260°C for 10 sec.,

up to seating plane

Solder Reflow Temperature

Profile (Surface Mount Parts Only)

SO-8 and

Option 300

See Package Outline

Drawings section

*JEDEC Registered Data (for 6N137 only).

**Ratings apply to all devices except otherwise noted in the Package column.

†0°C to 70°C on JEDEC Registration.

Recommended Operating Conditions

Parameter

Input Current, Low Level

Symbol

I_FL*

I_FH**

V_CC

Min.

0

5

4.5

0

2.0

-40

Max.

250

15

5.5

0.8

V_CC

85

Units

µA

mA

V

Input Current, High Level^[1]

Power Supply Voltage

Low Level Enable Voltage†

High Level Enable Voltage†

Operating Temperature

Fan Out (at R_L= 1 kΩ)^[1]

Output Pull-up Resistor

V_EL

V_EH

T_A

N

R_L

°C

TTL Loads

Ω

5

4 k

330

*The off condition can also be guaranteed by ensuring that V_FL≤ 0.8 volts.

**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit

at least a 20% LED degradation guardband.

†For single channel products only.

1-154

Electrical Specifications

Over recommended temperature (T_A= -40°C to +85°C) unless otherwise specified. All Typicals at V_CC= 5 V,

T_A= 25°C. All enable test conditions apply to single channel products only. See note 5.

Parameter

Sym.

Package

Min.

Typ. Max. Units

Test Conditions

Fig. Note

High Level Output I_OH

Current

*

All

5.5

100

µA

V

_CC= 5.5 V, V_E= 2.0 V,

1

1, 6,

19

V = 5.5 V, I_F= 250 µA

O

Input Threshold

Current

I_THSingle Channel

Widebody

2.0

5.0

mA

V

_CC= 5.5 V, V_E= 2.0 V, 2, 3

19

V_O= 0.6 V,

Dual Channel

2.5

I_OL(Sinking) = 13 mA

Low Level Output

Voltage

V_OL*

8-Pin DIP

SO-8

Widebody

0.35

0.6

V

V_CC= 5.5 V, V_E= 2.0 V, 2, 3, 1, 19

I_F= 5 mA, 4, 5

_OL(Sinking) = 13 mA

V_E= 0.5 V V_CC= 5.5 V

0.4

I

High Level Supply I_CCHSingle Channel

Current

7.0

6.5

10

10.0*

15

mA

7

V_E= V_CC

Both

I_F= 0 mA

Dual Channel

Channels

Low Level Supply

Current

I_CCLSingle Channel

Dual Channel

9.0

8.5

13

13.0*

21

mA

V_E= 0.5 V V_CC= 5.5 V

8

V_E= V_CC

Both

I_F= 10 mA

Channels

High Level Enable

Current

I_EHSingle Channel

-0.7

-0.9

-1.6

mA

V

V_CC= 5.5 V, V_E= 2.0 V

Low Level Enable

Current

I_EL*

V_CC= 5.5 V, V_E= 0.5 V

9

High Level Enable

Voltage

V_EH

V_EL

V_F

2.0

19

Low Level Enable

Voltage

0.8

V

Input Forward

Voltage

8-Pin DIP

SO-8

1.4

1.3

1.25

1.2

1.5

1.75*

1.80

1.85

2.05

V

T_A= 25°C I_F= 10 mA 6, 7

T_A= 25°C

1

Widebody

1.64

Input Reverse

Breakdown

Voltage

BV_R*

8-Pin DIP

SO-8

Widebody

5

V

I_R= 10 µA

1

3

I_R= 100 µA, T_A= 25°C

Input Diode

Temperature

Coefficient

∆V_F/

∆T_A

8-Pin DIP

SO-8

Widebody

-1.6

mV/°C I_F= 10 mA

7

-1.9

60

Input Capacitance

C_IN

8-Pin DIP

SO-8

pF

f = 1 MHz, V_F= 0 V

Widebody

70

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.

1-155

Switching Specifications (AC)

Over Recommended Temperature (T_A= -40°C to +85°C), V_CC= 5 V, I_F= 7.5 mA unless otherwise specified.

All Typicals at T_A= 25°C, V_CC= 5 V.

Parameter

Sym.

Package**

Min. Typ. Max. Units

Test Conditions

Fig. Note

Propagation Delay

Time to High

t_PLH

20

48

75*

100

ns T_A= 25°C R_L= 350 Ω 8, 9, 1, 10,

C_L= 15 pF 10

19

Output Level

Propagation Delay

Time to Low

t_PHL

25

50

75*

100

ns T_A= 25°C

1, 11,

19

Output Level

Pulse Width

Distortion

|t_PHL- t_PLH

|

8-Pin DIP

SO-8

Widebody

3.5

35

ns

8, 9, 13, 19

10,

11

40

Propagation Delay

Skew

t_PSK

t_r

ns

12, 13,

19

Output Rise

Time (10-90%)

24

10

30

12

1, 19

14

Output Fall

Time (90-10%)

t_f

Propagation Delay

Time of Enable

from V_EHto V_EL

t_ELH

Single Channel

ns R_L= 350 Ω,

13,

14

C_L= 15 pF,

V_EL= 0 V, V_EH= 3 V

Propagation Delay

Time of Enable

from V_ELto V_EH

t_EHL

20

ns

15

*JEDEC registered data for the 6N137.

**Ratings apply to all devices except otherwise noted in the Package column.

Parameter Sym.

Device

Min.

Typ. Units

Test Conditions

Fig. Note

Logic High |CM_H| 6N137

10,000 V/µs |V_CM| = 10 V V_CC= 5 V, I_F= 0 mA,

V_O(MIN)= 2 V,

15

1, 16,

18, 19

Common

Mode

HCPL-2630

HCPL-0600/0630

HCNW137

R_L= 350 Ω, T_A= 25°C

Transient

Immunity

HCPL-2601/2631

HCPL-0601/0631

HCNW2601

5,000 10,000

|V_CM| = 50 V

|V_CM| = 1 kV

HCPL-2611/4661 10,000 15,000

HCPL-0611/0661

HCNW2611

Logic Low

Common

Mode

Transient

Immunity

|CM_L| 6N137

HCPL-2630

10,000 V/µs |V_CM| = 10 V V_CC= 5 V, I_F= 7.5 mA,

V_O(MAX)= 0.8 V,

15

1, 17,

18, 19

HCPL-0600/0630

HCNW137

R_L= 350 Ω, T_A= 25°C

HCPL-2601/2631

HCPL-0601/0631

HCNW2601

HCPL-2611/4661 10,000 15,000

HCPL-0611/0661

HCNW2611

5,000 10,000

|V_CM| = 50 V

|V_CM| = 1 kV

1-156

Package Characteristics

All Typicals at T_A= 25°C.

Parameter

Sym.

I_I-O

Package

Min. Typ. Max. Units

Test Conditions

45% RH, t = 5 s,

_I-O= 3 kV dc, T = 25°C

Fig. Note

Input-Output

Insulation

*

Single 8-Pin DIP

Single SO-8

1

µA

20, 21

V

A

Input-Output

Momentary With-

stand Voltage**

V_ISO

8-Pin DIP, SO-8 2500

V rms RH ≤ 50%, t = 1 min,

T_A= 25°C

20, 21

20, 22

Widebody

OPT 020†

5000

Input-Output

Resistance

R_I-O

8-Pin DIP, SO-8

Widebody

10¹²

10¹³

Ω

V_I-O= 500 V dc

1, 20,

23

10¹²

10¹¹

T_A= 25°C

T_A= 100°C

Input-Output

Capacitance

C_I-O

I_I-I

8-Pin DIP, SO-8

Widebody

0.6

0.5

pF

f = 1 MHz, T_A= 25°C

1, 20,

23

0.6

Input-Input

Dual Channel

0.005

µA

RH ≤ 45%, t = 5 s,

24

Insulation

V_I-I= 500 V

Leakage Current

Resistance

(Input-Input)

R_I-I

C_I-I

Dual Channel

10¹¹

Ω

24

Capacitance

(Input-Input)

Dual 8-Pin DIP

Dual SO-8

0.03

0.25

pF

f = 1 MHz

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. HP specifies -40°C to 85°C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),

your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

†For 6N137, HCPL-2601/2611/2630/2631/4661 only.

Notes:

1. Each channel.

2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does

not exceed 20 mA.

3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does

not exceed 15 mA.

4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.

5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in

Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.

6. The JEDEC registration for the 6N137 specifies a maximum I_OHof 250 µA. HP guarantees a maximum I_OHof 100 µA.

7. The JEDEC registration for the 6N137 specifies a maximum I_CCHof 15 mA. HP guarantees a maximum I_CCHof 10 mA.

8. The JEDEC registration for the 6N137 specifies a maximum I_CCLof 18 mA. HP guarantees a maximum I_CCLof 13 mA.

9. The JEDEC registration for the 6N137 specifies a maximum I_ELof –2.0 mA. HP guarantees a maximum I_ELof -1.6 mA.

10. The t_PLHpropagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the

rising edge of the output pulse.

11. The t_PHLpropagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the

falling edge of the output pulse.

12. t_PSKis equal to the worst case difference in t_PHLand/or t_PLHthat will be seen between units at any given temperature and specified

test conditions.

13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.

14. The t_ELHenable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V

point on the rising edge of the output pulse.

15. The t_EHLenable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point

on the falling edge of the output pulse.

16. CM_His the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state

(i.e., V_O> 2.0 V).

17. CM_Lis the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state

(i.e., V_O< 0.8 V).

18. For sinusoidal voltages, (|dV_CM| / dt)_max= π f_CMV_CM(p-p).

1-157

19. No external pull up is required for a high logic state on the enable input. If the V_Epin is not used, tying V_Eto V_CCwill result in

improved CMR performance. For single channel products only.

20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second

(leakage detection current limit, I_I-O≤ 5 µA). This test is performed before the 100% production test for partial discharge

(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.

22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second

(leakage detection current limit, I_I-O≤ 5 µA). This test is performed before the 100% production test for partial discharge

(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.

23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products

only.

24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.

8-PIN DIP, SO-8

WIDEBODY

6

15

10

V

T

= 5 V

V

= 5 V

V

= 5.5 V

= 2.0 V*

= 250 µA

CC

= 25 °C

CC

T = 25 °C

A

CC

O

E

A

5

4

3

2

5

4

3

2

I

F

* FOR SINGLE

CHANNEL

PRODUCTS

ONLY

R

= 350 Ω

= 1 KΩ

R

= 350 Ω

= 1 KΩ

L

R

L

5

0

R

= 4 KΩ

R = 4 KΩ

L

1

0

1

0

-60 -40 -20

0

20 40 60 80 100

0

1

2

3

I – FORWARD INPUT CURRENT – mA

F

4

6

0

1

2

3

4

6

5

T

– TEMPERATURE – °C

I

– FORWARD INPUT CURRENT – mA

A

F

Figure 1. Typical High Level Output

Current vs. Temperature.

Figure 2. Typical Output Voltage vs. Forward Input Current.

8-PIN DIP, SO-8

6

WIDEBODY

6

V

= 5.0 V

V

= 5.0 V

CC

= 0.6 V

O

= 0.6 V

O

5

4

3

2

5

4

3

2

R

= 350 KΩ

L

R

= 1 KΩ

R

= 350 Ω

L

R

= 1 KΩ

L

1

0

1

0

R

= 4 KΩ

R = 4 KΩ

L

-60 -40 -20

0

20 40

80 100

-60 -40 -20

0

20 40

80 100

60

T

– TEMPERATURE – °C

T

A

– TEMPERATURE – °C

A

Figure 3. Typical Input Threshold Current vs. Temperature.

1-158

8-PIN DIP, SO-8

WIDEBODY

0.8

0.7

70

60

50

0.8

0.7

V

I

= 5.5 V * FOR SINGLE

V

I

= 5.5 V

V

= 5.0 V

= 2.0 V*

= 0.6 V

* FOR SINGLE

CHANNEL

PRODUCTS ONLY

CC

E

F

CC

= 2.0 V

F

CC

E

OL

= 2.0 V*

= 5.0 mA

CHANNEL

PRODUCTS ONLY

E

= 5.0 mA

0.6

0.5

0.4

0.3

0.2

0.6

0.5

0.4

0.3

0.2

I

= 16 mA

O

I

= 10-15 mA

F

I

= 16 mA

= 9.6 mA

I

= 12.8 mA

O

I

= 12.8 mA

= 6.4 mA

O

I

= 9.6 mA

I = 6.4 mA

O

I

O

I

= 5.0 mA

F

40

20

O

0.1

0

0.1

0

-60 -40 -20

0

20 40

80 100

60

-60 -40 -20

0

20 40

80 100

-60 -40 -20

0

20 40

80 100

60

T

– TEMPERATURE – °C

T

– TEMPERATURE – °C

T

– TEMPERATURE – °C

A

Figure 4. Typical Low Level Output Voltage vs. Temperature.

Figure 5. Typical Low Level Output

Current vs. Temperature.

8-PIN DIP, SO-8

T

WIDEBODY

1000

110

= 25 °C

T = 25 °C

A

100

10

100

10

I

F

+

V

F

+

F

V

–

1.0

0.1

0.01

0.1

0.01

0.001

1.1

1.2

1.3

1.4

1.5

1.6

1.2

1.3

V – FORWARD VOLTAGE – V

F

1.4

1.5

1.6

1.7

V

– FORWARD VOLTAGE – V

F

Figure 6. Typical Input Diode Forward Characteristic.

8-PIN DIP, SO-8

WIDEBODY

-2.4

-2.2

-2.3

-2.2

-2.0

-1.8

-1.6

-2.1

-2.0

-1.9

-1.8

-1.4

-1.2

0.1

1

10

100

0.1

1

10

I – PULSE INPUT CURRENT – mA

F

100

I

– PULSE INPUT CURRENT – mA

F

Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.

1-159

PULSE GEN.

= 50 Ω

Z

O

t

= t = 5 ns

r

f

SINGLE CHANNEL

DUAL CHANNEL

V

+5 V

I

F

I

F

PULSE GEN.

= 50 Ω

V

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CC

Z

O

R

L

t

= t = 5 ns

r

f

INPUT

MONITORING

NODE

OUTPUT V

O

MONITORING

NODE

0.1µF

BYPASS

R

L

0.1µF

BYPASS

OUTPUT V

MONITORING

NODE

INPUT

MONITORING

NODE

O

*C

L

R

C *

L

M

R

M

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

L

PROBE AND STRAY WIRING CAPACITANCE.

I

= 7.50 mA

= 3.75 mA

F

INPUT

I

F

t

PHL

PLH

OUTPUT

V

O

1.5 V

Figure 8. Test Circuit for t_PHLand t_PLH

.

100

105

V

I

= 5.0 V

V

= 5.0 V

CC

= 7.5 mA

CC

= 25°C

T

F

A

t

, R = 4 KΩ

L

80

t

, R = 4 KΩ

90

PLH

L

t

, R = 350 Ω

L

PHL

1 KΩ

4 KΩ

60

40

75

60

t

, R = 350 Ω

L

PLH

t

, R = 1 KΩ

L

PLH

t

, R = 1 KΩ

L

PLH

t

, R = 350 Ω

L

PLH

45

30

20

0

t

, R = 350 Ω

PHL

L

1 KΩ

4 KΩ

5

7

9

11

13

15

-60 -40 -20

0

20 40

80 100

60

I

– PULSE INPUT CURRENT – mA

T

– TEMPERATURE – °C

F

A

Figure 9. Typical Propagation Delay

vs. Temperature.

Figure 10. Typical Propagation Delay

vs. Pulse Input Current.

40

V

= 5.0 V

t

CC

I = 7.5 mA

F

RISE

FALL

R

= 4 kΩ

L

30

20

10

0

V

I

= 5.0 V

CC

= 7.5 mA

R

= 4 kΩ

= 1 kΩ

F

300

290

60

L

R

= 350 Ω

L

R

L

40

R

= 350 Ω

L

20

0

R

= 1 kΩ

L

= 350 Ω, 1 kΩ, 4 kΩ

L

0

-10

-60

-40 -20

0

20 40

80 100

60

-60 -40 -20

20 40 60 80 100

T

– TEMPERATURE – °C

T

– TEMPERATURE – °C

A

Figure 11. Typical Pulse Width

Distortion vs. Temperature.

Figure 12. Typical Rise and Fall Time

vs. Temperature.

1-160

PULSE GEN.

= 50 Ω

Z

O

t

= t = 5 ns

f

r

INPUT V

MONITORING NODE

E

+5 V

V

3.0 V

1.5 V

1

2

3

4

8

7

6

5

CC

INPUT

V

7.5 mA

E

0.1 µF

BYPASS

R

L

I

F

t

EHL

ELH

OUTPUT V

MONITORING

NODE

O

OUTPUT

V

O

1.5 V

*C

L

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

L

PROBE AND STRAY WIRING CAPACITANCE.

Figure 13. Test Circuit for t_EHLand t_ELH

.

120

V

= 5.0 V

= 3.0 V

= 0 V

CC

EH

EL

I

= 7.5 mA

F

90

60

t

, R = 4 kΩ

L

ELH

t

, R = 1 kΩ

ELH

L

30

0

t

, R = 350 Ω

ELH

L

t

, R = 350 Ω, 1 kΩ, 4 kΩ

EHL

L

-60 -40 -20

0

20 40 60 80 100

T

– TEMPERATURE – °C

A

Figure 14. Typical Enable Propagation

Delay vs. Temperature.

I

F

SINGLE CHANNEL

DUAL CHANNEL

B

I

F

V

1

2

3

4

8

7

6

5

+5 V

V

CC

+5 V

CC

1

2

3

4

8

A

R

B

A

L

OUTPUT V

MONITORING

NODE

0.1 µF

BYPASS

O

R

7

6

5

L

V

FF

OUTPUT V

MONITORING

NODE

O

V

FF

0.1 µF

BYPASS

GND

V

CM

V

CM

+

–

+

–

PULSE

GENERATOR

= 50 Ω

PULSE

GENERATOR

= 50 Ω

Z

O

V

CM

(PEAK)

V

CM

0 V

5 V

SWITCH AT A: I = 0 mA

F

CM

H

V

O

V

(MIN.)

O

SWITCH AT B: I = 7.5 mA

F

V

(MAX.)

O

V

O

0.5 V

CM

L

Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.

1-161

HCPL-2611 OPTION 060

(mW)

HCNWXXXX

P (mW)

S

800

700

600

500

400

300

200

100

0

P

S

I

(mA)

I (mA)

S

800

700

600

500

400

300

200

100

0

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

0

25

T – CASE TEMPERATURE – °C

S

50 75 100 125 150 175

T

S

Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with

Case Temperature per VDE 0884.

GND BUS (BACK)

V

BUS (FRONT)

NC

CC

ENABLE

OUTPUT

0.1µF

NC

10 mm MAX.

(SEE NOTE 5)

SINGLE CHANNEL

DEVICE ILLUSTRATED.

Figure 17. Recommended Printed Circuit Board Layout.

1-162

SINGLE CHANNEL DEVICE

5 V

8

6

V

CC1

V

CC2

390 Ω

470 Ω

I

F

+

2

3

D1*

V

0.1 µF

BYPASS

F

–

5

GND 1

GND 2

SHIELD

V

E

7

1

2

*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.

DUAL CHANNEL DEVICE

CHANNEL 1 SHOWN

5 V

8

7

V

CC1

V

CC2

390 Ω

470 Ω

I

F

+

1

2

D1*

V

0.1 µF

BYPASS

F

–

5

GND 1

GND 2

SHIELD

1

2

Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.

1-163

tions where synchronization of

signals on parallel data lines is a

concern. If the parallel data is

being sent through a group of

optocouplers, differences in

propagation delays will cause the

data to arrive at the outputs of the

optocouplers at different times. If

this difference in propagation

delays is large enough, it will

determine the maximum rate at

which parallel data can be sent

through the optocouplers.

signals at the inputs and outputs

of the optocouplers. To obtain the

maximum data transmission rate,

both edges of the clock signal are

being used to clock the data; if

only one edge were used, the

clock signal would need to be

twice as fast.

Propagation Delay, Pulse-

Width Distortion and

Propagation Delay Skew

Propagation delay is a figure of

merit which describes how

quickly a logic signal propagates

through a system. The propaga-

tion delay from low to high (t_PLH

)

is the amount of time required for

an input signal to propagate to

the output, causing the output to

change from low to high.

Similarly, the propagation delay

from high to low (t_PHL) is the

amount of time required for the

input signal to propagate to the

output causing the output to

change from high to low (see

Figure 8).

Propagation delay skew repre-

sents the uncertainty of where an

edge might be after being sent

through an optocoupler. Figure

20 shows that there will be

Propagation delay skew is defined

as the difference between the

minimum and maximum

propagation delays, either t_PLHor

t_PHL, for any given group of

optocouplers which are operating

under the same conditions (i.e.,

the same drive current, supply

voltage, output load, and

uncertainty in both the data and

the clock lines. It is important

that these two areas of uncertainty

not overlap, otherwise the clock

signal might arrive before all of

the data outputs have settled, or

some of the data outputs may

start to change before the clock

signal has arrived. From these

considerations, the absolute

minimum pulse width that can be

sent through optocouplers in a

parallel application is twice t_PSK. A

cautious design should use a

slightly longer pulse width to

ensure that any additional

Pulse-width distortion (PWD)

results when t_PLHand t_PHLdiffer in

value. PWD is defined as the

difference between t_PLHand t_PHL

and often determines the

maximum data rate capability of a

transmission system. PWD can be

expressed in percent by dividing

the PWD (in ns) by the minimum

pulse width (in ns) being

operating temperature). As

illustrated in Figure 19, if the

inputs of a group of optocouplers

are switched either ON or OFF at

the same time, t_PSKis the

difference between the shortest

propagation delay, either t_PLHor

t_PHL, and the longest propagation

uncertainty in the rest of the

circuit does not cause a problem.

transmitted. Typically, PWD on

the order of 20-30% of the

delay, either t_PLHor t_PHL

.

minimum pulse width is tolerable;

the exact figure depends on the

particular application (RS232,

RS422, T-l, etc.).

As mentioned earlier, t_PSKcan

determine the maximum parallel

data transmission rate. Figure 20

is the timing diagram of a typical

parallel data application with both

the clock and the data lines being

sent through optocouplers. The

figure shows data and clock

The t_PSKspecified optocouplers

offer the advantages of

guaranteed specifications for

propagation delays, pulsewidth

distortion and propagation delay

skew over the recommended

temperature, input current, and

power supply ranges.

Propagation delay skew, t_PSK, is

an important parameter to

consider in parallel data applica-

1-164

DATA

INPUTS

I

F

50%

CLOCK

1.5 V

V

O

DATA

I

F

OUTPUTS

CLOCK

t

PSK

V

1.5 V

O

t

PSK

t

PSK

Figure 19. Illustration of Propagation

Delay Skew - t

Figure 20. Parallel Data Transmission

Example.

.

PSK

1-165

型号:	HCPL-4661#300
生命周期：	Transferred
IHS 制造商：	AGILENT TECHNOLOGIES INC
包装说明：	0.300 INCH, SURFACE MOUNT, DIP-8
Reach Compliance Code：	unknown
风险等级：	5.33
其他特性：	UL RECOGNIZED, OPEN COLLECTOR
配置：	SEPARATE, 2 CHANNELS
标称数据速率：	10 MBps
最大正向电流：	0.015 A
最大绝缘电压：	3750 V
元件数量：	2
最大通态电流：	0.05 A
最高工作温度：	85 °C
最低工作温度：	-40 °C
光电设备类型：	LOGIC IC OUTPUT OPTOCOUPLER
最小供电电压：	4.5 V

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