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  • 北京元坤伟业科技有限公司

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  • 深圳市英信达电子有限公司

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产品型号HCPL-M611-500E的概述

HCPL-M611-500E 概述 HCPL-M611-500E 是一款高性能的光隔离器,由美国安森美半导体(ON Semiconductor)公司制造。该芯片主要用于信号传输的电气隔离,其工作原理基于光电耦合技术。它能够在维持电气隔离的同时,实现数据与电信号的有效传输,广泛应用于工业自动化、功率控制和数据通信等领域。光隔离器的使用在很多电子设备中是至关重要的,特别是在高压和高频环境下,能够有效保护下游电路,避免电压突变或噪声对其产生不良影响。 HCPL-M611-500E 的详细参数 HCPL-M611-500E 的一些关键技术参数包括: - 输入电压 (V_F) : 1.2V (典型值),可承受的最大输入电压为 1.5V。 - 工作电流 (I_F) : 10 mA 到 20 mA 之间。 - 输入灵敏度 : 50 µA,表示最小输入信号值。 - 输出电压 (V_O) : 5V 至 ...

产品型号HCPL-M611-500E的Datasheet PDF文件预览

HCPL-M600, HCPL-M601, HCPL-M611  
Small Outline, 5 Lead, High CMR,  
High Speed, Logic Gate Optocouplers  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
Surface Mountable  
Very Small, Low Profile JEDEC Registered Package  
Outline  
These small outline high CMR, high speed, logic gate  
optocouplers are single channel devices in a five lead  
miniature footprint. They are electrically equivalent to  
the following Avago optocouplers (except there is no  
output enable feature):  
Compatible with Infrared Vapor Phase Reflow and  
Wave Soldering Processes  
Internal Shield for High Common Mode Rejection (CMR)  
HCPL-M601: 10,000 V/μs at VCM = 50 V  
HCPL-M611: 15,000 V/μs at VCM = 1000 V  
SO-5 Package  
HCPL-M600  
HCPL-M601  
HCPL-M611  
Standard DIP  
6N137  
SO-8 Package  
HCPL-0600  
HCPL-0601  
HCPL-0611  
HCPL-2601  
HCPL-2611  
High Speed: 10 Mbd  
LSTTL/TTL Compatible  
Low Input Current Capability: 5 mA  
Guaranteed ac and dc Performance over Temperature:  
–40°C to 85°C  
The SO-5 JEDEC registered (MO-155) package outline  
does not require “through holes” in a PCB. This package  
occupies approximately one fourth the footprint area of  
the standard dual-in-line package. The lead profile is de-  
signed to be compatible with standard surface mount  
processes.  
Safety and regulatory approvals:  
-
UL recognized: 3750 Vac for 1 min. per U.L.  
(File No. 55361)  
-
-
CSA component acceptance Notice #5  
The HCPL-M600/01/11 optically coupled gates combine  
a GaAsP light emitting diode and an integrated high  
gain photon detector. The output of the detector I.C.  
is an Open-collector Schottky-clamped transistor. The  
internal shield provides a guaranteed common mode  
transient immunity specification of 5,000 V/μs for the  
HCPL-M601, and 10,000 V/μs for the HCPL-M611.  
IEC/EN/DIN EN 60747-5-2 approved for HCPL-M601/  
M611 Option 060.  
Lead Free Option  
Applications  
Isolated Line Receiver  
Simplex/Multiplex Data Transmission  
Computer-Peripheral Interface  
Microprocessor System Interface  
Digital Isolation for A/D, D/A Conversion  
Switching Power Supply  
This unique design provides maximum ac and dc circuit  
isolation while achievingTTL compatibility.The optocou-  
pleracanddcoperationalparametersareguaranteedfrom  
–40°C to 85°C allowing trouble free system performance.  
Instrument Input/Output Isolation  
Ground Loop Elimination  
Pulse Transformer Replacement  
CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's  
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in  
handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.  
The SO-5 JEDEC registered (MO-155) package outline  
does not require “through holes” in a PCB. This package  
occupies approximately one fourth the footprint area of  
the standard dual-in-line package. The lead profile is de-  
signed to be compatible with standard surface mount  
processes.  
This unique design provides maximum ac and dc circuit  
isolation while achieving TTL compatibility. The opto-  
coupler ac and dc operational parameters are guaran-  
teed from -40°C to 85°C allowing trouble free system  
performance.  
The HCPL-M600/01/11 are suitable for high speed logic  
interfacing, input/output buffering, as line receivers in  
environments that conventional line receivers cannot  
tolerate, and are recommended for use in extremely  
high ground or induced noise environments.  
The HCPL-M600/01/11 optically coupled gates combine  
a GaAsP light emitting diode and an integrated high  
gain photon detector. The output of the detector I.C.  
is an Open-collector Schottky-clamped transistor. The  
internal shield provides a guaranteed common mode  
transient immunity specification of 5,000 V/μs for the  
HCPL-M601, and 10,000 V/μs for the HCPL-M611.  
Ordering Information  
HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577.  
Option  
Part  
number  
RoHS  
Non RoHS  
Surface Gull  
Mount Wing  
Tape& UL 5000 Vrms/ IEC/EN/DIN EN  
Compliant Compliant  
Package  
Reel 1 Minute rating  
60747-5-2 Quantity  
HCPL-M600  
-000E  
-500E  
-000E  
-500E  
-560E  
No option  
#500  
X
X
X
X
X
100 per tube  
1500 per reel  
100 per tube  
1500 per reel  
1500 per reel  
SO-5  
X
HCPL-M601  
HCPL-M611  
No option  
#500  
SO-5  
X
X
-
X
To order, choose a part number from the part number column and combine with the desired option from the op-  
tion column to form an order entry. Combination of Option 020 and Option 060 is not available.  
Example 1:  
HCPL-M600-500E to order product of Surface Mount SO-5 package in Tape and Reel packaging with RoHS  
compliant.  
Example 2:  
HCPL-M601 to order product of Surface Mount SO-5 package in tube packaging and non RoHS compliant.  
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.  
Remarks:  
The notation ‘#XXXis used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE.  
2
Outline Drawing (JEDEC MO-155)  
ANODE  
1
3
6
5
V
V
CC  
MXXX  
XXX  
7.0 0.ꢀ  
(0.ꢀ76 0.00ꢁ)  
4.4 0.1  
(0.173 0.004)  
OUT  
CATHODE  
4
GND  
0.4 0.05  
(0.016 0.00ꢀ)  
3.6 0.1ꢂ  
(0.14ꢀ 0.004)  
0.10ꢀ 0.10ꢀ  
(0.004 0.004)  
0.ꢀ16 0.03ꢁ  
(0.00ꢁ5 0.0015)  
ꢀ.5 0.1  
(0.09ꢁ 0.004)  
7° MAX.  
1.ꢀ7  
0.71  
BSC  
MIN.  
(0.0ꢀꢁ)  
(0.050)  
MAX. LEAD COPLANARITY  
= 0.10ꢀ (0.004)  
DIMENSIONS IN MILLIMETERS (INCHES)  
ꢂ MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)  
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.  
Land Pattern Recommendation  
Schematic  
4.4  
(0.17)  
I
+
1
I
CC  
F
V
V
CC  
O
6
5
I
O
1.3  
(0.05)  
ꢀ.5  
(0.10)  
3
GND  
4
HCPL-M601/11 SHIELD  
ꢀ.0  
(0.0ꢁ0)  
0.64  
(0.0ꢀ5)  
TRUTH TABLE  
(POSITIVE LOGIC)  
USE OF A 0.1 μF BYPASS CAPACITOR  
MUST BE CONNECTED BETWEEN PINS  
6 AND 4 (SEE NOTE 1).  
ꢁ.ꢀ7  
(0.3ꢀ5)  
LED  
ON  
OUTPUT  
L
OFF  
H
Regulatory Information  
The HCPL-M600, HCPL-M601 and HCPL-M611 are approved by the following organizations:  
IEC/EN/DIN EN 60747-5-5 (Option 060 only)  
UL  
for HCPL-M601 and HCPL-M611  
Approval under UL 1577, component recognition pro-  
gram up to VISO = 3750 VRMS  
.
CSA  
Approval under CSA Component Acceptance Notice #5,  
File CA 88324.  
3
Insulation and Safety Related Specifications  
Parameter  
Symbol  
Value  
Units  
Conditions  
Minimum External Air Gap  
(External Clearance)  
L(101)  
5
mm  
Measured from input terminals to output terminals,  
shortest distance through air.  
Minimum External  
Tracking (External Creepage)  
L(102)  
CTI  
5
mm  
mm  
Measured from input terminals to output terminals,  
shortest distance path along body.  
Minimum Internal Plastic Gap  
(Internal Clearance)  
0.08  
Through insulation distance conductor to conductor,  
usually the straight line distance thickness between  
the emitter and detector.  
Tracking Resistance  
(Comparative Tracking Index)  
175  
IIIa  
V
DIN IEC 112/VDE 0303 Part 1  
Isolation Group  
Material Group (DIN VDE 0110, 1/89, Table 1)  
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)  
Description  
Symbol  
Characteristic  
Unit  
Installation classification per DIN VDE 0110/39, Table 1  
for rated mains voltage 150 Vrms  
for rated mains voltage 300 Vrms  
I – IV  
I – III  
Climatic Classification  
55/85/21  
2
Pollution Degree (DIN VDE 0110/1.89)  
Maximum Working Insulation Voltage  
VIORM  
VPR  
560  
Vpeak  
Vpeak  
Input to Output Test Voltage, Method b*  
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,  
Partial discharge < 5 pC  
1050  
Input to Output Test Voltage, Method a*  
VPR  
840  
Vpeak  
Vpeak  
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,  
Partial discharge < 5 pC  
Highest Allowable Overvoltage  
VIOTM  
6000  
(Transient Overvoltage tini =10 sec)  
Safety-limiting values – maximum values allowed in the event  
of a failure.  
Case Temperature  
Input Current**  
Output Power**  
TS  
150  
150  
600  
°C  
mA  
mW  
IS, INPUT  
PS, OUTPUT  
>109  
Insulation Resistance at TS, VIO = 500 V  
RS  
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/  
EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.  
** Refer to the following figure for dependence of PS and IS on ambient temperature.  
Recommended Operating Conditions  
Parameter  
Symbol  
IFL*  
IFH**  
VCC  
Min.  
0
Max.  
250  
15  
Units  
Input Current, Low Level  
Input Current, High Level  
Supply Voltage, Output  
Fan Out (RL = 1 kΩ)  
μA  
5
mA  
4.5  
5.5  
5
V
N
TTL Loads  
Output Pull-Up Resistor  
Operating Temperature  
RL  
330  
-40  
4,000  
85  
Ω
TA  
°C  
*
The off condition can also be guaranteed by ensuring that VF(o) ≤ 0.8 volts.  
** The initial switching threshold is 5mA or less. It is recommended that 6.3mA to 10mA be used for best performance and to permit at least a  
20% LED degradation guardband.  
4
Absolute Maximum Ratings  
(No Derating Required up to 85°C)  
Parameter  
Abs. Max.  
-55°C to +125°C  
-40°C to +85°C  
20 mA  
Storage Temperature  
Operating Temperature  
Forward Input Current - IF (see Note 2)  
Reverse Input Voltage - VR  
Supply Voltage - VCC (1 Minute Maximum)  
Output Collector Current - IO  
Output Collector Power Dissipation  
5 V  
7 V  
50 mA  
85 mW  
7 V  
Output Collector Voltage - VO  
(Selection for higher output voltages up to 20 V is available)  
Infrared and Vapor Phase Reflow Temperature  
see below  
Solder Reflow Thermal Profile  
300  
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.  
REFLOW HEATING RATE ꢀ.5°C 0.5°C/SEC.  
PEAK  
TEMP.  
ꢀ45°C  
PEAK  
TEMP.  
ꢀ40°C  
PEAK  
TEMP.  
ꢀ30°C  
ꢀ00  
ꢀ.5°C 0.5°C/SEC.  
SOLDERING  
TIME  
30  
160°C  
150°C  
140°C  
ꢀ00°C  
SEC.  
30  
SEC.  
3°C + 1°C/–0.5°C  
100  
PREHEATING TIME  
150°C, 90 + 30 SEC.  
50 SEC.  
TIGHT  
TYPICAL  
LOOSE  
ROOM  
TEMPERATURE  
0
0
50  
100  
150  
ꢀ00  
ꢀ50  
TIME (SECONDS)  
Note: Non-halide flux should be used.  
Recommended Pb-Free IR Profile  
TIME WITHIN 5 °C of ACTUAL  
PEAKTEMPERATURE  
t
p
ꢀ0-40 SEC.  
ꢀ60 +0/-5 °C  
T
T
p
ꢀ17 °C  
L
RAMP-UP  
3 °C/SEC. MAX.  
150 - ꢀ00 °C  
RAMP-DOWN  
6 °C/SEC. MAX.  
T
smax  
T
smin  
t
s
t
L
60 to 150 SEC.  
NOTES:  
PREHEAT  
60 to 1ꢁ0 SEC.  
ꢀ5  
THE TIME FROM ꢀ5 °C to PEAK  
TEMPERATURE = ꢁ MINUTES MAX.  
t ꢀ5 °C to PEAK  
TIME  
Note: Non-halide flux should be used.  
T
= ꢀ00 °C, T = 150 °C  
smin  
smax  
5
Insulation Related Specifications  
Parameter  
Symbol  
Value  
Units  
Conditions  
Min. External Air Gap  
(Clearance)  
L(IO1)  
≥5  
mm  
Measured from input terminals  
to output terminals  
Min. External Tracking Path  
(Creepage)  
L(IO2)  
CTI  
≥5  
mm  
mm  
V
Measured from input terminals  
to output terminals  
Min. Internal Plastic Gap  
(Clearance)  
0.08  
Through insulation distance  
conductor to conductor  
Tracking Resistance  
175  
IIIa  
DIN IEC 112/VDE 0303 Part 1  
Material Group DIN VDE 0109  
Isolation Group (per DIN VDE 0109)  
Electrical Specifications  
Over recommended temperature (TA = -40°C to 85°C) unless otherwise specified. (See note 1.)  
Parameter  
Symbol  
Min.  
Typ.*  
Max.  
Units  
Test Conditions  
Fig.  
Note  
Input Threshold  
Current  
ITH  
2
5
mA  
VCC = 5.5 V, IO ≥13 mA,  
13  
VO = 0.6 V  
High Level Output  
Current  
IOH  
VOL  
ICCH  
ICCL  
VF  
5.5  
0.4  
4
100  
0.6  
μA  
V
VCC = 5.5 V, VO = 5.5 V  
IF = 250 μA  
1
Low Level Output  
Voltage  
VCC = 5.5 V, IF = 5 mA,  
2, 4,  
5, 13  
IOL (Sinking) = 13 mA  
High Level Supply  
Current  
7.5  
mA  
mA  
V
VCC = 5.5 V, IF = 0 mA,  
VCC = 5.5 V, IF = 10 mA,  
Low Level Supply  
Current  
6
10.5  
Input Forward  
Voltage  
1.4  
1.75  
1.85  
T = 25°C, IF=10 mA  
A
3
1.5  
1.3  
5
IF = 10 mA  
IR = 10 μA  
Input Reverse  
Breakdown Voltage  
BVR  
CIN  
Input Capacitance  
60  
pF  
V = 0V, f = 1 MHz  
F
Input Diode  
Temperature  
Coefficient  
∆VF/∆T  
-1.6  
mV/°C  
IF = 10 mA  
12  
A
Input-Output  
Insulation  
V
3750  
VRMS  
RH ≤ 50%, t = 1 min.  
3, 4  
3
ISO  
Resistance  
(Input-Output)  
RI-O  
1012  
0.6  
Ω
VI-O = 500 V  
Capacitance  
CI-O  
pF  
f = 1 MHz  
3
(Input-Output)  
*All typicals at TA = 25°C, VCC = 5 V.  
6
Switching Specifications  
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.  
Device  
HCPL-  
Parameter  
Symbol  
Min.  
Typ.*  
Max. Unit  
Test Conditions  
Fig. Note  
Propagation  
Delay Time  
to High  
tPLH  
20  
48  
75  
ns  
TA = 25°C  
TA = 25°C  
RL = 350 Ω  
CL = 15 pF  
6, 7  
8
5
100  
Output Level  
Propagation  
Delay Time  
to Low  
tPHL  
25  
50  
75  
6, 7  
8
6
100  
Output Level  
Propagation  
Delay Skew  
tPSK  
|tPHL - tPLH  
trise  
40  
35  
10,  
11  
Pulse Width  
Distortion  
|
3.5  
24  
9
10  
Output Rise  
Time  
(10%-90%)  
10  
Output Fall  
Time  
tfall  
10  
10  
11  
(10%-90%)  
Common  
|CMH|  
M600  
M601  
M611  
10,000  
V/μs VCM = 10 V  
VCM = 50 V  
VO(min) = 2 V  
7, 9  
8, 9  
Mode Transient  
Immunity at High  
Output Level  
RL = 350 Ω  
IF = 0 mA  
TA = 25°C  
5,000 10,000  
10,000 15,000  
VCM = 1000 V  
Common  
|CMH|  
M600  
M601  
M611  
10,000  
5,000 10,000  
10,000 15,000  
VCM = 10 V  
VCM = 50 V  
VCM = 1000 V  
VO(max) = 0.8 V  
11  
Mode Transient  
Immunity at Low  
Output Level  
RL = 350 Ω  
IF = 7.5 mA  
TA = 25°C  
*All typicals at TA = 25°C, VCC = 5 V.  
Notes:  
1. Bypassing of the power supply line is required with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler. The total lead length be-  
tween both ends of the capacitor and the isolator pins should not exceed 10mm.  
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed  
20mA.  
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.  
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (Leakage detec-  
tion current limit, II-O ≤ 5 μA).  
5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the  
output pulse.  
6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the  
output pulse.  
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V  
>
OUT  
2.0V).  
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT > 0.8  
V).  
9. For sinusoidal voltages, (|dVCM|/dt)max = fCMVCM(p-p)  
.
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skewfor more information.  
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case  
operating condition range.  
7
15  
10  
0.5  
0.4  
100  
V
F
= 5.5 V  
T
= ꢀ5°C  
CC  
A
V
V
I
= 5.5 V  
CC  
= 5.5 V  
F
I
= 5.0 mA  
O
10  
= ꢀ50 μA  
I
F
+
I
= 1ꢀ.ꢁ mA  
O
V
1.0  
F
I
= 16 mA  
= 6.4 mA  
O
0.3  
0.ꢀ  
0.1  
0.1  
5
0
I
O
0.01  
I
= 9.6 mA  
O
0.001  
-60 -40 -ꢀ0  
0
ꢀ0 40 60 ꢁ0 100  
-60 -40 -ꢀ0  
0
ꢀ0 40 60 ꢁ0 100  
1.10 1.ꢀ0  
1.30 1.40  
1.50  
1.60  
T
– TEMPERATURE – °C  
A
T
– TEMPERATURE – °C  
V
– FORWARD VOLTAGE – VOLTS  
A
F
Figure 1. High Level Output Current vs. Temperature.  
Figure 2. Low Level Output Voltage vs. Temperature.  
Figure 3. Input Diode Forward Characteristic.  
6
PULSE GEN.  
V
T
= 5 V  
CC  
= ꢀ5 °C  
Z
= 50 Ω  
O
A
+5 V  
t = t = 5 ns  
5
4
3
f
r
I
F
V
1
3
6
5
4
CC  
R
L
R
= 350 Ω  
L
0.1μF  
BYPASS  
OUTPUT V  
O
MONITORING  
NODE  
R
= 1 KΩ  
L
ꢂC  
L
INPUT  
MONITORING  
NODE  
R
= 4 KΩ  
L
GND  
1
0
R
M
0
1
3
4
6
5
ꢂC IS APPROXIMATELY 15 pF WHICH INCLUDES  
L
I
– FORWARD INPUT CURRENT – mA  
F
PROBE AND STRAY WIRING CAPACITANCE.  
Figure 4. Output Voltage vs. Forward Input current.  
I
I
= 7.5 mA  
F
INPUT  
= 3.75 mA  
F
I
F
t
t
PLH  
PHL  
ꢁ0  
OUTPUT  
V
V
V
= 5.0 V  
= 0.6 V  
O
CC  
OL  
1.5 V  
60  
40  
I
I
= 10 mA, 15 mA  
= 5.0 mA  
F
F
Figure 6. Test Circuit for tPHL and tPLH  
.
ꢀ0  
0
-60 -40 -ꢀ0  
0
ꢀ0 40 60 ꢁ0 100  
T
– TEMPERATURE – °C  
A
Figure 5. Low Level Output Current vs. Temperature.  
8
100  
ꢁ0  
105  
90  
40  
30  
ꢀ0  
10  
V
I
= 5.0 V  
V
T
= 5.0 V  
CC  
= 7.5 mA  
CC  
= ꢀ5°C  
R
= 4 kΩ  
L
F
A
t
, R = 4 KΩ  
L
t
, R = 4 KΩ  
L
PLH  
PLH  
V
F
= 5.0 V  
CC  
= 7.5 mA  
t
, R = 350 Ω  
L
PHL  
I
1 KΩ  
4 KΩ  
60  
40  
75  
60  
t
PLH  
, R = 350 Ω  
L
R
= 350 kΩ  
L
t
, R = 1 KΩ  
L
PLH  
t
, R = 1 KΩ  
L
PLH  
t
, R = 350 Ω  
L
PLH  
45  
30  
0
ꢀ0  
0
t
, R = 350 Ω  
PHL  
L
R
= 1 kΩ  
L
1 KΩ  
4 KΩ  
-10  
-60 -40 -ꢀ0  
0
ꢀ0 40  
ꢁ0 100  
5
7
9
11  
13  
15  
-60 -40 -ꢀ0  
0
ꢀ0 40  
ꢁ0 100  
60  
60  
I
– PULSE INPUT CURRENT – mA  
T
– TEMPERATURE – °C  
T
– TEMPERATURE – °C  
F
A
A
Figure 7. Propagation Delay vs. Temperature.  
Figure 8. Propagation Delay vs. Pulse Input Current.  
Figure 9. Pulse Width Distortion vs. Temperature.  
I
F
V
= 5.0 V  
t
t
CC  
= 7.5 mA  
RISE  
FALL  
+5 V  
I
B
A
F
V
1
3
CC  
6
5
4
350 Ω  
OUTPUT V  
0.1 μF  
BYPASS  
O
R
= 4 kΩ  
= 1 kΩ  
300  
ꢀ90  
60  
L
MONITORING  
NODE  
V
FF  
R
L
GND  
40  
R
R
= 350 Ω  
L
ꢀ0  
0
_
+
PULSE  
GENERATOR  
= 50 Ω  
= 350 Ω, 1 kΩ, 4 kΩ  
ꢀ0 40 60 ꢁ0 100  
L
0
-60 -40 -ꢀ0  
Z
O
T
– TEMPERATURE – °C  
A
V
(PEAK)  
CM  
V
CM  
Figure 10. Rise and Fall Time vs. Temperature.  
0 V  
5 V  
SWITCH AT A: I = 0 mA  
F
CM  
H
V
V
O
V
(MIN.)  
O
SWITCH AT B: I = 7.5 mA  
F
V
(MAX.)  
O
O
CM  
0.5 V  
L
-ꢀ.4  
-ꢀ.ꢀ  
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.  
-ꢀ.0  
-1.ꢁ  
-1.6  
-1.4  
-1.ꢀ  
0.1  
1
10  
100  
I
– PULSE INPUT CURRENT – mA  
F
Figure 12. Temperature Coefficient for Forward Voltage  
vs. Input Current.  
9
Propagation Delay,  
Pulse-Width Distortion and Propagation Delay Skew  
puts of a group of optocouplers are switched either ON  
or OFF at the same time, tPSK is the difference between  
the shortest propagation delay, either tPLH or tPHL, and  
Propagation delay is a figure of merit which describes  
how quickly a logic signal propagates through a sys-  
tem. The propagation delay from low to high (tPLH) is the  
amount of time required for an input signal to propagate  
to the output, causing the output to change from low to  
high. Similarly, the propagation delay from high to low  
(tPHL) is the amount of time required for the input sig-  
nal to propagate to the output, causing the output to  
change from high to low (see Figure 7).  
the longest propagation delay, either tPLH or tPHL  
.
As mentioned earlier, tPSK can determine the maximum  
parallel data transmission rate. Figure 11 is the timing  
diagram of a typical parallel data application with both  
the clock and the data lines being sent through opto-  
couplers. The figure shows data and clock signals at the  
inputs and outputs of the optocouplers. To obtain the  
maximum data transmission rate, both edges of the  
clock signal are being used to clock the data; if only one  
edge were used, the clock signal would need to be twice  
as fast.  
Pulse-width distortion (PWD) results when tPLH and tPHL  
differ in value. PWD is defined as the difference between  
tPLH and tPHL and often determines the maximum data  
rate capability of a transmission system. PWD can be  
expressed in percent by dividing the PWD (in ns) by the  
minimum pulse width (in ns) being transmitted. Typi-  
cally, PWD on the order of 20-30% of the minimum pulse  
width is tolerable; the exact figure depends on the par-  
ticular application (RS232, RS422, T-1, etc.).  
Propagation delay skew represents the uncertainty of  
where an edge might be after being sent through an op-  
tocoupler. Figure 16 shows that there will be uncertainty  
in both the data and the clock lines. It is important that  
these two areas of uncertainty not overlap, otherwise  
the clock signal might arrive before all of the data out-  
puts have settled, or some of the data outputs may start  
to change before the clock signal has arrived. From these  
considerations, the absolute minimum pulse width that  
can be sent through optocouplers in a parallel applica-  
tion is twice tPSK. A cautious design should use a slightly  
longer pulse width to ensure that any additional uncer-  
tainty in the rest of the circuit does not cause a prob-  
lem.  
Propagation delay skew, tPSK, is an important param-  
eter to consider in parallel data applications where  
synchronization of signals on parallel data lines is a con-  
cern. If the parallel data is being sent through a group  
of optocouplers, differences in propagation delays will  
cause the data to arrive at the outputs of the optocou-  
plers at different times. If this difference in propagation  
delays is large enough, it will determine the maximum  
rate at which parallel data can be sent through the op-  
tocouplers.  
The tPSK specified optocouplers offer the advantages of  
guaranteed specifications for propagation delays, pulse-  
width distortion and propagation delay skew over the  
recommended temperature, and input current, and  
power supply ranges.  
Propagation delay skew is defined as the difference be-  
tween the minimum and maximum propagation delays,  
either tPLH or tPHL, for any given group of optocouplers  
which are operating under the same conditions (i.e., the  
same drive current, supply voltage, output load, and op-  
erating temperature). As illustrated in Figure 15, if the in-  
6
5
4
3
5 V  
6
5
5 V  
V
V
= 5.0 V  
CC  
= 0.6 V  
V
1
V
CC  
CC  
O
390 Ω  
470  
ꢂD1  
I
F
1
3
R
= 350 Ω  
L
V
0.1 μF  
BYPASS  
F
R
R
= 1 kΩ  
= 4 kΩ  
L
4
GND 1  
GND ꢀ  
SHIELD  
1
1
0
L
ꢂ DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED  
FOR UNITS WITH OPEN COLLECTOR OUTPUT.  
-60 -40 -ꢀ0  
0
ꢀ0 40 60 ꢁ0 100  
T
– TEMPERATURE – °C  
A
Figure 13. Input Threshold Current vs. Temperature.  
Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.  
DATA  
INPUTS  
I
F
50%  
50%  
CLOCK  
1.5 V  
V
O
DATA  
I
F
OUTPUTS  
t
PSK  
V
1.5 V  
O
CLOCK  
t
PSK  
t
PSK  
Figure 15. Illustration of Propagation Delay Skew  
– tPSK  
Figure 16. Parallel Data Transmission Example.  
.
For product information and a complete list of distributors, please go to our website: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.  
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0562EN  
AV02-0941EN - February 23, 2010  
配单直通车
HCPL-M611-500E产品参数
型号:HCPL-M611-500E
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:AVAGO TECHNOLOGIES INC
包装说明:ROHS COMPLIANT, MO-155, SOP-5
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8541.40.80.00
Factory Lead Time:22 weeks
风险等级:0.84
Is Samacsys:N
其他特性:TTL COMPATIBLE, UL RECOGNIZED
配置:SINGLE
标称数据速率:10 MBps
最大正向电流:0.02 A
最大正向电压:1.75 V
最大绝缘电压:3750 V
JESD-609代码:e3
安装特点:SURFACE MOUNT
元件数量:1
最大通态电流:0.05 A
最高工作温度:85 °C
最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER
最大功率耗散:0.085 W
子类别:Optocoupler - Transistor Outputs
最小供电电压:4.5 V
表面贴装:YES
端子面层:Matte Tin (Sn)
Base Number Matches:1
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