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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT125

Quad buffer/line driver; 3-state

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Quad buffer/line driver; 3-state

74HC/HCT125

FEATURES

• Output capability: bus driver

• I_CCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled

by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a HIGH impedance OFF-state.

The “125” is identical to the “126” but has active LOW enable inputs.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

t_PHL/ t_PLH

PARAMETER

CONDITIONS

UNIT

HC

HCT

propagation delay nA to nY

input capacitance

C_L= 15 pF; V_CC= 5 V

9

12

ns

pF

C_I

3.5

22

3.5

24

C_PD

power dissipation capacitance per buffer

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in V

∑ (C_L× V_CC²× f_o) = sum of outputs

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

2

Philips Semiconductors

Product speciﬁcation

Quad buffer/line driver; 3-state

74HC/HCT125

PIN DESCRIPTION

PIN NO.

1, 4, 10, 13

2, 5, 9, 12

3, 6, 8, 11

7

SYMBOL

1OE to 4OE

1A to 4A

1Y to 4Y

GND

NAME AND FUNCTION

outputs enable inputs (active LOW)

data inputs

data outputs

ground (0 V)

14

V_CC

positive supply voltage

(a)

(b)

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

FUNCTION TABLE

INPUTS

OUTPUT

nY

nOE

nA

L

H

L

H

X

L

H

Z

Note

1. H = HIGH voltage level

L = LOW voltage level

X = don’t care

Z = high impedance OFF-state

Fig.4 Functional diagram.

Fig.5 Logic diagram (one buffer).

December 1990

3

Philips Semiconductors

Product speciﬁcation

Quad buffer/line driver; 3-state

74HC/HCT125

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

ns

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA to nY

30 100

125

25

150

30

2.0 Fig.6

11

9

20

17

4.5

21

26

6.0

t

_PZH/ t_PZL3-state output enable time

nOE to nY

41 125

15 25

12 21

41 125

15 25

12 21

14 60

155

31

190

38

ns

2.0 Fig.7

4.5

26

32

6.0

_PHZ/ t_PLZ3-state output disable time

nOE to nY

155

31

190

38

ns

2.0 Fig.7

4.5

26

32

6.0

_THL/ t_TLHoutput transition time

75

90

ns

2.0 Fig.6

5

4

12

10

15

18

4.5

6.0

13

15

December 1990

4

Philips Semiconductors

Product speciﬁcation

Quad buffer/line driver; 3-state

74HC/HCT125

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

nA, nOE

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA to nY

15 25

15 28

15 25

31

35

31

15

38

42

38

18

ns

4.5 Fig.6

4.5 Fig.7

4.5 Fig.6

t

_PZH/ t_PZL3-state output enable time

nOE to nY

_PHZ/ t_PLZ3-state output disable time

nOE to nY

_THL/ t_TLHoutput transition time

5

12

December 1990

5

Philips Semiconductors

Product speciﬁcation

Quad buffer/line driver; 3-state

74HC/HCT125

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

.

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.

(1) HC : V_M= 50%; V_I= GND to V_CC

.

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the 3-state enable and disable times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

6

型号:	HCT14-SERIES
生命周期：	Contact Manufacturer
IHS 制造商：	KAPPA NETWORKS INC
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.7
Base Number Matches：	1

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