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HD61830/HD61830B

LCDC (LCD Timing Controller)

ADE-207-275(Z)

'99.9

Rev. 0.0

Description

The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the

display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal

driving signals.

It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on

liquid crystal display and a character mode in which characters are displayed by storing character codes in

the external RAM and developing them into the dot patterns with the internal character generator ROM.

Both modes can be provided for various applications.

The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS

microcontroller it can complete a liquid crystal display device with lower power dissipation.

Features

•

Dot matrix liquid crystal graphic display controller

Display control capacity

Graphic mode: 512k dots (2¹⁶bytes)

Character mode: 4096 characters (2¹²characters)

Internal character generator ROM: 7360 bits

160 types of 5 × 7 dot characters

•

32 types of 5 × 11 dot characters

Total 192 characters

Can be extended to 256 characters (4 kbytes max.) with external ROM

1

HD61830/HD61830B

•

Interfaces to 8-bit MPU

Display duty cycle (can be selected by a program)

Static to 1/128 duty cycle

•

Various instruction functions

Scroll, cursor on/off/blink, character blink, bit manipulation

Display method: Selectable A or B types

Internal oscillator (with external resistor and capacitor) HD61830

Operating frequency

•

1.1 MHz HD61830

2.4 MHz HD61830B

•

Low power dissipation

Power supply: Single +5 V ±10%

CMOS process

2

HD61830/HD61830B

Differences between Products

HD61830 and HD61830B

HD61830

HD61830B

Oscillator

Internal or external

1.1 MHz

External only

2.4 MHz

Operating frequency

Pin arrangement

and signal name

Pin 6: C

Pin 7: R

Pin 9: CPO

Pin 6: CE

Pin 7: OE

Pin 9: NC

Package marking

to see figure

A

B

Package Marking

3D13

Lot No.

HD61830A00

A

JAPAN

Lot No.

3D13

HD61830B00

B

JAPAN

Ordering Information

Type No.

Package

HD61830A00H

HD61830B00H

60-pin plastic QFP (FP-60)

3

HD61830/HD61830B

Pin Arrangement

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

MA10

MA11

MA12

MA13

MA14

MA15

D2

(CE) C

(OE) R

CR

6

7

8

(NC) CPO

FLM

CL1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

SYNC

WE

D1

CL2

FP-60

(Top view)

RES

CS

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

MD0

MD1

E

R/W

RS

MA

GND

DB7

DB6

DB5

( ) is for HD61830B

4

HD61830/HD61830B

Terminal Functions

Symbol

Pin Number I/O

Function

DB0–DB7

28–21

I/O

Data bus: Three-state I/O common terminal

Data is transferred to MPU through DB0 to DB7.

CS

15

17

I

Chip select: Selected state with CS = 0

R/W

Read/Write:R/W = 1: MPU ← HD61830

R/W = 0: MPU → HD61830

RS

E

18

16

I

Register select:RS = 1: Instruction register

RS = 0: Data register

Enable: Data is written at the fall of E

Data can be read while E is 1

CR

C

8

6

7

9

6

I

CR oscillator (HD61830), External clock input (HD61830B)

CR oscillator to capacitor (HD61830 only)

—

O

R

CR oscillator to resistor (HD61830 only)

CPO

CE

Clock signal for HD61830 in slave mode (HD61830 only)

Chip enable (HD61830B only)

CE = 0: Chip enables make external RAM in active

OE

7

9

O

Output enable (HD61830B only)

OE = 1: Output enable informs external RAM that HD61830B requires

data bus

NC

Open Unused terminal. Don’t connect any wires to this terminal

(HD61830B only)

MA0–MA15 4–1, 60–49

O

External RAM address output

In character mode, the line code for external CG is output through

MA12 to MA15 (0: Character 1st line, F: Character 16th line)

MD0–MD7

RD0–RD7

WE

37–30

45–38

13

I/O

I

Display data bus: Three-state I/O common terminal

ROM data input: Dot data from external character generator is input

Write enable: Write signal for external RAM

O

CL2

46

Display data shift clock for LCD drivers

CL1

11

Display data latch signal for LCD drivers

FLM

10

Frame signal for display synchronization

MA

19

Signal for converting liquid crystal driving signal into AC, A type

Signal for converting liquid crystal driving signal into AC, B type

MB

5

D1

47

Display data serial output

D1: For upper half of screen

D2: For lower half of screen

D2

48

SYNC

RES

12

14

I/O

I

Synchronous signal for parallel operation

Three-state I/O common terminal (with pull-up MOS)

Master: Synchronous signal is output

Slave: Synchronous signal is input

Reset: Reset = 0 results in display off, slave mode and H_p= 6

5

HD61830/HD61830B

Block Diagram

M u l t i p l e x e r

I / O i n t e r f a c e c i r c u i t

6

HD61830/HD61830B

Block Functions

Registers

The HD61830/HD61830B has the five types of registers: instruction register (IR), data input register (DIR),

data output register (DOR), dot registers (DR), and mode control register (MCR).

The IR is a 4-bit register that stores the instruction codes for specifying MCR, DR, a start address register,

a cursor address register, and so on. The lower order 4 bits DB0to DB3 of data buses are written in it.

The DIR is an 8-bit register used to temporarily store the data written into the external RAM, DR, MCR,

and so on.

The DOR is an 8-bit register used to temporarily store the data read from the external RAM. Cursor address

information is written into the cursor address counter (CAC) through the DIR. When the memory read

instruction is set in the IR (latched at the falling edge of E signal), the data of external RAM is read to DOR

by an internal operation. The data is transferred to the MPU by reading the DOR with the next instruction

(the contents of DOR are output to the data bus when E is at the high level).

The DR are registers used to store dot information such as character pitches and the number of vertical

dots, and so on. The information sent from the MPU is written into the DR via the DIR.

The MCR is a 6-bit register used to store the data which specifies states of display such as display on/off

and cursor on/off/blink. The information sent from the MPU is written in it via the DIR.

Busy Flag (BF)

The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot be

accepted. As shown in Control Instruction, read busy flag, the busy flag is output on DB7 under the

conditions of RS = 1, R/W = 1, and E = 1. Make sure the busy flag is 0 before writing the next instruction.

Dot Counters (DC)

The dot counters are counters that generate liquid crystal display timing according to the contents of DR.

7

HD61830/HD61830B

Refresh Address Counters (RAC1/RAC2)

The refresh address counters, RAC1 and RAC2, control the addresses of external RAM, character generator

ROM (CGROM), and extended external ROM. The RAC1 is used for the upper half of the screen and the

RAC2 for the lower half. In the graphic mode, 16-bit data is output and used as the address signal of

external RAM. In the character mode, the high order 4 bits (MA12–MA15) are ignored. The 4 bits of line

address counter are output instead and used as the address of extended ROM.

Character Generator ROM

The character generator ROM has 7360 bits in total and stores 192 types of character data. A character code

(8 bits) from the external RAM and a line code (4 bits) from the line address counter are applied to its

address signals, and it outputs 5-bit dot data.

The character font is 5 × 7 (160 characters) or 5 × 11 (32 characters). The use of extended ROM allows 8 ×

16 (256 characters max.) to be used.

Cursor Address Counter

The cursor address counter is a 16-bit counter that can be preset by instruction. It holds an address when the

data of external RAM is read or written (when display dot data or a character code is read or written). The

value of the cursor address counter is automatically increased by 1 after the display data is read or written

and after the set/clear bit instruction is executed.

Cursor Signal Generator

The cursor can be displayed by instruction in character mode. The cursor is automatically generated on the

display specified by the cursor address and cursor position.

Parallel/Serial Conversion

The parallel data sent from the external RAM, character generator ROM, or extended ROM is converted

into serial data by two parallel/serial conversion circuits and transferred to the liquid crystal driver circuits

for upper screen and lower screen simultaneously.

8

HD61830/HD61830B

Display Control Instructions

Display is controlled by writing data into the instruction register and 13 data registers. The RS signal

distinguishes the instruction register from the data registers. 8-bit data is written into the instruction register

with RS = 1, and the data register code is specified. After that, the 8-bit data is written in the data register

and the specified instruction is executed with RS = 0.

During the execution of the instruction, no new instruction can be accepted. Since the busy flag is set

during this, read the busy flag and make sure it is 0 before writing the next instruction.

1. Mode Control: (Execution time: 4 µs) Code H'00 (hexadecimal) written into the instruction register

specifies the mode control register.

Register

R/W

0

RS

1

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

Instruction reg.

Mode control reg.

0

Mode data

Graphic/character

display

DB5

1/0

DB4

1/0

DB3

DB2

DB1

0

DB0

Cursor/blink

Cursor off

Cursor on

CG

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Character display

(Character mode)

Cursor off, character blink

Cursor blink

Cursor off

Cursor on

Cursor off, character blink

Cursor blink

1

Graphic mode

1: Master mode

0: Slave mode

1: Display ON

0: Display OFF

9

HD61830/HD61830B

2. Set Character Pitch: (Execution time: 4 µs) V_pindicates the number of vertical dots per character. The

space between the vertically-displayed characters is included in the determination. This value is meaningful

only during character display (in the character mode) and becomes invalid in the graphic mode.

H_pindicates the number of horizontal dots per character in display, including the space between

horizontally-displayed characters. In the graphic mode, the H_pindicates the number of bits of 1-byte display

data to be displayed.

There are three H_pvalues (Table 1).

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

Character pitch reg.

0

1

0

(V_p– 1) binary

(H_p– 1) binary

Table 1

H_pValues

H_p

6

DB2

DB1

DB0

Horizontal Character Pitch

1

0

1

0

1

6

7

8

7

8

10

HD61830/HD61830B

3. Set Number of Characters: (Execution time: 4 µs) H_Nindicates the number of horizontal characters in

the character mode or the number of horizontal bytes in the graphic mode. If the total sum of horizontal

dots on the screen is taken as n,

n = H_p× H_N

H_Ncan be set to an even number from 2 to 128 (decimal).

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

0

Number-of-characters reg.

0

(H_N– 1) binary

4. Set Number of Time Divisions (Inverse of Display Duty Ratio): (Execution time: 4 µs) N_Xindicates

the number of time divisions in multiplex display.

1/N_Xis the display duty ratio.

A value of 1 to 128 (decimal) can be set to N_X.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

Number-of-time-divisions reg.

0

(N_X– 1) binary

5. Set Cursor Position: (Execution time: 4 µs) C_pindicates the position in a character where the cursor is

displayed in the character mode. For example, in 5 × 7 dot font, the cursor is displayed under a character by

specifying C_p= 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch H_p. A

value of 1 to 16 (decimal) can be set to C_p. If a smaller value than the vertical character pitch Vp is set (C_p

≤ Vp), and a character overlaps with the cursor, the cursor has higher priority of display (at cursor display

on). If C_pis greater than Vp, no cursor is displayed. The cursor horizontal length is equal to H_p.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

Cursor position reg.

0

1

0

(C_p– 1) binary

11

HD61830/HD61830B

6. Set Display Start Low Order Address: (Execution time: 4 µs) Cause display start addresses to be

written in the display start address registers. The display start address indicates a RAM address at which the

data displayed at the top left end on the screen is stored. In the graphic mode, the start address is composed

of high/low order 16 bits. In the character display, it is composed of the lower 4 bits of high order address

(DB3–DB0) and 8 bits of low order address. The upper 4 bits of high order address are ignored.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

0

Display start address reg.

(low order byte)

0

(Start low order address) binary

Set Display Start High Order Address

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

0

1

Display start address reg.

(high order byte)

0

(Start high order address) binary

7. Set Cursor Address (Low Order) (RAM Write Low Order Address): (Execution time: 4 µs) Cause

cursor addresses to be written in the cursor address counters. The cursor address indicates an address for

sending or receiving display data and character codes to or from the RAM.

That is, data at the address specified by the cursor address are read/written. In the character mode, the

cursor is displayed at the character specified by the cursor address.

A cursor address consists of the low-order address (8 bits) and the high-order address (8 bits). Satisfy the

following requirements setting the cursor address (Table 2).

The cursor address counter is a 16-bit up-counter with set and reset functions. When bit N changes from 1

to 0, bit N + 1 is incremented by 1. When setting the low order address, the LSB (bit 1) of the high order

address is incremented by 1 if the MSB (bit 8) of the low order address changes from 1 to 0. Therefore, set

both the low order address and the high order address as shown in the Table 2.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

0

1

0

Cursor address counter

(low order byte)

0

(Cursor low order address) binary

12

HD61830/HD61830B

Set Cursor Address (High Order) (RAM Write High Order Address)

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

0

1

0

1

Cursor address counter

(high order byte)

0

(Cursor high order address) binary

Table 2

Cursor Address Setting

Condition

Requirement

When you want to rewrite (set ) both the low order

address and the high order address.

Set the low order address and then set the high

order address.

When you want to rewrite only the low order address. Do not fail to set the high order address again after

setting the low order address.

When you want to rewrite only the high order address. Set the high order address. You do not have to set

the low order address again.

13

HD61830/HD61830B

8. Write Display Data: (Execution time: 6 µs) After the code $“0C” is written into the instruction register

with RS = 1, 8-bit data with RS = 0 should be written into the data register. This data is transferred to the

RAM specified by the cursor address as display data or character code. The cursor address is increased by 1

after this operation.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

RAM

0

1

0

MSB (pattern data, character code) LSB

9. Read Display Data: (Execution time: 6 µs) Data can be read from the RAM with RS = 0 after writing

code $“0D” into the instruction register. Figure 1 shows the read procedure.

This instruction outputs the contents of data output register on the data bus (DB0 to DB7) and then

transfers RAM data specified by the cursor address to the data output register, also increasing the cursor

address by 1. After setting the cursor address, correct data is not output at the first read but at the second

one. Thus, make one dummy read when reading data after setting the cursor address.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

RAM

0

1

0

1

0

MSB (pattern data, character code) LSB

CS

E

R/W

RS

(N+1)

B

0A

N_L

B

OB

N_U

B

0D

B

(N)

B

DB

*

Busy Cursor Cursor Busy Cursor Cursor Busy

Data

Dummy Busy

N

Busy N + 1

check address low

check address high

check read

mode

read check address check address

set

order

set

order

data

read

data

read

mode

address

write

mode

address

write

Cursor

address

N_L

N

N + 1

N + 2

N + 3

...

Data output

register

N address data N + 1 address data N + 2

Figure 1 Read Procedure

14

HD61830/HD61830B

10. Clear Bit: (Execution time: 36 µs) The clear/set bit instruction sets 1 bit in a byte of display data RAM

to 0 or 1, respectively. The position of the bit in a byte is specified by N_Band RAM address is specified by

cursor address. After the execution of the instruction, the cursor address is automatically increased by 1. N_B

is a value from 1 to 8. N_B= 1 and N_B= 8 indicates LSB and MSB, respectively.

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

Bit clear reg.

0

1

0

1

0

(N_B– 1) binary

Set Bit

Register

R/W

0

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction reg.

Bit set reg.

0

1

0

1

0

(N_B– 1) binary

11. Read Busy Flag: (Execution time: 0 µs) When the read mode is set with RS = 1, the busy flag is

output to DB7. The busy flag is set to 1 during the execution of any of the other instructions. After the

execution, it is set to 0. The next instruction can be accepted. No instruction can be accepted when busy

flag = 1. Before executing an instruction or writing data, perform a busy flag check to make sure the busy

flag is 0. When data is written in the register (RS = 1), no busy flag changes. Thus, no busy flag check is

required just after the write operation into the instruction register with RS = 1.

The busy flag can be read without specifying any instruction register.

Register

R/W

1

RS

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1/0

Busy flag

*

15

HD61830/HD61830B

H_p

RD0

RD7

CURA

STA

H_N(digit)

Symbol

H_p

Name

Meaning

Value

Horizontal character pitch

6 to 8 dots

2 to 128 digits

H_N

Number of horizontal

characters

Number of horizontal characters per

line (number of digits) in the character (an even number)

mode or number of bytes per line in

the graphic mode

V_p

C_p

Vertical character pitch

Cursor position

Vertical character pitch

1 to 16 dots

1 to 16 lines

Line number on which the cursor

can be displayed

N_X

Number of time divisions

Inverse of display duty ratio

1 to 128 lines

Note: If the number of vertical dots on the screen is m, and the number of horizontal dots is n,

1/m = 1/N_X= display duty ratio

n = H_p× H_N,

m/V_p= Number of display lines

C_p≤ V_p

Figure 2 Display Variables

16

HD61830/HD61830B

Display Mode

17

HD61830/HD61830B

Internal Character Generator Patterns and Character Codes

Higher

4 bits

Lower

4 bits

0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

xxxx1111

18

HD61830/HD61830B

Example of Correspondence between External CGROM Address Data and

Character Pattern

8 × 8 Dot Font

A10

A 9

A 8

A 7

0

1

0

1

0

1

A6 A5 A4 A3

A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8 × 16 Dot Font

A11

A10

A 9

A 8

0

1

0

1

0

A7 A6 A5 A4 A3 A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

19

HD61830/HD61830B

Example of Configuration

Graphic Mode or Character Mode (1) (Internal Character Generator)

HD61830

HD61830B

Liquid crystal

display module

MPU

MA0–MA15 at graphic mode,

MA0–MA11at character mode

MD0–MD7

RAM

Character Mode (2) (External Character Generator)

HD61830

HD61830B

Liquid crystal

display module

MPU

MA12–

MA15

MA0–MA11

RAM

RD0–RD7

ROM

–

MD0

MD7

20

HD61830/HD61830B

Parallel Operation (HD61830)

(Master)

Liquid crystal

display module (1) display module (2)

Liquid crystal

MPU

HD61830 (1)

CS CPO SYNC

Driving both of two

module by same

common signal

RAM

CR

SYNC

HD61830 (2)

CS

(Slave)

RAM

Parallel Operation (HD61830B)

(Master)

HD61830B (1)

CS

Liquid crystal

display module (1) display module (2)

Liquid crystal

MPU

SYNC

Driving both of two

module by same

common signal

RAM

SYNC

HD61830B (2)

CS

(Slave)

RAM

21

HD61830/HD61830B

HD61830 Application (Character Mode, External CG, Character Font 8 × 8)

HD6800

HD61830

WE

OE

RAM (1)

HM6116

OE

A0

RS

CS

WE

RAM (2)

HM6116

A0

to

A10

A0

to

A10

MA0

to

MA10

A12

A13

A14

A15

VMA

D0

to

D7

CS

MA11

MA12

to

MA14

DB0

to

DB7

E

MA15

ø2

MD0

to

MD7

R/W

A0–A2

A3–A10

RD0

to

RD7

D0

ROM

HN462716

OE

CE

to

D7

D1

FLM

MB

CL1

CL2

D2

D1

FLM

M

CL1

CL2

D2

+5 V

GND

–5 V

V0

SYNC

CPO

RES

Open

V_CC

LCD module

Open

MA

R

C

CR

C

R

+5 V

GND

–5 V

HD61830 Application (Graphic Mode)

D1

D2

Segment

driver

Segment

driver

DB0–DB7

HD6800

MPU

HD61830

controller

CS E

RS R/W

RES

CL1, CL2

MB, FLM

MA0–

MA15

LCD

MD0–MD7

WE

RAM

16 kbits

CMOS

Segment

driver

Segment

driver

V1– V6

Power supply for

liquid crystal

display drive

GND

VDD (5 V)

V_EE(–5 V)

22

HD61830/HD61830B

HD61830B Application (Character Mode, External CG, Character Font 8 × 8)

HD6303

HD61830B

OE

D0

to

OE

D0

to

WE

A0

WE

A0

to

WE

A0

to

RS

CS

RAM (1)

HM6116

RAM (2)

HM6116

MA0

to

MA10

A1

to

A15

D7

A10

CS

OE

Decoder

CE

MA11

MA12

to

D0

to

D7

DB0

to

DB7

MA15

E

MD0

to

MD7

R/W

A0–A3

A4–A11

RD0

to

RD7

D0

ROM

HN482732A

OE

CE

to

D7

D1

FLM

M

D1

FLM

MB

Open

V_CC

SYNC

CL1

CL2

D2

CL1

CL2

D2

+5 V

GND

–5 V

LCD module

RES

CR

MA

Open

External

clock

V0

+5 V

GND

–5 V

HD61830B Application (Graphic Mode)

D1

DB0–DB7

Segment

driver

Segment

driver

HD61830B

controller

D2

HD6303

MPU

CS E

RS R/W

RES

CL1, CL2

MB, FLM

MA0–

MA15

LCD

MD0–MD7

WE

OE

RAM

16 kbits

CMOS

CE

Segment

driver

Segment

driver

V1 – V6

Power supply for

liquid crystal

display drive

GND

VDD (5 V)

V_EE(–5 V)

23

HD61830/HD61830B

HD61830 Absolute Maximum Ratings

Item

Symbol

V_CC

Value

Unit

V

Notes

1, 2

Supply voltage

Terminal voltage

Operating temperature

Storage temperature

–0.3 to +0.7

–0.3 to V_CC+0.3

–20 to +75

–55 to +125

VT

V

1, 2

T_opr

°C

T_stg

Notes: 1. All voltages are referenced to GND = 0 V.

2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed.

We strongly recommend that you use the LSIs within electrical characteristic limits for normal

operation, because use beyond these conditions will cause malfunction and poor reliability.

24

HD61830/HD61830B

HD61830 Electrical Characteristics (V_CC= 5 V ±10%, GND = 0 V, T_a= –20 to

+75°C)

Item

Symbol Min

Typ Max

Unit Test Condition Notes

Input high voltage (TTL)

Input low voltage (TTL)

Input high voltage

VIH

2.2

—

V_CC

0.8

V_CC

0.3 V_CC

V_CC

0.4

V_CC

0.4

5

V

1

2

3

4

5

6

7

8

9

VIL

0

V

VIHR

VIHC

VILC

VOH

VOL

3.0

V

Input high voltage (CMOS)

Input low voltage (CMOS)

Output high voltage (TTL)

Output low voltage (TTL)

Output high voltage (CMOS)

Output low voltage (CMOS)

Input leakage current

Three-state leakage current

Power dissipation (1)

0.7 V_CC

V

0

V

2.4

0

V

–I_OH= 0.6 mA

I_OL= 1.6 mA

V

VOHC V_CC– 0.4 —

V

–I_OH= 0.6 mA

I_OL= 0.6 mA

VOLC

I_IN

0

—

10

V

–5

–10

—

µA

VIN = 0 – V_CC

VOUT = 0 – V_CC

I_TSL

10

P_W1

15

mW CR oscillation

_osc= 500 kHz

f

Power dissipation (2)

P_W2

f_osc

f_cp

—

20

30

mW External clock

_cp= 1 MHz

9

f

Internal clock operation

(Clock oscillation frequency)

400

100

500 600

kHz C_f= 15 pF ±5% 10

R_f= 39 kΩ ±2%

External clock operation

500 1100

kHz

11

(External clock operating frequency)

External clock duty

External clock rise time

External clock fall time

Pull-up current

Duty

t_rcp

47.5

—

50

—

10

52.5

0.05

20

%

11

12

µs

µA

t_fcp

—

I_PL

2

VIN = GND

Notes: The I/O terminals have the following configuration:

1. Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES.

2. Applied to input terminals and I/O common terminals, except terminals SYNC and CR.

3. Applied to terminal RES.

4. Applied to terminals SYNC and CR.

5. Applied to terminals DB0–DB7, WE, MA0–MA15, and MD0–MD7.

6. Applied to terminals SYNC, CP0, FLM, CL1, CL2, D1, D2, MA, and MB.

7. Applied to input terminals.

8. Applied to I/O common terminals. However, the current which flows into the output drive MOS is

excluded.

25

HD61830/HD61830B

9. The current which flows into the input and output circuits is excluded. When the input of CMOS is

in the intermediate level, current flows through the input circuit, resulting in the increase of power

supply current. To avoid this, input must be fixed at high or low.

The relationship between the operating frequency and the power dissipation is given below.

50

Max

40

30

20

10

0

Typ

250

500

750

1000

1250

f_OSC

1500

(kHz)

10. Applied to the operation of the internal oscillator when oscillation resistor R_fand oscillation

capacity C_fare used.

C_f= 15 pF ±5%

R_f= 39 kΩ ±2%

R

(when f_OSC

500 kHz typ)

=

R_f

C

C_f

CR

The relationship among oscillation frequency, R_fand C_fis given below.

T_a= 25°C, V_CC= 5 V

f_OSC(kHz)

800

600

400

200

C_f= 10 pF

C_f= 15 pF

0

40

60

80

100

120

140

160

180

R_f(kΩ)

26

HD61830/HD61830B

11. Applied to external clock operation.

T_h

T_I

Open

R

0.7 V_CC

0.5 V_CC

0.3 V_CC

C

Oscillator

CR

T_h

T_h+ T_I

Duty cycle =

× 100%

t_fcp

t_rcp

12. Applied to SYNC, DB0–DB7, and RD0–RD7.

27

HD61830/HD61830B

Input Terminal

Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)

V_CC

PMOS

NMOS

Applicable terminal: RD0–RD7 (with pull-up MOS)

V_CC

PMOS

(Pull-up MOS)

NMOS

28

HD61830/HD61830B

Output Terminal

Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, CPO, MA0–MA15

V_CC

PMOS

NMOS

I/O Common Terminal

Applicable terminal: DB0–DB7, SYNC, MD0–MD7 (MD0–MD7 have no pull-up MOS)

V_CC

PMOS

V_CC

PMOS

V_CC

(Pull-up MOS)

Enable

Data

NMOS

PMOS

NMOS

Input circuit

Output circuit

(Three state)

29

HD61830/HD61830B

Timing Characteristics

HD61830 MPU Interface (V_CC= 5 V ±10%, GND = 0 V, T_a= –20 to +75°C)

Item

Symbol

t_CYC

t_WEH

t_WEL

t_Er

Min

1.0

0.45

—

Typ

—

Max

—

Unit

µs

Enable cycle time

Enable pulse width

High level

Low level

—

µs

—

µs

Enable rise time

Enable fall time

Setup time

25

—

ns

t_Ef

—

ns

t_AS

140

225

—

ns

Data setup time

Data delay time

Data hold time

t_DSW

t_DDR

t_DHW

t_AH

—

ns

225

—

ns *

ns

10

Address hold time

Output data hold time

10

—

ns

t_DH

20

—

ns

Note: * The following load circuit is connected for specification:

t_CYC

t_WEH

t_WEL

2.2 V

0.8 V

E

t_Er

t_Ef

t_AH

t_AS

2.2 V

0.8 V

CS, R/W, RS

t_DSW

t_DHW

2.2 V

0.8 V

DB0–DB7

(MPU→HD61830)

t_DH

t_DDR

DB0–DB7

(MPU←HD61830)

2.4 V

0.4 V

V_CC

R_L

D1

Test point

R

D2

R_L= 2.4 kΩ

R = 11 kΩ

C = 130 pF (C includes jig capacitance)

C

D3

D4

H

Diodes D1to D4: 1S2074

30

HD61830/HD61830B

HD61830 External RAM and ROM Interface (V_CC= 5 V ±10%, GND = 0 V, T_a= –20 to +75°C)

Item

Symbol

t_DSY

Min

—

Typ

—

Max

200

—

Unit

ns

SYNC delay time

SYNC pulse width

CPO cycle time

CPO pulse width

Low level

t_WSY

900

450

—

t_CCPO

t_WCPOH

t_WCPOL

t_DMAR

t_DMAW

t_DMDW

t_SMD

—

High level

Low level

—

MA0 to MA15 refresh delay time

MA0 to MA15 write address delay time

MD0 to MD7 write data delay time

MD0 to MD7, RD0 to RD7 setup time

Memory address setup time

Memory data setup time

200

—

900

250

—

t_SMAW

t_SMDW

t_DWE

—

WE delay time

200

—

WE pulse width (low level)

t_WWE

450

1

2

V_CC

SYNC

CPO

t_DSY

t_CCPO

t_WSY

1

2

V_CC

t_WCPOL

t_WCPOH

2.4 V

0.4 V

MA0–MA15

MD0–MD7

t_DMAR

t_DMAW

t_SMAW

*

2.2 V

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

t_SMDW

t_SMD

t_DMDW

*

2.2 V

0.8 V

RD0–RD7

WE

t_SMD

*

2.4 V

0.4 V

t_DWE

t_WWE

Notes: 1. No load is applied to all the output terminals.

2. “*” indicates the delay time of RAM and ROM.

31

HD61830/HD61830B

HD61830 LCD Driver Interface (V_CC= 5 V ±10%, GND = 0 V, T_a= –20 to +75°C)

Item

Symbol

t_WCL1

t_DCL2

t_WCL2

t_WCH

t_WCL

t_DM

Min

450

—

Typ

—

Max

—

Unit

ns

Clock pulse width (high level)

Clock delay time

Clock cycle time

Clock pulse width

200

—

900

450

—

High level

Low level

—

MA, MB delay time

FLM delay time

Data delay time

Data setup time

300

200

—

t_DF

—

t_DD

—

t_SD

250

Note: No load is applied to all the output terminals (MA, MB, FLM, D1, and D2).

t_WCL1

1

2

V_CC

CL1

CL2

t_WCL2

t_DCL2

1

2

V_CC

t_WCH

t_WCL

1

2

MA, MB

V_CC

t_DM

t_DF

FLM

D1

1

2

V_CC

t_SD

t_DD

1

2

D2

V_CC

32

HD61830/HD61830B

HD61830B Absolute Maximum Ratings

Item

Symbol

V_CC

Value

Unit

V

Notes

1, 2

Supply voltage

Terminal voltage

Operating temperature

Storage temperature

–0.3 to +0.7

–0.3 to V_CC+0.3

–20 to +75

–55 to +125

VT

V

1, 2

T_opr

°C

T_stg

Notes: 1. All voltage is referred to GND = 0 V.

2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed.

We strongly recommend that you use the LSIs within electrical characteristic limits for normal

operation, because use beyond these conditions will cause malfunction and poor reliability.

33

HD61830/HD61830B

HD61830B Electrical Characteristics (V_CC= 5V ±10%, GND = 0V, T_a= –20 to

+75°C)

Item

Symbol Min

Typ Max

Unit Test Condition Notes

Input high voltage (TTL)

Input low voltage (TTL)

Input high voltage

VIH

2.2

—

10

—

V_CC

0.8

V_CC

0.3 V_CC

V_CC

0.4

V_CC

0.4

5

V

1

2

3

4

5

6

7

8

9

10

VIL

0

V

VIHR

VIHC

VILC

VOH

VOL

VOHC

VOLC

I_IN

3.0

V

Input high voltage (CMOS)

Input low voltage (CMOS)

Output high voltage (TTL)

Output low voltage (TTL)

Output high voltage (CMOS)

Output low voltage (CMOS)

Input leakage current

Three-state leakage current

Pull-up current

0.7 V_CC

V

0

V

2.4

V

–I_OH= 0.6 mA

I_OL= 1.6 mA

–I_OH= 0.6 mA

I_OI= 0.6 mA

0

V

V_CC– 0.4

V

0

V

–5

–10

2

µA

VIN = 0 – V_CC

VOUT = 0 – V_CC

Vin = GND

I_TSL

10

I_PL

20

Power dissipation

P_W

—

50

mW External clock

_cp= 2.4 MHz

f

Notes: 1. Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES.

2. Applied to input terminals and I/O common terminals, except terminals SYNC and CR.

3. Applied to terminal RES.

4. Applied to terminals SYNC and CR.

5. Applied to terminals DB0–DB7, WE, MA0–MA15, OE, CE, and MD0–MD7.

6. Applied to terminals SYNC, FLM, CL1, CL2, D1, D2, MA, and MB.

7. Applied to input terminals.

8. Applied to I/O common terminals. However, the current which flows into the output drive MOS is

excluded.

9. Applied to SYNC, DB0–DB7, and RD0–RD7.

10. The current which flows into the input and output circuits is excluded. When the input of CMOS is

in the intermediate level, current flows through the input circuit, resulting in the increase of power

supply current. To avoid this, input must be fixed at high or low.

34

HD61830/HD61830B

Input Terminal

Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)

V_CC

PMOS

NMOS

Applicable terminal: RD0–RD7 (with pull-up MOS)

V_CC

PMOS

NMOS

(Pull-up MOS)

35

HD61830/HD61830B

Output Terminal

Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, OE, CE, MA0–MA15

V_CC

PMOS

NMOS

I/O Common Terminal

Applicable terminal: DB0–DB7, SYNC, MD0–MD7 (MD0–MD7 have no pull-up MOS)

V_CC

PMOS

NMOS

V_CC

(Pull-up MOS)

Enable

Data

PMOS

NMOS

Input circuit

Output circuit

(Three state)

36

HD61830/HD61830B

Timing Characteristics

HD61830B Clock Operation (V_CC= 5 V ±10%, GND = 0V, T_a= –20 to +75°C)

Item

Symbol

Min

100

47.5

—

Typ

—

50

—

Max

2400

52.5

25.0

—

Unit

kHz

%

Notes

External clock operating frequency f_cp

1

External clock duty

Duty

1

External clock rise time

External clock fall time

SYNC output hold time

SYNC output delay time

SYNC input hold time

SYNC input set-up time

t_rcp

ns

1

t_fcp

—

ns

1

t_HSYO

t_DSY

t_HSYI

t_SSY

30

ns

2, 3

2

—

210

—

ns

10

ns

—

180

ns

2

Notes: 1. Applied to external clock input terminal.

T_h

T_l

0.7 V_CC

0.5 V_CC

0.3 V_CC

Oscillator

CR

T_h

T_h+ T_l

Duty cycle =

× 100%

t_fcp

t_rcp

2. Applied to SYNC terminal.

0.7 V_CC

CR

0.3 V_CC

t_DSY

t_HSYO

t_DSY

t_HSYO

0.7 V_CC

SYNC

(Output:

at master

mode)

0.3 V_CC

t_SSY

t_HSYI

t_SSY

0.7 V_CC

0.3 V_CC

SYNC

(Input:

at slave

mode)

3. Testing load circuit.

Test point

C_L= 30 pF

(C_Lincludes jig capacitance)

C_L

37

HD61830/HD61830B

HD61830B MPU Interface (V_CC= 5V ±10%, GND = 0V, T_a= –20 to +75°C)

Item

Symbol

t_CYC

t_WEH

t_WEL

t_Er

Min

1.0

0.45

—

Typ

—

Max

—

Unit

µs

Enable cycle time

Enable pulse width

High level

Low level

—

µs

—

µs

Enable rise time

Enable fall time

Setup time

25

—

ns

t_Ef

—

ns

t_AS

140

225

—

ns

Data setup time

Data delay time

Data hold time

t_DSW

t_DDR

t_DHW

t_AH

—

ns

225

—

ns *

ns

10

Address hold time

Output data hold time

10

—

ns

t_DH

20

—

ns

Note:

*

The following load circuit is connected for specification:

t_CYC

t_WEH

t_WEL

2.2V

0.8V

E

t_Er

t_Ef

t_AH

t_AS

2.2V

0.8V

CS, R/W, RS

t_DSW

t_DHW

2.2V

0.8V

DB0–DB7

(MPU→HD61830B)

t_DH

t_DDR

DB0–DB7

(MPU←HD61830B)

2.4V

0.4V

V_CC

R_L

D1

Test point

D2

D3

R_L= 2.4 kΩ

R = 11 kΩ

R

C

C = 130 pF (C includes jig capacitance)

Diodes D1to D4: 1S2074 ^H

D4

38

HD61830/HD61830B

HD61830B External RAM and ROM Interface (V_CC= 5V ±10%, GND = 0V, T_a= –20 to +75°C)

Item

Symbol

t_DMA

Min

—

Typ

—

Max

300

—

Unit

ns

Notes

1, 2, 3

1, 3

2

MA0–MA15 delay time

MA0–MA15 hold time

CE delay time

t_HMA

40

—

t_DCE

300

—

CE hold time

t_HCE

40

—

OE delay time

t_DOE

300

—

OE hold time

t_HOE

40

—

MD output delay time

MD output hold time

WE delay time

t_DMD

150

—

t_HMDW

t_DWE

10

—

150

—

WE clock pulse width

t_WWE

150

10

50

40

50

40

MD output high impedance time (1) t_ZMDF

MD output high impedance time (2) t_ZMDR

—

RD data set-up time

RD data hold time

t_SRD

t_HRD

t_SMD

t_HMD

—

2

MD data set-up time

MD data hold time

—

2

—

2

Notes: 1. RAM write timing

T₁

T₂

T₃

T₁

0.7 V_CC

CR

CE

0.3 V_CC

t_HCE

0.6V

t_DMA

t_HMA

t_DMA

t_HMA

2.4V

0.6V

MA0–MA15

t_DOE

t_HOE

t_DOE

t_HOE

2.4V

0.6V

OE

t_DWEt_DWE

t_ZMDR

2.4V

0.6V

WE

t_ZMDF

t_DMD

2.4V

t_WWE

Valid

data

(High impedance)

MD0–MD7

(output)

2.4V

0.6V

t_HMDW

T1: Memory data refresh timing for upper screen

T2: Memory data refresh timing for lower screen

T3: Memory read/write timing

39

HD61830/HD61830B

2. ROM/RAM read timing

T₁

T₂

T₃

T₁

CR

(*1)

a

t_DCE

t_HCE

t_DCE

t_HCE

t_DCE

t_HCE

a

b

(*1)

2.4V

0.6V

(*2)

CE

(*2)

0.6V

OE

t_DMA

t_HMA

t_DMA

t_HMA

t_DMA

t_HMA

2.4V

0.6V

Address for

the lower screen

(*3)

MA0–MA15

Address for upper screen

t_SMD

t_HMD

2.2V

0.8V

Data for

the lower screen

Data for the upper screen

t_SRD

(*4)

MD0–MD7

(input)

t_SRD

t_HRD

2.2V

0.8V

Data for the

lower screen

RD0–RD7

Invalid data

Data for the upper screen

*1

This figures shows the timing for H_p= 8.

For H_p= 7, time shown by “b” becomes zero. For H_p= 6, time shown by “a” and “b”

become zero.

Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of H_p= 8,

H_p= 7, or H_p= 6 respectively.

*2

*3

*4

The waveform for instructions with memory read is shown with a dash line. In other cases,

the waveform shown with a solid line is generated.

When an instruction with RAM read/write is executed, the value of cursor address is

output. In other cases, invalid data is output.

When an instruction with RAM read is executed, HD61830B latches the data at this timing.

In other cases, this data is invalid.

3. Test load circuit

V_CC

R_L

D1

Test point

D2

D3

R_L= 2.4 kΩ

R = 11 kΩ

R

C

C = 50 pF (C includes jig capacitance)

D4

H

Diodes D1to D4: 1S2074

40

HD61830/HD61830B

HD61830B LCD Driver Interface (V_CC= 5V ±10%, GND = 0V, Ta = –20 to +75°C)

Item

Symbol

Min

416

150

—

Typ

—

Max

—

Unit

ns

Notes

1, 3

2, 3

Clock cycle time

t_WCL2

Clock pulse width(high level) t_WCH

Clock pulse width(low level) t_WCL

—

Data delay time

t_DD

50

—

Data hold time

t_DH

100

–200

400

1000

400

1000

Clock phase difference (1)

Clock phase difference (2)

Clock phase difference (3)

MA, MB delay time

FLM set-up time

t_CL1

t_CL2

t_CL3

t_DM

t_SF

—

200

—

FLM hold time

t_HF

—

MA set-up time

t_SMA

t_HMA

—

MA hold time

—

41

HD61830/HD61830B

Notes: 1.

t_WCL2

t_WCH

t_WCL

0.7 V_CC

0.3 V_CC

CL2

t_CL1

t_CL2

t_CL3

0.7 V_CC

0.3 V_CC

CL1

t_WCH

t_DH

t_DD

0.7 V_CC

D1, D2

0.3 V_CC

t_DM

0.7 V_CC

0.3 V_CC

MA, MB

2.

0.7 V_CC

0.3 V_CC

CL1

t_SF

t_HF

0.7 V_CC

0.3 V_CC

FLM

MA

t_SMA

t_HMA

0.7 V_CC

0.3 V_CC

3. Test load circuit

Test point

C_L= 100 pF

(C_Lincludes jig capacitance)

C_L

42

HD61830/HD61830B

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower, World Finance Centre,

Harbour City, Canton Road, Tsim Sha Tsui,

Kowloon, Hong Kong

Tel: <852> (2) 735 9218

Fax: <852> (2) 730 0281

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Electronic components Group

Dornacher Straße 3

D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

179 East Tasman Drive,

San Jose,CA 95134

Tel: <1> (408) 433-1990

Fax: <1>(408) 433-0223

Fax: 535-1533

Hitachi Asia Ltd.

Taipei Branch Office

3F, Hung Kuo Building. No.167,

Tun-Hwa North Road, Taipei (105)

Tel: <886> (2) 2718-3666

Fax: <886> (2) 2718-8180

Telex: 40815 HITEC HX

Hitachi Europe Ltd.

Electronic Components Group.

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Fax: <44> (1628) 778322

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