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  • 北京元坤伟业科技有限公司

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  • HD74LV163AFPEL
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产品型号HD74LV163AFPEL的Datasheet PDF文件预览

HD74LV163A  
Synchronous 4-bit Binary Counter (Synchronous Clear)  
REJ03D0320–0500Z  
(Previous ADE-205-265C (Z))  
Rev.5.00  
Jun. 04, 2004  
Description  
The HD74LV163A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to transition  
(positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four  
flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A,  
B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive  
edge of clock, the count operation will be unaffected.  
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the  
low-power consumption extends the battery life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)  
Ordering Information  
Part Name  
Package Type  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
HD74LV163AFPEL  
HD74LV163ARPEL  
HD74LV163ATELL  
SOP–16 pin(JEITA)  
SOP–16 pin(JEDEC)  
TSSOP–16 pin  
FP–16DAV  
FP–16DNV  
TTP–16DAV  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
ELL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Rev.5.00 Jun. 04, 2004 page 1 of 14  
HD74LV163A  
Function Table  
Inputs  
Outputs  
QA  
CLR  
L
LOAD  
X
ENP  
X
ENT  
X
CLK  
QB  
L
QC  
L
QD  
L
L
H
L
X
X
A
B
C
D
H
H
H
H
X
X
L
No change  
No change  
Count up  
No change  
H
L
X
H
H
H
X
X
X
Note: H: High level  
L: Low level  
X: Immaterial  
: Low to high transition  
: High to low transition  
A, B, C, D: Data input  
Carry = ENT • QA • QB • QC • QD  
Pin Arrangement  
1
2
3
4
5
6
7
8
16 VCC  
CLR  
CK  
A
CARRY  
15  
14  
13  
12  
11  
10  
9
OUTPUT  
QA  
QB  
B
QC  
C
QD  
D
ENP  
GND  
ENT  
LOAD  
(Top view)  
Rev.5.00 Jun. 04, 2004 page 2 of 14  
HD74LV163A  
Absolute Maximum Ratings  
Item  
Symbol  
Ratings  
–0.5 to 7.0  
–0.5 to 7.0  
–0.5 to VCC + 0.5  
–0.5 to 7.0  
–20  
Unit  
V
Conditions  
Supply voltage range  
Input voltage range*1  
Output voltage range*1, 2  
VCC  
VI  
V
VO  
V
Output: H or L  
VCC: OFF  
Input clamp current  
IIK  
IOK  
IO  
mA  
mA  
mA  
mA  
VI < 0  
Output clamp current  
±50  
VO < 0 or VO > VCC  
VO = 0 to VCC  
Continuous output current  
Continuous current through  
±25  
ICC or  
IGND  
±50  
VCC or GND  
Maximum power dissipation at PT  
Ta = 25°C (in still air)*3  
785  
mW  
SOP  
500  
TSSOP  
Storage temperature  
Tstg  
–65 to 150  
°C  
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of  
which may be realized at the same time.  
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are  
observed.  
2. This value is limited to 5.5 V maximum.  
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.  
Recommended Operating Conditions  
Item  
Symbol  
VCC  
VI  
Min  
2.0  
0
Max  
5.5  
5.5  
VCC  
–50  
–2  
Unit  
V
Conditions  
Supply voltage range  
Input voltage range  
Output voltage range  
Output current  
V
VO  
0
V
H or L  
IOH  
0
µA  
mA  
VCC = 2.0 V  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
VCC = 2.0 V  
–6  
–12  
50  
IOL  
µA  
2
mA  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
6
12  
Input transition rise or fall rate  
Operating free-air temperature  
t /v  
200  
100  
20  
ns/V  
°C  
0
0
VCC = 4.5 to 5.5 V  
Ta  
–40  
85  
Note: Unused or floating inputs must be held high or low.  
Rev.5.00 Jun. 04, 2004 page 3 of 14  
HD74LV163A  
Logic Diagram  
CLK  
Output  
QA  
CLR  
D
Q
CK  
Q
LOAD  
P
T
Enable  
A
Output  
QB  
D
Q
CK  
Q
B
Output  
QC  
D
Q
Data  
Inputs  
CK  
Q
C
D
Output  
QD  
D
Q
CK  
Q
Carry  
Output  
Rev.5.00 Jun. 04, 2004 page 4 of 14  
HD74LV163A  
Timing Diagram  
CLR  
LOAD  
A
B
Data  
Inputs  
C
D
CLK  
ENP  
ENT  
QA  
QB  
QC  
QD  
Out  
puts  
Carry  
12  
13  
14  
15  
0
1
2
Count  
Inhibit  
Clear Preset  
Rev.5.00 Jun. 04, 2004 page 5 of 14  
HD74LV163A  
DC Electrical Characteristics  
Ta = –40 to 85°C  
Unit Test Conditions  
V
Item  
Symbol  
V
CC (V)*  
Min  
Typ Max  
Input voltage  
VIH  
2.0  
1.5  
0.5  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
2.0  
V
V
V
CC × 0.7  
CC × 0.7  
CC × 0.7  
VIL  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
V
V
V
CC × 0.3  
CC × 0.3  
CC × 0.3  
Output voltage  
VOH  
Min to Max VCC – 0.1  
V
IOL = –50 µA  
IOL = –2 mA  
2.3  
2.0  
2.48  
3.8  
3.0  
IOL = –6 mA  
4.5  
IOL = –12 mA  
IOL = 50 µA  
VOL  
Min to Max  
2.3  
0.1  
0.4  
0.44  
0.55  
±1  
IOL = 2 mA  
3.0  
IOL = 6 mA  
4.5  
IOL = 12 mA  
Input current  
IIN  
0 to 5.5  
5.5  
µA  
µA  
VIN = 5.5 V or GND  
VIN = VCC or GND, IO = 0  
Quiescent supply  
current  
ICC  
20  
Output leakage  
current  
IOFF  
0
5
µA  
VI or VO = 0 V to 5.5 V  
Input capacitance  
CIN  
3.3  
1.7  
pF  
VI = VCC or GND  
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.  
Rev.5.00 Jun. 04, 2004 page 6 of 14  
HD74LV163A  
Switching Characteristics  
VCC = 2.5 ± 0.2 V  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
TO  
Item  
Symbol  
Unit Conditions (Input)  
(Output)  
Min  
50  
30  
Typ  
Max Min  
Max  
Maximum clock  
frequency  
fmax  
90  
60  
40  
25  
MHz CL = 15 pF  
CL = 50 pF  
Propagation  
delay time  
tPLH/tPHL  
11.1 16.2 1.0  
14.3 19.2 1.0  
11.5 17.0 1.0  
14.7 20.0 1.0  
13.8 20.6 1.0  
17.0 23.6 1.0  
10.3 15.7 1.0  
14.0 18.7 1.0  
19.5  
22.5  
20.5  
23.5  
24.5  
27.5  
19.0  
22.0  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CLK  
CLK  
CLK  
ENT  
Q
tPLH/tPHL  
Carry  
Carry  
Carry  
Count mode  
tPLH/tPHL  
Load mode  
tPLH/tPHL  
Setup time  
tsu  
7.5  
10.0  
9.5  
8.5  
ns  
Data before CLK ↑  
LOAD before CLK ↑  
11.5  
11.0  
ENT, ENP before  
CLK ↑  
6.0  
1.5  
1.5  
7.0  
6.0  
1.5  
1.5  
7.0  
CLR before CLK ↑  
Hold time  
th  
ns  
ns  
CLR after CLK ↑  
CLK H or L  
Pulse width  
tw  
Rev.5.00 Jun. 04, 2004 page 7 of 14  
HD74LV163A  
Switching Characteristics (cont)  
VCC = 3.3 ± 0.3 V  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
TO  
Item  
Symbol  
Unit Conditions (Input)  
(Output)  
Min  
80  
55  
Typ  
Max Min  
Max  
Maximum clock  
frequency  
tmax  
130  
85  
70  
50  
MHz CL = 15 pF  
CL = 50 pF  
Propagation  
delay time  
tPLH/tPHL  
8.3  
12.8 1.0  
15.0  
18.5  
16.0  
19.5  
20.0  
23.5  
14.5  
18.0  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CLK  
CLK  
CLK  
ENT  
Q
10.8 16.3 1.0  
8.7 13.6 1.0  
tPLH/tPHL  
Carry  
Carry  
Carry  
Count mode  
tPLH/tPHL  
11.2 17.1 1.0  
11.0 17.2 1.0  
13.5 20.7 1.0  
Load mode  
tPLH/tPHL  
7.5  
12.3 1.0  
10.5 15.8 1.0  
Setup time  
tsu  
5.5  
8.0  
7.5  
6.5  
9.5  
9.0  
ns  
Data before CLK ↑  
LOAD before CLK ↑  
ENT, ENP before  
CLK ↑  
4.0  
1.0  
1.0  
5.0  
4.0  
1.0  
1.0  
5.0  
CLR before CLK ↑  
Hold time  
th  
ns  
ns  
CLR after CLK ↑  
CLK H or L  
Pulse width  
tw  
VCC = 5.0 ± 0.5 V  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
TO  
Item  
Symbol  
Unit Conditions (Input)  
(Output)  
Min  
135  
95  
Typ  
Max Min  
Max  
Maximum clock  
frequency  
tmax  
185  
125  
4.9  
8.7  
4.9  
6.4  
6.2  
7.7  
4.9  
6.4  
115  
85  
MHz CL = 15 pF  
CL = 50 pF  
Propagation  
delay time  
tPLH/tPHL  
8.1  
1.0  
9.5  
11.5  
9.5  
11.5  
12.0  
14.0  
9.5  
11.5  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CLK  
CLK  
CLK  
ENT  
Q
10.1 1.0  
8.1 1.0  
tPLH/tPHL  
Carry  
Carry  
Carry  
Count mode  
tPLH/tPHL  
10.1 1.0  
10.3 1.0  
12.3 1.0  
Load mode  
tPLH/tPHL  
8.1  
1.0  
10.1 1.0  
Setup time  
tsu  
4.5  
5.0  
5.0  
4.5  
6.0  
6.0  
ns  
Data before CLK ↑  
LOAD before CLK ↑  
ENT, ENP before  
CLK ↑  
3.5  
1.0  
1.5  
5.0  
3.5  
1.0  
1.5  
5.0  
CLR before CLK ↑  
Hold time  
th  
ns  
ns  
CLR after CLK ↑  
CLK H or L  
Pulse width  
tw  
Rev.5.00 Jun. 04, 2004 page 8 of 14  
HD74LV163A  
Operating Characteristics  
CL = 50 pF  
Ta = 25°C  
VCC (V) Min  
Item  
Symbol  
Typ  
Max  
Unit  
Test Conditions  
f = 10 MHz  
Power dissipation capacitance CPD  
3.3  
5.0  
17.3  
20.6  
pF  
Noise Characteristics  
CL = 50 pF  
Test Conditions  
Ta = 25°C  
Min  
Item  
Symbol  
VCC (V)  
Unit  
Typ  
Max  
Quiet output, maximum  
dynamic VOL  
VOL (P)  
VOL (V)  
VOH (V)  
VIH (D)  
VIL (D)  
3.3  
0.3  
0.8  
V
Quiet output, minimum  
dynamic VOL  
3.3  
3.3  
3.3  
3.3  
–0.3  
3.0  
–0.8  
V
V
V
V
Quiet output, minimum  
dynamic VOH  
High-level dynamic input  
voltage  
2.31  
Low-level dynamic input  
voltage  
0.99  
Test Circuit  
Measurement point  
*
C L  
Note: 1. CL includes the probe and jig capacitance.  
Rev.5.00 Jun. 04, 2004 page 9 of 14  
HD74LV163A  
Waveforms  
Waveform  
1  
Count mode  
t
t
WL  
WH  
V
CC  
50%  
50%  
CLK  
GND  
V
V
OH  
OL  
50%  
50%  
Q, CARRY  
t
t
pHL  
pLH  
Waveform  
2  
Preset mode  
V
CC  
50%  
50%  
LOAD  
GND  
t
t
t
t
h
su  
h
su  
50%  
A to D  
CLK  
t
t
h
su  
V
CC  
50%  
50%  
GND  
t
t
pLH, pHL  
V
OH  
OL  
50%  
Q, CARRY  
V
Rev.5.00 Jun. 04, 2004 page 10 of 14  
HD74LV163A  
Waveform  
3  
Count enable mode  
V
CC  
ENP  
50%  
50%  
ENT  
CLK  
GND  
t
t
t
t
h
su  
h
su  
V
CC  
50%  
50%  
GND  
V
V
OH  
OL  
Q
Waveform  
4  
Clear mode  
V
CLR  
CC  
50%  
50%  
GND  
t
t
h
su  
V
CC  
CLK  
50%  
GND  
V
V
OH  
OL  
Q, CARRY  
Rev.5.00 Jun. 04, 2004 page 11 of 14  
HD74LV163A  
Waveform  
5  
Cascade mode  
(set to maximum count number)  
V
CC  
ENT  
50%  
50%  
GND  
V
V
OH  
OL  
CARRY  
50%  
50%  
t
t
pHL  
pLH  
Note: 1. Input waveform: PRR1 MHz, duty cycle 50%, tr 3 ns, tf 3 ns  
Application  
Cascade circuitry  
H: COUNT  
L : DISABLE  
INPUTS  
INPUTS  
INPUTS  
LD  
A
B
C
D
LD  
A
B
C
D
LD  
A
B
C
D
ENP  
ENT  
CK  
ENP  
ENT  
CK  
ENP  
ENT  
CK  
H: COUNT  
L : DISABLE  
CARRY  
CARRY  
CARRY  
to next stages  
CLR QA QB QC QD  
CLR QA QB QC QD  
CLR QA QB QC QD  
OUTPUT  
OUTPUT  
OUTPUT  
CLR  
CLK  
Rev.5.00 Jun. 04, 2004 page 12 of 14  
HD74LV163A  
Package Dimensions  
As of January, 2003  
Unit: mm  
10.06  
10.5 Max  
9
16  
1
8
+ 0.20  
7.80  
– 0.30  
0.80 Max  
1.15  
0˚ – 8˚  
1.27  
0.70 ± 0.20  
*0.40 ± 0.06  
0.15  
M
0.12  
Package Code  
JEDEC  
FP-16DAV  
JEITA  
Mass (reference value)  
Conforms  
0.24 g  
*Ni/Pd/Au plating  
As of January, 2003  
Unit: mm  
9.9  
10.3 Max  
9
8
16  
1
1.27  
+ 0.10  
6.10  
– 0.30  
1.08  
0.635 Max  
0˚ – 8˚  
+ 0.67  
0.60  
– 0.20  
*0.40 ± 0.06  
0.15  
0.25  
M
Package Code  
JEDEC  
JEITA  
FP-16DNV  
Conforms  
Conforms  
0.15 g  
*Ni/Pd/Au plating  
Mass (reference value)  
Rev.5.00 Jun. 04, 2004 page 13 of 14  
HD74LV163A  
As of January, 2003  
Unit: mm  
5.00  
5.30 Max  
16  
9
1
8
0.65  
0.13 M  
0.65 Max  
1.0  
*0.20 ± 0.05  
6.40 ± 0.20  
0˚ – 8˚  
0.50 ± 0.10  
0.10  
Package Code  
JEDEC  
TTP-16DAV  
JEITA  
*Ni/Pd/Au plating  
Mass (reference value)  
0.05 g  
Rev.5.00 Jun. 04, 2004 page 14 of 14  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and  
cannot be imported into a country other than the approved destination.  
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.  
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http://www.renesas.com  
Renesas Technology America, Inc.  
450 Holger Way, San Jose, CA 95134-1368, U.S.A  
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501  
Renesas Technology Europe Limited.  
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom  
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900  
Renesas Technology Europe GmbH  
Dornacher Str. 3, D-85622 Feldkirchen, Germany  
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11  
Renesas Technology Hong Kong Ltd.  
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong  
Tel: <852> 2265-6688, Fax: <852> 2375-6836  
Renesas Technology Taiwan Co., Ltd.  
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan  
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999  
Renesas Technology (Shanghai) Co., Ltd.  
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China  
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952  
Renesas Technology Singapore Pte. Ltd.  
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632  
Tel: <65> 6213-0200, Fax: <65> 6278-8001  
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .1.0  
配单直通车
HD74LV163AFPEL产品参数
型号:HD74LV163AFPEL
生命周期:Transferred
IHS 制造商:HITACHI LTD
零件包装代码:SOIC
包装说明:SOP,
针数:16
Reach Compliance Code:unknown
HTS代码:8542.39.00.01
风险等级:5.28
计数方向:UP
系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G16
长度:10.06 mm
负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS
位数:4
功能数量:1
端子数量:16
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
传播延迟(tpd):22.5 ns
认证状态:Not Qualified
座面最大高度:2.2 mm
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
触发器类型:POSITIVE EDGE
宽度:5.5 mm
最小 fmax:115 MHz
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