欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
更多
  • HEF4029BP图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • HEF4029BP
  • 数量3491 
  • 厂家PHILIPS/飞利浦 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • HEF4029BP图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • HEF4029BP
  • 数量13600 
  • 厂家SIG 
  • 封装原厂原封装 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • HEF4029BP图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • HEF4029BP
  • 数量24154 
  • 厂家PHILIPS 
  • 封装DIP16 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • HEF4029BP图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • HEF4029BP
  • 数量18000 
  • 厂家PHILIPS/飞利浦 
  • 封装DIP16 
  • 批号23+ 
  • 全新原装现货,假一赔十
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • HEF4029BP 其他IC图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • HEF4029BP 其他IC
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • HEF4029BP图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • HEF4029BP
  • 数量8800 
  • 厂家PHILIPS/飞利浦 
  • 封装DIP16 
  • 批号20+ 
  • 全新原装原厂实力挺实单欢迎来撩
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • HEF4029BP图
  • 深圳市澳亿芯电子

     该会员已使用本站13年以上
  • HEF4029BP
  • 数量
  • 厂家PHI 
  • 封装DIP-16 
  • 批号 
  • QQ:634389814QQ:634389814 复制
  • 0755-83227826 QQ:634389814
  • HEF4029BP图
  • 深圳市一线半导体有限公司

     该会员已使用本站16年以上
  • HEF4029BP
  • 数量24500 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921

产品型号HEF4029BP的Datasheet PDF文件预览

INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4029B  
MSI  
Synchronous up/down counter,  
binary/decade counter  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
Information on P0 to P3 is asynchronously loaded into the  
counter while PL is HIGH, independent of CP.  
DESCRIPTION  
The HEF4029B is a synchronous edge-triggered up/down  
4-bit binary/BCD decade counter with a clock input (CP),  
an active LOW count enable input (CE), an up/down  
control input (UP/DN), a binary/decade control input  
(BIN/DEC), an overriding asynchronous active HIGH  
parallel load input (PL), four parallel data inputs (P0 to P3),  
four parallel buffered outputs (O0 to O3) and an active  
LOW terminal count output (TC).  
The counter is advanced one count on the LOW to HIGH  
transition of CP when CE and PL are LOW. The TC signal  
is normally HIGH and goes LOW when the counter  
reaches its maximum count in the UP mode, or the  
minimum count in the DOWN mode provided CE is LOW.  
Fig.1 Functional diagram.  
Fig.2 Pinning diagram.  
PINNING  
HEF4029BP(N):  
HEF4029BD(F):  
HEF4029BT(D):  
16-lead DIL; plastic  
(SOT38-1)  
PL  
parallel load input  
P0 to P3  
BIN/DEC  
UP/DN  
CE  
parallel data inputs  
16-lead DIL; ceramic (cerdip)  
(SOT74)  
binary/decade control input  
up/down control input  
16-lead SO; plastic  
(SOT109-1)  
count enable input (active LOW)  
clock input (LOW to HIGH, edge triggered)  
buffered parallel outputs  
CP  
( ): Package Designator North America  
O0 to O3  
TC  
terminal count output (active LOW)  
FAMILY DATA, IDD LIMITS category MSI  
See Family Specifications  
January 1995  
2
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
Fig.3 Logic diagram (continued in Fig.4).  
January 1995  
3
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
Fig.4 Logic diagram (continued from Fig.3).  
January 1995  
4
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
FUNCTION TABLE  
PL  
BIN/DEC  
UP/DN  
CE  
CP  
MODE  
H
L
L
X
X
L
X
X
L
X
H
L
X
X
parallel load (Pn On)  
no change  
count-down, decade  
L
L
L
L
H
H
H
L
L
L
L
count-up, decade  
count-down, binary  
count-up, binary  
H
Notes  
1. H = HIGH state (the more positive voltage)  
L = LOW state (the less positive voltage)  
X = state is immaterial  
= positive-going clock pulse edge  
Fig.5 State diagram; BIN/DEC = LOW.  
January 1995  
5
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
Fig.6 State diagram; BIN/DEC = HIGH.  
Logic equation for terminal count:  
TC = CE (BIN DEC UP DN O0 O1 O2 O3 + BIN DEC UP DN O0 O1 O2 O3 +  
BIN DEC UP DN O0 O3 + BIN DEC UP DN O0 O1 O2 O3 )  
January 1995  
6
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; input transition times 20 ns  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
2
2
Dynamic power  
5
1000 fi + ∑(foCL) × VDD  
4500 fi + ∑(foCL) × VDD  
where  
dissipation per  
package (P)  
10  
15  
fi = input freq. (MHz)  
11 500 fi + ∑(foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
VDD = supply voltage (V)  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL MIN.  
TYP.  
MAX.  
Propagation delays  
CP On  
5
145  
55  
290  
110  
75  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
118 ns + (0,55 ns/pF) CL  
44 ns + (0,23 ns/pF) CL  
32 ns + (0,16 ns/pF) CL  
133 ns + (0,55 ns/pF) CL  
49 ns + (0,23 ns/pF) CL  
32 ns + (0,16 ns/pF) CL  
253 ns + (0,55 ns/pF) CL  
94 ns + (0,23 ns/pF) CL  
62 ns + (0,16 ns/pF) CL  
168 ns + (0,55 ns/pF) CL  
64 ns + (0,23 ns/pF) CL  
47 ns + (0,16 ns/pF) CL  
93 ns + (0,55 ns/pF) CL  
39 ns + (0,23 ns/pF) CL  
27 ns + (0,16 ns/pF) CL  
143 ns + (0,55 ns/pF) CL  
54 ns + (0,23 ns/pF) CL  
37 ns + (0,16 ns/pF) CL  
153 ns + (0,55 ns/pF) CL  
59 ns + (0,23 ns/pF) CL  
42 ns + (0,16 ns/pF) CL  
143 ns + (0,55 ns/pF) CL  
54 ns + (0,23 ns/pF) CL  
42 ns + (0,16 ns/pF) CL  
HIGH to LOW  
10  
15  
5
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
40  
160  
60  
315  
120  
80  
LOW to HIGH  
10  
15  
5
40  
CP TC  
280  
105  
70  
560  
205  
140  
385  
150  
105  
240  
100  
70  
HIGH to LOW  
10  
15  
5
195  
75  
LOW to HIGH  
10  
15  
5
55  
PL On  
120  
50  
HIGH to LOW  
10  
15  
5
35  
170  
65  
335  
130  
90  
LOW to HIGH  
10  
15  
5
45  
CE TC  
180  
70  
360  
140  
100  
335  
135  
100  
HIGH to LOW  
10  
15  
5
50  
170  
65  
LOW to HIGH  
10  
15  
50  
January 1995  
7
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL MIN.  
TYP.  
60  
MAX.  
Output transition times  
HIGH to LOW  
5
120  
60  
ns  
ns  
ns  
ns  
ns  
ns  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10  
15  
5
tTHL  
30  
20  
60  
30  
20  
40  
120  
60  
LOW to HIGH  
10  
15  
tTLH  
40  
January 1995  
8
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
SYMBOL  
MIN  
TYP  
MAX  
Minimum clock  
pulse width; LOW  
5
110  
35  
25  
160  
55  
35  
150  
50  
35  
270  
90  
60  
300  
105  
75  
240  
90  
70  
70  
20  
10  
45  
15  
10  
15  
0
55  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MHz  
MHz  
MHz  
10  
15  
5
tWCPL  
15  
Minimum PL  
pulse width; HIGH  
80  
10  
15  
5
tWPLH  
tRPL  
tsu  
25  
15  
Recovery time  
for PL  
75  
10  
15  
5
25  
20  
Set-up times  
135  
45  
BIN/DEC CP  
10  
15  
5
30  
150  
55  
UP/DN CP  
CE CP  
Pn PL  
10  
15  
5
tsu  
35  
120  
50  
10  
15  
5
tsu  
40  
see also waveforms  
Figs 7 and 8  
35  
10  
15  
5
tsu  
10  
5
Hold times  
90  
30  
20  
135  
50  
35  
30  
10  
10  
20  
10  
5  
BIN/DEC CP  
UP/DN CP  
CE CP  
10  
15  
5
thold  
thold  
thold  
thold  
fmax  
10  
15  
5
5  
30  
10  
5
10  
15  
5
15  
0
Pn PL  
10  
15  
5
0
Maximum clock  
pulse frequency  
2
4
10  
15  
5
10  
8
15  
January 1995  
9
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
Fig.7 Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP, BIN/DEC to CP  
and UP/DN to CP. Set-up and hold times are shown as positive values but may be specified as negative  
values.  
Fig.8 Waveforms showing minimum pulse width for PL, recovery time for PL, and set-up and hold times for Pn  
to PL. Set-up and hold times are shown as positive values but may be specified as negative values.  
January 1995  
10  
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in  
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in  
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...  
Fig.9 Timing diagram; decade mode; P0 = LOW; P3 = LOW; BIN/DEC = LOW.  
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in  
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in  
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...  
Fig.10 Timing diagram; binary mode; P0 = HIGH; P1 = LOW; BIN/DEC = HIGH.  
Philips Semiconductors  
Product specification  
Synchronous up/down counter,  
binary/decade counter  
HEF4029B  
MSI  
APPLICATION INFORMATION  
Some examples of applications for the HEF4029B are:  
Programmable binary and decade counting/frequency synthesizers - BCD output.  
Analogue-to-digital and digital-to-analogue conversion.  
Up/down binary counting.  
Magnitude and sign generation.  
Up/down decade counting.  
Difference counting.  
January 1995  
13  
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in  
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in  
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...  
Fig.11 Example of parallel clocking when cascading HEF4029B ICs.  
Note  
TC lines at all stages after the first may have a negative-going glitch pulse resulting from differential delays of different HEF4029B ICs. These  
negative-going glitches do not affect proper HEF4029B operation; however if the TC signals are used to trigger other edge-sensitive logic devices,  
such as flip-flops or counters, the TC signals should be gated with the clock signal using a 2-input OR gate such as HEF4071B.  
Fig.12 Example of ripple clocking when cascading HEF4029B ICs. Ripple clocking mode: the up/down control can be changed at any count;  
the only restriction on changing the up/down control is that the clock input to the first counting stage must be HIGH.  
WWW.ALLDATASHEET.COM  
Copyright © Each Manufacturing Company.  
All Datasheets cannot be modified without permission.  
This datasheet has been download from :  
www.AllDataSheet.com  
100% Free DataSheet Search Site.  
Free Download.  
No Register.  
Fast Search System.  
www.AllDataSheet.com  
配单直通车
HEF4029BP产品参数
型号:HEF4029BP
是否Rohs认证: 不符合
生命周期:Transferred
包装说明:DIP, DIP16,.3
Reach Compliance Code:unknown
风险等级:5.8
计数方向:BIDIRECTIONAL
JESD-30 代码:R-PDIP-T16
JESD-609代码:e0
负载电容(CL):50 pF
负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:2000000 Hz
最大I(ol):0.00036 A
工作模式:SYNCHRONOUS
功能数量:1
端子数量:16
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:DIP
封装等效代码:DIP16,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
电源:5/15 V
认证状态:Not Qualified
子类别:Counters
表面贴装:NO
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!