18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
HG74ALVC162835C
Jan. 1999
General Description
Features
The HG74ALVC162835C is an 18-bit universal bus
driver designed for 2.3V to 3.6 V VCC Operation.
l Ideal for Use in PC100 Registered DIMM
l 0.5mm CMOS Technology
l 2.3 ~ 3.6 VCC Operation
l Output Port Has 26-WSeries Damping
Resistor, No External Resistors are Required
l Package Options Include Plastic Thin Shrink
Small-Outline Packages, Shrink Small-Outline
Packages , Thin Very Small Outline Packages
(TSSOP 56 Pins, SSOP 56 Pins , TVSOP 56 Pins)
The Output Enable(OE) controls data flow from A to Y.
The device operates in transparent mode when the
latch-enable(LE) input is high. When LE is low, the A
data is latched if the clock input is held at a high or low
logic level. If LE is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the Outputs are in the high
impedance state. OE should be tied to VCC through a
pull up resistor to ensure the high impedance state
during power up or power down.
Pin Configuration
The equivalent 26-W series resistors are included in
the output to reduce overshoot and undershoot.
(TOP VIEW)
NC
NC
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
The HG74ALVC162835C is characterized for operation
from -40°C to 85°C.
Y1
3
A1
GND
Y2
4
GND
A2
5
Y3
6
A3
Vcc
Y4
7
Vcc
A4
8
Y5
9
A5
Function Table
Y6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A6
GND
Y7
GND
A7
INPUTS
Y8
A8
OUTPUT
Y9
A9
Y
LE
CLK
A
OE
Y10
Y11
Y12
GND
Y13
Y14
Y15
Vcc
Y16
Y17
GND
Y18
A10
A11
A12
GND
A13
A14
A15
Vcc
A16
A17
GND
A18
CLK
GND
H
L
L
L
L
L
X
H
H
L
L
L
X
X
X
•
X
L
H
L
H
X
Z
L
H
L
H
YO
•
=
L or H
=Output level before the indicated steady-state input
conditions were established, provided that CLK is high
before LE goes low.
26
27
28
OE
LE
NC- No ineternal connection
Copyright©1999, Hyundai Electronics Industries Co., Ltd.
ELECTRONICS