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  • 深圳市一呈科技有限公司

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  • HI-3717PQI
  • 数量3210 
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  • 批号23+ 
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产品型号HI-3717PQI的Datasheet PDF文件预览

HI-3717  
Single-Rail ARINC 717 Protocol IC  
with SPI Interface  
November 2011  
GENERALDESCRIPTION  
APPLICATIONS  
The HI-3717 from Holt Integrated Circuits is a CMOS device  
designed for interfacing an ARINC 717 compatible bus to a  
Serial Peripheral Interface (SPI) enabled micro-controller.  
The part includes a selectable Harvard Bi-Phase (HBP) or  
Bi-Polar Return-to-Zero (BPRZ) receive channel and  
transmit channels with HBP and BPRZ encoders and line  
drivers. The receive channel has integrated analog line  
receivers and the transmit channels have integrated line  
drivers for the corresponding encoding method (HBP and  
BPRZ). The part operates from a single +3.3V supply using  
only four external capacitors. Each transmit and receive  
channel has a 32-word by 12-bit FIFO for data buffering.  
· Digital Flight Data Acquisition Units (DFDAU)  
· Digital Flight Data Recorders (DFDR)  
· Quick Access Recorders (cassette type)  
· Expandable Flight Data Acquisition and Recording  
Systems  
PIN CONFIGURATIONS (Top View)  
The HI-3717 is available in very small 44-pin 7mm x 7mm  
Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic  
packages.  
NOCONV - 1  
RINB-40 - 2  
RINB - 3  
33 - OUTHA  
32 - TXOUTHA  
31 - TXOUTHB  
30 - OUTHB  
29 - TXHB  
RINA - 4  
HI-3717PCI  
HI-3717PCT  
HI-3717PCM  
RINA-40 - 5  
GND - 6  
TFIFO - 7  
TEMPTY - 8  
INSYNC - 9  
SYNC0 - 10  
SYNC1 - 11  
FEATURES  
· Compliant with ARINC 717 and ARINC 573 standards  
· Operates from a single +3.3V supply with on-chip  
converters to provide proper voltages for both Harvard  
Bi-Phase (HPB) and Bi-Polar Return-to-Zero (BPRZ)  
outputs  
28 - TXBA  
27 - OUTBA  
26 - TXOUTBA  
25 - TXOUTBB  
24 - OUTBB  
23 - TXBB  
· One selectable receive channel as HBP or BPRZ with  
integrated analog line receiver  
44 - Pin Plastic 7mm x 7mm  
Chip-Scale Package (QFN)  
· Both HBP and BPRZ transmitters have integrated line  
drivers as well as digital outputs  
· 32-word by 12-bit FIFOs for both the receive and the  
transmit channel  
· Programmable slew rates on transmit channels: 1.5μs,  
7.5μs or 10μs  
· Digital transmitter outputs available for use with  
external line drivers  
33 - OUTHA  
32 - TXOUTHA  
31 - TXOUTHB  
30 - OUTHB  
29 - TXHB  
NOCONV - 1  
RINB-40 - 2  
RINB - 3  
RINA - 4  
RINA-40 - 5  
GND - 6  
TFIFO - 7  
TEMPTY - 8  
INSYNC - 9  
SYNC0 - 10  
SYNC1 - 11  
· Programmable bit rates: 384, 768, 1536, 3072, 6144,  
12288, 24576, 49152 and 98304 bits/sec (32, 64, 128,  
256, 512, 1024, 2048, 4096 and 8192 words/sec)  
HI-3717PQI  
HI-3717PQT  
HI-3717PQM  
28 - TXBA  
· Enhanced Sync detection allows multiple false sync  
marks in user data while still synchronizing within 8  
seconds  
27 - OUTBA  
26 - TXOUTBA  
25 - TXOUTBB  
24 - OUTBB  
23 - TXBB  
· Fast SPI transmitter write and receiver read modes  
· Match pin flags when preprogrammed word count /  
subframe is received  
· Frame / subframe word count indicator  
· Industrial and Extended temperature ranges  
· Burn-in available  
44 - Pin Plastic Quad Flat Pack (PQFP)  
HOLT INTEGRATED CIRCUITS  
www.holtic.com  
(DS3717 Rev. B)  
11/11  
HI-3717  
BLOCK DIAGRAM  
VDD  
TXHA  
5Ω  
5Ω  
OUTHA  
Transmit  
32 x 12-BIT  
FIFO  
Transmit  
Rate  
37.5Ω  
37.5Ω  
TXOUTHA  
TXOUTHB  
Line  
HBP  
Driver  
Encoder  
Selection  
OUTHB  
TXHB  
Slew  
Rate  
&
Loopback  
Test  
TXBA  
Control  
5Ω  
5Ω  
OUTBA  
TXOUTBA  
TXOUTBB  
37.5Ω  
37.5Ω  
Line  
BPRZ  
Driver  
Encoder  
OUTBB  
TXBB  
NOCONV  
MR  
+3.3V  
V+  
Transmit FIFO  
V+  
V-  
Status Register  
TXFSTAT  
47uF  
V-  
SCK  
CS  
SI  
SO  
47uF  
DC / DC  
SPI  
C1+  
Converter  
Interface  
0.47uF  
C1-  
C2+  
C2-  
Control  
Control  
ARINC 717  
2.2uF  
Register 0  
CTRL0  
Register 1  
ACLK  
RSEL  
Clock  
CTRL1  
Divider  
FIFO Status Pin  
Word Count  
Receive FIFO  
Assignment  
Register  
FSPIN  
Utility Register  
Status Register  
RXFSTAT  
WRDCNT  
MATCH  
RFIFO  
TFIFO  
TEMPTY  
HBP Line  
Receiver  
RINA  
RINB  
40 KΩ  
40 KΩ  
HBP / BPRZ  
Clock  
RINA-40  
RINB-40  
HBP / BPRZ  
Data  
RECEIVE  
32 x 12-BIT  
FIFO  
SYNC  
Recovery  
&
ROVF  
Detect  
Sampler  
Decoder  
INSYNC  
SYNC1  
SYNC0  
BPRZ Line  
Receiver  
GND  
FIGURE 1.  
HOLT INTEGRATED CIRCUITS  
2
HI-3717  
PIN DESCRIPTIONS  
SIGNAL FUNCTION  
Internal  
DESCRIPTION  
Pull-up / Down  
50KΩ pull-down  
NOCONV  
RINB-40  
RINB  
RINA  
RINA-40  
GND  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
POWER  
Disables on-chip DC-DC voltage converter  
Alternate receiver negative input. Requires external 40K ohm resistor  
Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)  
Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)  
Alternate receiver positive input. Requires external 40K ohm resistor  
Chip 0V Supply (All GND pins on package must be connected)  
Output is user programmable to indicate the Transmit FIFO Full or Half-full state.  
TFIFO  
OUTPUT  
OUTPUT  
See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.  
TEMPTY  
Output goes high when the transmit FIFO is empty  
Output goes high when the receiver is synchronized to the incoming data. Synchroni-  
zation occurs at the next valid sync mark following the detection of the proper  
number and order of consecutively spaced sync marks. See Table 3.  
Output in conjunction with SYNC1 output indicates when each of the four ARINC 717  
subframe sync words are received. Only valid when the INSYNC pin is high.  
Output in conjunction with SYNC0 output indicates when each of the four ARINC 717  
subframe sync words are received. Only valid when the INSYNC pin is high.  
Output goes high when the value of the Frame Word Count Register matches the  
value in the Frame Count Utility Register, WRDCNT.  
Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty  
state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.  
Receive FIFO Overflow. Output goes high when an attempt is made to load a full  
Receive FIFO  
INSYNC  
OUTPUT  
SYNC0  
SYNC1  
MATCH  
RFIFO  
ROVF  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
50KΩ pull-up  
50KΩ pull-down  
50KΩ pull-down  
50KΩ pull-down  
INPUT  
INPUT  
INPUT  
INPUT  
OUTPUT  
INPUT  
Master Reset, active low  
Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0  
SPI interface serial data input  
SPI Clock. Data is shifted into SI and out of SO when  
SPI Interface seral data output  
MR  
RSEL  
SI  
SCK  
SO  
is low.  
CS  
50KΩ pull-up  
Chip Select. Data is shifted into SI and out of SO using SCK when  
is low  
CS  
CS  
50KΩ pull-down  
ACLK  
TXBB  
INPUT  
OUTPUT  
Master timing source for receiver and transmitters. 24 MHZ ±0.1%  
Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)  
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external  
32.5 ohm resistor  
Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717  
bus  
Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC  
717 bus  
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external  
32.5 ohm resistor  
OUTBB  
TXOUTBB  
TXOUTBA  
OUTBA  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)  
Harvard Bi-Phase (HBP) digital low output (external line driver required)  
TXBA  
TXHB  
OUTPUT  
OUTPUT  
Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5  
ohm resistor  
OUTHB  
OUTPUT  
Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus  
Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus  
Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5  
ohm resistor  
TXOUTHB  
TXOUTHA  
OUTPUT  
OUTPUT  
OUTHA  
OUTPUT  
Harvard Bi-Phase (HBP) digital high output (external line driver required)  
TXHA  
V-  
C2-  
C2+  
V+  
C1+  
C1-  
VDD  
OUTPUT  
CONVERTER DC/DC converter negative voltage  
CONVERTER DC/DC converter fly capacitor for V-  
CONVERTER DC/DC converter fly capacitor for V-  
CONVERTER DC/DC converter positive voltage  
CONVERTER DC/DC converter fly capacitor for V+  
CONVERTER DC/DC converter fly capacitor for V+  
Chip +3.3V Supply  
POWER  
TABLE 1.  
HOLT INTEGRATED CIRCUITS  
3
HI-3717  
SERIAL PERIPHERAL  
INTERFACE (SPI)  
HI-3717 SPIINSTRUCTIONS  
SPI BASICS  
Instruction op codes are used to read, write and configure the  
HI-3717. Each SPI read or write operation begins with an 8-bit  
instruction. When CS goes low, the next 8 clocks at the SCK  
pin shift an instruction op code into the decoder, starting with  
the first rising edge. The op code is shifted into the SI pin, most  
significant bit (MSB)first.The SPIcan be clocked up to10 MHz.  
The HI-3717 uses an SPI (Serial Peripheral Interface) for host  
access to internal registers and data FIFOs. Host serial  
communication is enabled through the Chip Select (CS) pin,  
and is accessed via a four-wire interface consisting of Serial  
Data Input (SI) from the host, Serial Data Output (SO) to the  
host and Serial Clock (SCK). All read / write cycles are  
completely self-timed.  
The SPI instructions are of a common format. The most  
significant bit (MSB) specifies whether the instruction is a write  
“0” or read “1” transfer.  
The SPI protocol specifies master and slave operation; the  
HI-3717 operates as an SPIslave.  
The SPI protocol defines two parameters, CPOL (clock  
polarity) and CPHA (clock phase). The possible CPOL-CPHA  
combinations define four possible “SPI Modes”. Without  
describing details of the SPI modes, the HI-3717 operates in  
Mode 0 where input data for each device (master and slave) is  
clocked on the rising edge of SCK, and output data for each  
device changes on the falling edge (CPHA= 0, CPOL = 0). The  
host SPI logic must be set for Mode 0 for proper  
communications with the HI-3717 .  
X
6
X
5
X
4
X
3
X
2
X
1
X
0
MSB  
7
LSB  
SPI INSTRUCTION FORMAT  
For write instructions, the most significant bit of the data word  
must immediately follow the instruction op code and is clocked  
into its register on the next rising SCK edge. Data word length  
varies depending on word type written: 8-bit Control & Status  
Register writes, 16-bit Word Count Utility Register writes and  
16-bitTransmit FIFOwrites.  
As seen in Figure 2, SPI Mode 0 holds SCK in the low state  
when idle. The SPI protocol transfers serial data as 8-bit bytes.  
Once CS is asserted, the next 8 rising edges on SCK latch input  
data into the master and slave devices, starting with each byte's  
most-significant bit. A rising edge on CS terminates the serial  
transfer and re-initializes the HI-3717 SPI for the next transfer.  
If CS goes high before a full byte is clocked by SCK, the  
incomplete byte clocked into the device SIpin is discarded.  
For read instructions, the most significant bit of the requested  
data word appears at the SO pin at the next falling SCK edge  
after the last op code bit is clocked into the decoder. As in write  
instructions, the data field bit-length varies with read instruction  
type.  
In the general case, both master and slave simultaneously  
send and receive serial data (full duplex), per Figure 2 below.  
However the HI-3717 operates half duplex, maintaining high  
impedance on the SO output, except when actually transmitting  
serial data. When the HI-3717 is sending data on SO during  
read operations, activity on its SI input is ignored. Figure 3 and  
Figure 4 show actual behavior forthe HI-3717 SOoutput.  
Since HI-3717 operates in half-duplex mode, the host discards  
the dummy byte it receives while serially transmitting the  
instruction op code tothe HI-3717.  
SCK  
(SPI Mode 0)  
High Z  
SI  
SO  
CS  
MSB  
MSB  
LSB  
High Z  
LSB  
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0  
HOLT INTEGRATED CIRCUITS  
4
HI-3717  
Figure 3 and Figure 4 show read and write timing as it appears  
Note: SPI Instruction op-codes not shown in Table 2 are  
“reserved” and must not be used. Further, these op-codes will  
not provide meaningful data in response toa read instruction.  
for a single-byte and dual-byte register operation. The  
instruction op code is immediately followed by a data byte  
comprising the 8-bit data word read or written. For a register  
read or write, CS is negated afterthe data byte is transferred.  
Two instruction bytes cannot be “chained”; CS must be negated  
after each instruction, and then reasserted for the following  
Read or Write instruction.  
Table 2 summarizes the HI-3717 SPIinstruction set.  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
MSB  
LSB  
SI  
Op-Code Byte  
MSB  
LSB MSB  
High Z  
High Z  
SO  
CS  
Data Byte  
Host may continue to assert CS  
here to read sequential byte(s)  
when allowed by the instruction.  
Each byte needs 8 SCK clocks.  
FIGURE 3. Single-Byte Read From a Register  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
SPI Mode 0  
MSB  
LSB MSB  
LSB MSB  
LSB  
SI  
Op-Code Byte  
Data Byte 0  
Data Byte 1  
High Z  
SO  
CS  
Host may continue to assert CS  
here to write sequential byte(s)  
when allowed by the SPI instruction.  
Each byte needs 8 SCK clocks.  
FIGURE 4. 2-Byte SPI Write Example  
HOLT INTEGRATED CIRCUITS  
5
HI-3717  
# Data  
bytes  
OP Code R/W  
DESCRIPTION  
0x64  
W
1
Write Control Register 0  
Write Control Register 1  
Write Receiver FIFO Status Pin Assignment Register  
Write Word Count Utility Register  
Write Transmit FIFO word  
0x62  
0x6A  
0x72  
0x74  
0x2*  
W
W
W
W
W
1
1
2
2
1
Fast Write Transmit FIFO Word  
0xE4  
R
1
Read Control Register 0  
0xE2  
0xE6  
0xE8  
0xEA  
0xF2  
0xF6  
0xFE  
0xC*  
R
R
R
R
R
R
R
R
1
1
1
1
2
2
4
1
Read Control Register 1  
Read Receive FIFO Status Register  
Read Transmit FIFO Status Register  
Read Receive FIFO Status Pin Assignment Register  
Read Word Count Utility Register  
Read Receive FIFO Word  
Read Receive FIFO Word and Word Count  
Fast Read Receive FIFO  
* In the case of FAST instructions, the last four bits of the instruction byte are data  
TABLE 2. SPI Instruction Set  
REGISTER DESCRIPTIONS  
CONTROL REGISTER 0: CTRL0  
BR1  
SLEWR0XSEL  
X
7
MSB  
Read: SPI Op-code 0xE4  
Write: SPI Op-code 0x64  
6
5
4
3
2
1
0
LSB  
Bit  
Name  
-
R/W Default Description  
7
R/W  
R/W  
0
0
Not Used. Always reads a “0”  
6 -4  
BR2:0  
Setting these bits setstheARINC 717 data rate forboth the receive and transmitdata.  
000 768 Bits/sec. (64 words/sec.)  
001 1536 Bits/sec. (128 words/sec.)  
010 3072 Bits/sec. (256 words/sec.)  
011 6144 Bits/sec. (512 words /sec.)  
100 12288 Bits/sec. (1024 words/sec.)  
101 24576 Bits/sec. (2048 words/sec.)  
110 49152 Bits/sec. (4096 words/sec.)  
111 98304 Bits/sec. (8192 words/sec.)  
3
32WPS  
R/W  
0
0
Setting this bit overrides the stateofBR2:0 and setsthe data rate at384 Bits/sec. (32 words/sec.)  
Setting these bits controls the nominal slew rate on both the HBP&BPRZtransmitchannel outputs.  
2-1 SLEW1:0 R/W  
00  
01  
10  
11  
7.5 µs  
10.0 µs(Same asARINC 429 Low Speed)  
10.0 µs(Same asARINC 429 Low Speed)  
1.5 µs(Same asARINC 429 High Speed)  
0
RXSEL  
R/W  
0
Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input  
pin.  
TABLE 3.  
HOLT INTEGRATED CIRCUITS  
6
HI-3717  
REGISTER DESCRIPTIONS (cont.)  
CONTROL REGISTER 1: CTRL1  
NOSYNC  
TEST  
SRSTSFTSYNC  
X X  
X X  
Read: SPI Op-code 0xE2  
Write: SPI Op-code 0x62  
7
6
5
4
3
2
1
0
LSB  
MSB  
Bit  
7 -4  
3
Name  
-
R/W Default Description  
R/W  
R/W  
0
0
Not Used,Always reads a “0”  
SRST  
Software Reset - Setting this bit to “1” empties all the FIFO’s, clears the Sync detection logic and  
setsthe analog line drivers toHi-Zstate. All other register bits remain unchanged.  
2
1
SFTSYNC R/W  
NOSYNC R/W  
0
0
Software Synchronization - Setting the bit to “1” will result in the INSYNC output pin going high  
when the third ofthree consecutively occurring sync marksis detected.  
No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the  
receive FIFO. WARNING: In this mode there is no way the HI-3717 can determine frame or sub-  
frame boundaries.This sync mode overrides all the other sync modes when setto1”.  
0
TEST  
R/W  
0
Test Mode -A1” in this bit position will disable the line receiver and both line drivers and the digital  
transmitted data will be looped back tothe HBPor BPRZdata sampler selected by RXSEL.  
TABLE 4.  
RECEIVE FIFO STATUS REGISTER: RXFSTAT  
C
Y
1
N
C
Y
N
S
N
I
SYNC0  
RFOVF  
TEST  
RFHARLFFEMPTY  
S
X X  
X X X X  
X X  
Read: SPI Op-code 0xE6  
Write: Read Only  
7
6
5
4
3
2
1
0
LSB  
MSB  
Bit  
7
Name  
R/W Default Description  
INSYNC  
R
0
Receive channel sync indicator. The bit is set to”1” when synchronization is achieved on the  
receive channel.  
Normal synchronization occurs when four consecutive valid sync marks (Octal 1107, 2670, 5107  
and 6670 respectively) are received exactly 1 second apart. The bit is set when the next valid and  
properly spaced subframe sync mark (Octal1107) is detected.  
Software Synchronization (CTRL1<2> = “1”) occurs when two consecutively valid sync marks are  
received exactly 1 second apart and in the proper order but the first sync mark does not have to be  
Octal1107. The bit is setwhen the next valid and properly spaced subframe sync markis detected.  
The bit remains set until synchronization is lost at which time the device automatically attempts to  
re-synchronize. No data is passed to the receive FIFO until Synchronization is re-established.  
Existing data in the FIFOremains intact and can be read atany time.  
6-5 SYNC0:1  
R
0
The two bits are a realtime indicators of when each of the fourARINC 717 subframe sync marks are  
received. They are updated when the sync mark is detected and passed to the Receive FIFO. The  
two bits are only valid when INSYNC is “1”  
00  
01  
10  
11  
Subframe SYNC1 markreceived (Octal1107)  
Subframe SYNC2 markreceived (Octal2670)  
Subframe SYNC3 markreceived (Octal5107)  
Subframe SYNC4 markreceived (Octal6670)  
4
3
2
RFFULL  
RFHALF  
R
R
R
0
0
1
Bitis setwhen the Receive FIFOcontains 32 words.  
Bitis setwhen the Receive FIFOcontains exactly 16 words.  
RFEMPTY  
Bit is set when the Receive FIFO is empty. It is reset to”0” when the first valid word is passed to the  
Receive FIFO.  
1
0
RFOVF  
-
R
R
0
0
FIFO Overflow bit and ROVF pin are set to “1” when devices attempts to load a valid word to a full  
Receive FIFO.The Receive FIFOwill ignore additional words ifitis full.  
Not used, Always reads “0”  
TABLE 5.  
HOLT INTEGRATED CIRCUITS  
7
HI-3717  
REGISTER DESCRIPTIONS (cont.)  
TRANSMIT FIFO STATUS REGISTER: TXFSTAT  
L
F
L
L
U
A
F
H
F
F
T
TFEMPTY  
FFOVFW  
TEST  
FFHAFLFFEMPTY  
T
X X  
X X X X  
X X  
Read: SPI Op-code 0xE8  
Write: Read Only  
7
6
5
4
3
2
1
0
LSB  
MSB  
Bit  
7
Name  
TFFULL  
TFHALF  
TFEMPTY  
R/W Default Description  
R
R
R
0
0
1
Setwhen theTransmit FIFOcontains 32 words  
Setwhen theTransmit FIFOcontains exactly 16 words  
6
5
Set when theTransmit FIFO is empty. Reset to “0” when at least one word is loaded to theTransmit  
FIFO.  
4 -0  
-
R
0
Not used,Always reads “0”  
TABLE 6.  
FIFO STATUS PIN ASSIGNMENT  
REGISTER: FSPIN  
1
0
O
O
F
F
I
I
F
F
R
TFIFO  
FFOVFW  
TEST  
FFHAFLFFEMPTY  
R
X X X X X X X X  
Read: SPI Op-code 0xEA  
Write: SPI Op-code 0x6A  
7
6
5
4
3
2
1
0
LSB  
MSB  
Bit  
Name  
R/W Default Description  
7 -6 RFIFO1:0 R/W  
0
These bits program which Receive FIFOStatusRegister bit is represented by the RFIFOpin .  
00  
01  
10  
11  
RFIFOpin is set1” when Receive FIFOStatusRegister Bit2, RFEMPTY, is “1”.  
RFIFOpin is set1” when Receive FIFOStatusRegister Bit3, RFHALF, is “1”.  
RFIFOpin is set1” when Receive FIFOStatusRegister Bit3, RFHALF, is “1”.  
RFIFOpin is set1” when Receive FIFOStatusRegister Bit4, RFFULL, is “1”.  
5
TFIFO  
-
R/W  
R
0
0
Thebit programs whichTransmit FIFOStatusRegister bit is represented by theTFIFOpin.  
0
1
TFIFOpin is set1whenTransmit FIFOStatusRegister Bit7,TTFULL, is “1”.  
TFIFOpin is set1whenTransmit FIFOStatusRegister Bit6,TFHALF, is “1”.  
4 -0  
Not used,Always reads “0”  
TABLE 7.  
WORD COUNT UTILITY REGISTER: WRDCNT  
2
1
1
4
1
3
C
C
C10  
C6 C5  
C2  
S1 SO  
C0 FFEMPTY  
C
C8 C7  
C
Read: SPI Op-code 0xF2  
Write: SPI Op-code 0x72  
X X  
15 14 13 12 11 10  
X X X X  
X X  
X X X X  
X
X
X
X
9
8
7
6
5
4
3
2
1
0
LSB  
MSB  
The Word Count Utility Register can be programmed to generate an interrupt on the MATCH pin when the data for the specified word  
count of the specified subframe is loaded into the Receive FIFO. The Word Count Utility Register can used with any of the standard  
ARINC 717 data rate and all ofthe expanded data rates, except 8192 wps.  
Bit  
Name  
C12:0  
R/W Default Description  
15 -3  
R/W  
0
Subframe Word Count - The value is compared to the current word count in the Receive FIFO and  
sets the MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word  
time.  
2
-
R/W  
R/W  
0
0
Not used,Always reads “0”  
1 -0  
S1:0  
Subframe ID  
00  
01  
10  
11  
Subframe One  
SubframeTwo  
SubframeThree  
Subframe Four  
TABLE 8.  
HOLT INTEGRATED CIRCUITS  
8
HI-3717  
ARINC 717 MESSAGE AND BIT ORDERING  
The first 12- bit word of a subframe that appears on the ARINC 717  
bus is the synchronization code with the least significant bit (LSB)  
first. This is immediately followed by up to 8191 12-bit data words,  
all within1 second from the start of the synchronization code. The  
next three subframes immediately follow the first subframe with  
their synchronization code as the first 12-bit word of the subframe  
followed by the same number of data words as the first subframe.  
ARINC 717 messages consist of 12-bit words sent in a 4 second  
frame divided into four 1 second subframes. Each subframe  
consists of 64 (basic rate), 128, 256, 512, 1024, 2048, 4096 or  
8192 12 bit words, depending on the data rate of the target  
system.  
ARINC 717 data is transmitted between the HI-3717 and host  
microcontroller using the four-wire Serial Peripheral Interface  
(SPI). A read or write operation consists of a single-byte op-code  
followed by 8-bit data words. Figure 5 shows examples of how the  
SPI data bytes are mapped to the ARINC 717 message.  
The first word of each subframe contains a unique Barker Code  
synchronization pattern that identifies the subframe. The octal  
synchronization code for subframes 1 through 4 are 1107, 2507,  
5107 and 6670 respectively.  
ARINC717 Message as received / transmitted on the ARINC 717 serial bus  
Frame  
Subframe 1  
1 Second  
Subframe 2  
1 Second  
Subframe 3  
1 Second  
Subframe 4  
1 Second  
MSB  
MSB  
MSB  
MSB  
LSB  
LSB  
LSB  
LSB  
4 Seconds  
ARINC717 Subframe Format  
2nd Data Word  
Nth Data Word  
1st Subframe Sync Code (1107)  
1
1
1
0
0
0
1
0
0
1
0
0
0
1
2
3
4
5
6
7
8
9 10 11  
0
LSB  
1
2 3  
4 5  
6 7 8 9 10 11  
LSB  
MSB LSB  
MSB  
MSB  
1 Second  
time  
ARINC 717 Message as transferred on the SPI bus  
SPI Op-Code  
Don’t Care  
Subframe Sync or Data Word Bits  
0
1
1
0
X X X X 11 10  
8
7
5
4 3  
1
2
0
LSB  
0
1
0
9
6
1
MSB  
LSB MSB  
Example 1. Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x74).  
SPI Op-Code  
Always “0” Subframe Sync or Data Word Bits  
1
1
0
0
1
1
0
8
7 5 4 3 1  
6 2  
0
LSB  
1
0 0 0 0 11 10 9  
MSB  
LSB MSB  
Example 2. Read Receive FIFO Subframe Sync or Data Word (Op-Code 0xF6).  
SPI Op-Code Subframe Sync or Data Word Bits  
0 0 1 0 11 10 9  
MSB  
8
7
6
5
4 3  
2
1
0
LSB  
Example 3. Fast Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x2-) .  
SPI Op-Code  
Word Count Bits  
Sync Bits  
0
1
1
1
0
0
1
0
5
4 2 1 0 X 1  
0
LSB  
12 11 10 9 8  
7
6
3
MSB  
LSB MSB  
Example 4. Write Word Count Utility Register, WRDCNT (Op-Code 0x72).  
SPI Op-Code  
Always “0” Subframe Sync or Data Word Bits  
Word Count Bits  
Sync Bits  
1
1
1
1
1
1
0
0 0  
0
0
11 10 9  
8
7
5
4 3  
1
0
10  
8
2
1 0 1  
0
0
LSB  
1
6
2
12 11  
9
7 6  
5
4
3
MSB  
LSB MSB  
LSB MSB  
Always “0”  
Example 5. Read Receive FIFO Data Word with Word Count (Op-Code 0xFE).  
FIGURE 5. ARINC 717 & SPI Bit Ordering  
HOLT INTEGRATED CIRCUITS  
9
HI-3717  
FUNCTIONAL DESCRIPTION  
In order to avoid inadvertent transceiver operation, Control  
Register 0, CTRL0, should be programmed last. Writing  
CTRL0 sets the desired data rate which, after one bit period,  
the internal clocks are enabled. This in turn makes the  
transmitter or receiver operational. Changing the data rate on  
the fly may result in unpredictable operation during the  
transition to the new programmed state. A full reset, POR or  
MR, should be issued before reprogramming the data rate.  
OVERVIEW  
ARINC 717 is a continuous transmission of 12-bit words in 4 second  
frames divided into four 1 second subframes. The programmed  
data rate (32 to 8192 wps) determines the number of words per  
subframe. The first word of each subframe is reserved for a unique  
sync mark. Figure 5 illustrates the relationship betweenARINC 717  
frames, subframes and words.  
Data Rate  
The HI-3717 is comprised of independent ARINC 717 receive and  
transmit sections easily accessible via  
a four wire SPI  
For correct ARINC 717 date rate reception, transmission and bit  
timing, the HI-3717 requires a 24 MHz reference clock source  
applied to the ACLK input. This clock is divided down to achieve the  
data rate programmed with CNTL0<6:4>. The input receive data is  
8X oversampled relative to the programmed data rate.  
communications bus. It supports theARINC 717 Harvard Bi-Phase  
(HBP) protocol as well as the Bi-Polar Return to Zero (BPRZ)  
auxiliary protocol.  
The receiver accepts data from either a Harvard Bi-Phase (HBP) or  
a Bi-Polar Return to Zero (BPRZ) bus, recovers the clock, decodes  
the data, synchronizes the ARINC 717 data frames using the  
unique subframe sync marks and stores the recovered data in a 32  
word x12 bit Receive FIFO.  
ARINC 717 requires a basic data rate of 64 wps with support for  
128, 256 and 512 wps. The HI-3717 offers an expanded range of  
32 to 8192 wps for testing purposes and future expansion.  
CTRL0<3>, 32WPS, overrides the state of CTRL0<6:4> and sets  
the data rate to 32 wps. The required 0.1% timing tolerance is  
maintained over all data rates.  
The ARINC 717 Transmitter accesses data from a 32 word x 12 bit  
Transmit FIFO, encodes it into both HBP and BPRZ data streams at  
the selected data rate, and converts the digital data stream to  
ARINC 717 bus compatible outputs. There are separate outputs for  
the HBPand BPRZARINC 717 buses.  
Line Driver Output Slew Rates  
The slew rate of the HBP and BPRZ outputs is controllable with  
CNTR0<2:1>. A 7.5µs slew rate conforms to all the required  
ARINC 717 data rates. In addition, a 1.5µs is provided for the  
higher data rates and a 10µs for the 32 wps data rate.  
The receive and transmit sections operate at the same data rate  
and they are configured and monitored via the SPIinterface.  
Refer to Figure 1 for the Block Diagram of the HI-3717  
Receiver Format  
INITIALIZATION AND RESET  
The ARINC 717 format of the receiver is selectable as HBP or  
BPRZ by the state in CNTL0<0>, RXSEL, OR’d with the state of the  
external RSEL input pin. A “0” on RSEL and CNTL0<0> selects  
HBP and a “1” on either RSEL or CNTL0<0> selects BPRZ.  
The HI-3717 generates a full reset upon application power. The  
power-on-reset (POR) sets all registers to their default values,  
places the Receive and Transmit FIFOs to their empty state, and  
clears the sync detection logic. It also sets both the HBP and BPRZ  
outputs to the high impedance state and the input sampling and  
decoders are disabled. See Register Descriptions for complete  
definition ofthe default values.  
Refer to Table 3 for the detail description of each bit in Control  
Register 0.  
Input Synchronization Mode  
The part can also be initialized to the full reset state by applying a  
100ns active low pulse tothe external MR pin.  
The HI-3717 has three different synchronization modes, depending  
on how it is being used.  
A software reset is also possible via the SPI communications  
interface by writing a “1” to the CTRL1<3>. This bit places both the  
Receive and Transmit FIFO’s in the empty state, clears the sync  
detection logic, and sets both the HBP and BPRZ line drivers to a  
high impedance state. All other registers remain unchanged. The  
device is held in the reset stateuntil a “0” is written toCTRL1<3>.  
1. Flight Recorder Mode  
This is the normal synchronization mode. In this mode the  
HI-3717 searches for the four subframe sync marks:  
SYNC1 = Octal 1107  
SYNC2 = Octal 2670  
SYNC3 = Octal 5107  
SYNC4 = Octal 6670  
CONFIGURATION  
in the correct sequential order starting from SYNC1 and the  
exact bit time determined by the programmed word rate. When  
synchronization is achieved the INSYNC pin as well as the  
INSYNC bit of the Receive FIFO Status Register, RXFSTAT<7>  
are set to “1” on the next valid SYNC1 mark. The valid SYNC1  
mark and following data words are stored in the Receive FIFO.  
The HI-3717 is configured via the SPI communications bus by  
writing to Control Register 0, CTRL0, and Control Register 1,  
CTRL1. They are reset to 0x00 following a Power On Reset  
(POR) or a Master Reset (MR) but remain unchanged on a  
Software Reset, CTRL1<3>, SRST. The function of each register  
bit is shown in the Register Descriptions.  
Sync time varies from 4 seconds to a worst case of 8 seconds  
for a valid data stream.  
HOLT INTEGRATED CIRCUITS  
10  
HI-3717  
FUNCTIONAL DESCRIPTION (cont.)  
with RSEL pin or CTRL1<0>, writing the transmit FIFO and  
reading the receive FIFO. All status pins and registers reflect the  
status of the loopback operation.  
The first word stored in the Receive FIFO is available when  
RXFSTAT<2>, RFEMPTY, is reset to “0”, which is 12-bit periods  
(one word time) after INSYNC is set to “1”.  
FIFO Status Pin Assignment Register, FSPIN  
The HI-3717 remains in sync as long as the proper sync  
sequence is maintained. INSYNC is reset to “0” when the next  
expected subframe sync mark is not present. The HI-3717 will  
initiate a new synchronization process at the next valid SYNC1  
mark.  
This register assigns the function of the external RFIFO and  
TFIFO pins. The RFIFO pin reflects the state of one of the three  
Receive FIFO status flags (RFFULL, RFHALF and RFEMPTY) in  
the Receive FIFO Status Register, RXFSTAT. The TFIFO pin  
reflects the state of one of two Transmit FIFO status flags (TFULL  
or TFHALF) in the TFXSTAT register. Refer to the FSPIN Register  
Description in Table 7 for register assignment details.  
Once the part falls out of sync, the whole previous subframe  
should be discarded.  
2. Test Mode  
Word Count Utility Register, WRDCNT  
In this mode the HI-3717 searches for any two subframe sync  
marks in the correct sequential order and the exact starting time  
for the sync mark. INSYNC is set to “1” when the third valid sync  
mark is detected. The part must continue to detect each sync  
mark in the correct order and with the correct starting time to  
stay in sync.  
The MATCH pin goes high when the HI-3717 is in the INSYNC  
condition and the word count and subframe count matches the  
value programmed in the Word Count Utility Register. Note: The  
INSYNC pin is set to “1” when the second consecutive SYNC1  
mark of the proper sync sequence is received. The Word Count  
Utility Register and Match pin function can be used for the  
standard ARINC 717 data rates and all of the expanded data rates,  
except 8192 wps.  
This method reduces the time required to obtain sync to about 2  
seconds typical and a worst case of 3 seconds.  
3. No Sync Detect Mode  
ARINC 717 RECEIVER  
In this mode, the INSYNC is set to “1” and all data is stored in  
the Receive FIFO. Without sync detection, the Receive FIFO  
just records the sequential bits, not words, from the bus. It is up  
to the user to detect the sync marks and determine the word  
boundaries in this mode.  
The input data stream for ARINC 717 can be one of two formats.  
The main ARINC 717 bus to a Digital Flight Data Recorder (DFDR)  
uses Harvard Bi-phase (HBP) encoding and the auxiliary output  
bus to an Aircraft Integrated Data System (AIDS) uses Bi-Polar  
Return toZero(BPRZ)encoding as shown in Figure 6.  
In both the Flight Recorder Mode and the Test Mode, the HI-3717  
uses a proprietary sync tracking and detection method which allows  
multiple random false sync marks in the user data without  
increasing the sync time.  
The HI-3717 has an independentARINC 717 receive channel with a  
selectable on-chip HBP analog line receiver for connection to the  
main incomingARINC 717 data bus or a BPRZ analog line receiver  
forconnection toan auxiliary data bus.  
Digital Loopback  
TheARINC 717 specification requires the following detection levels  
forthe HBPinputs:  
Normal HI-3717 operation is with CTRL1<0> set to “0”. Setting it to  
“1” places the part in digital loopback mode. In this mode the  
analog line receivers are disconnected from the data samplers and  
both output line drivers are placed in a high impedance state. The  
output encoders are connected to input sampler / decoder. The  
part may be verified by selecting the desired receive decode format  
STATE  
DIFFERENTIAL VOLTAGE  
HI  
NULL  
LO  
+2 Volts to +8 Volts  
NA  
-2 Volts to -8 Volts  
+5V  
Harvard Bi-Phase  
-5V  
+10V  
Bi-Polar Return to Zero  
-10V  
Data  
1
0
1
1
0
1
0
1
0
0
1
1
LSB  
MSB  
FIGURE 6. ARINC 717 HBP & BPRZ Differential Input Signal Format  
HOLT INTEGRATED CIRCUITS  
11  
HI-3717  
FUNCTIONAL DESCRIPTION (cont.)  
For Havard Bi-phase, HBP, coding, the sampler validates a HI  
(One) or LO (Zero) if the signal is in that state for at least two  
samples. There is no Null stateforthe HBPformat.  
The auxiliary BPRZ input detection levels are the same as  
standard ARINC 429 levels:  
The Bi-Polar Return to Zero, BPRZ, coding sampler validates that  
at least two consecutive Ones or two consecutive Zeroes are  
followed by atleast two consecutive Null states.  
STATE  
DIFFERENTIALVOLTAGE  
ONE  
NULL  
ZERO  
+6.5 Volts to +13 Volts  
+2.5 Volts to -2.5 Volts  
-6.5 Volts to -13 Volts  
Decoders  
The HI-3717 guarantees recognition of these levels with a  
common mode voltage with respect to GND less than ±25V for the  
worst case conditions (3.15V supply, 8V HBP signal level and 13V  
BPRZ signal level).  
The decoder recovers the clock and resynchronizes each valid one  
or zero tothe transition bit period.  
The Harvard Bi-phase, HBP, decoder confirms the sampler only  
provided a valid One or Zero, not both, then detects the presence of  
absence of an edge in the data bit period. The output of the decoder  
is a “1” ifthere was a transition, otherwise a “0”.  
Design tolerances guarantee detection of the above levels, so the  
actual acceptance ranges are slightly larger. If the signal (including  
nulls) is outside the differential voltage ranges, the HI-3717 receiver  
rejects the data.  
The Bi-Polar Return to Zero, BPRZ, decoder confirms the sampler  
only provided a valid One or Zero, followed by a valid Null. The  
decoder output is a “1” fora valid One and “0” fora valid Zero.  
BitTiming& InputSampling  
Once the data is captured, it is re-sampled to the recovered  
transition rate clock (sample clock sent to the sync detector) and re-  
sampled torecover the data bit rate clock.  
The bit timing for both the receive and transmit functions is the data  
rate programmed in CTRL0<6:3>. The HI-3717 allows the  
following word /bit rates:  
The decoders will operate correctly when the input data bit period is  
not more than 2 sample clocks (25%) larger or 1 sample clock  
(12.5%) smaller than the nominal value. The slower input frequency  
causes a mismatch between the sampled data and the recovered  
clock. The faster input frequency causes issues with internal edge  
detection logic.  
32 words/sec. = 384 Bits/sec  
64 words /sec. = 768 Bits/sec.  
128 words/sec. = 1536 Bits/sec.  
256 words/sec. = 3072 Bits/sec.  
512 words /sec. = 6144 Bits/sec.  
1024 words/sec. = 12288 Bits/sec.  
2048 words/sec. = 24576 Bits/sec.  
4096 words/sec. = 49152 Bits/sec.  
8192 words/sec. = 98304 Bits/sec.  
Any incorrectly decoded data will cause the next sync mark to be  
missed and the INSYNC bit togo to0”.  
The 32 WPS data rate is typically used for testing purposes.  
SYNC Detect  
The input data from the selected analog line receiver is  
oversampled at 8X relative to the word rate programmed in  
CTRL0<6:3>. This is 4X oversample of the transition rate since the  
code rate forboth methods is double the data rate.  
The HI-3717 employs a proprietary, four level sync algorithm that  
samples each bit and compares each combination of 12-bits  
against the four validARINC 717 subframe sync marks.  
In the Flight Mode, once a valid SYNC1 mark is discovered, it  
continues to look for each of the next three subframe sync marks in  
the proper order and timing. If any one is not found, the search  
starts over looking for SYNC1 again. Once all four sync marks are  
detected in the proper order and location in a frame, the INSYNC  
pin is set to “1” at the next SYNC1 subframe sync mark if it is the  
correct value and it occurs at the proper relationship to the previous  
valid sync mark. This is the default synchronization mode for the  
HI-3717.  
The sampler uses three separate shift registers, one each for  
Ones, Zero and Null detection. When the input signal is within the  
differential voltage range of one of the valid states (One, Zero or  
Null) of the selected data format, the sampler clocks “1” into that  
register and a “0” into the other two. When the signal is outside the  
differential voltage ranges defined for all the shift registers, a “0” is  
clocked into all three registers. Only one shift register can clock “1”  
for a given sample. The Null shift register is only used for the BPNZ  
format.  
In the Software Synchronization Mode, CTRL1<2> = “1”, once two  
consecutive valid subframe sync marks are detected, the INSYNC  
bit is set to “1” at the next consecutive valid subframe sync mark if it  
occurs at the proper relationship to the previous valid sync marks.  
The first valid subframe sync mark does not have to be SYNC1 in  
this mode but each successive subframe sync marks must be the  
next in the sequence and properly spaced from the preceding valid  
subframe sync mark.  
DIFFERENTIAL  
COMPARATORS  
VDD  
AMPLIFIERS  
RINA-40  
ONE  
RINA  
NULL  
GND  
VDD  
ZERO  
INSYNC is set to “0” when the next expected subframe sync mark is  
missed in the Flight Mode and Software Synchronization Modes.  
The HI-3717 sync detection logic is reset and the part initiates the  
full synchronization process again. The data from the subframe  
preceding the first incorrect subframe sync mark should be  
discarded. No data is passed to the Receive FIFO until synchroni-  
zation is reestablished.  
RINB  
RINB-40  
GND  
CNTL0<0>  
RSEL  
FIGURE 7. ARINC 717 Receiver Inputs  
HOLT INTEGRATED CIRCUITS  
12  
HI-3717  
FUNCTIONAL DESCRIPTION (cont.)  
The Fast Read instruction 0xC uses only one SPI data byte for a  
read operation. This is accomplished by using only first four bits for  
the SPI op-code and placing the first four most significant bits of the  
ARINC 717 word in the four remaining bit locations of what are  
normally part of an op-code. The remaining 8-bits of theARINC 717  
word are in a normal SPI data byte. This method use one less SPI  
data byte than a normal read instruction.  
There are also two bits in the Receive FIFO Status Register,  
RXFSTAT<6:5> that provide a realtime indicator when each of the  
four ARINC 717 subframe sync marks are received. The bits are  
valid only when INSYNC is “1” and are updated when the subframe  
sync word is loaded into the Receive FIFO.  
The final mode is No Synchronization, CRTL1<1> = “1”. In this  
mode data is captured and loaded directly to the Receive FIFO in  
the order it was received. It is the responsibility of the user to extract  
the data from the FIFO and determine word, frame and subframe  
boundaries. The INSYNC bit remains “0” while in this mode.  
Up to 32 ARINC 717 words may be held in the Receive FIFO. The  
RFFULL bit (RXFSTAT<4>) is set to “1” when the Receive FIFO is  
full. Failure to unload the Receive FIFOwhen full will result in loss of  
new data words until there are less than 32 words in the FIFO. The  
RFOVF bit (RXFSTAT<1>) and external FROV pin are set to “1”  
when an attemptis made towrite toa full Receive FIFO.  
Receive FIFOand Retrieving Data  
Data is transferred from the Receive FIFO starting with the valid  
subframe sync mark when INSYNC was set to “1” and continues  
with each consecutive 12-bit word until INSYNC is setto0”.  
The Receive FIFO half-full flag, the RFHALF bit (RXFSTAT<3), is  
set to “1” whenever the Receive FIFO contains exactly 16 words.  
The RFHALF bit provides a useful indicator to the host CPU that the  
FIFOis filling up.  
Each time a valid ARINC 717 word is loaded to the Receive FIFO  
the RFFULL, RFHALF and RFEMPTY bits in the Receive FIFO  
Status Register (RXFSTAT<4:2>) are updated. Each word is  
retrieved from the Receive FIFO via the SPI interface using SPI  
Op-code instruction 0xF6 (word only), 0xFE (word & word count) or  
0xC (FastRead).  
The Receive FIFO empty, the RFEMPTY bit (RXFSTAT<2>), is set  
to “1” when the Receive FIFO is empty. It is reset to “0” when there  
is atleast one word in the Receive FIFO.  
When the HI-3717 attempts to load a valid word to a full Receive  
FIF0, the RFOVF flag, RXFSTAT<1>, and the external RFOV pin  
are set to “1”. The Receive FIFO ignores any attempt to load any  
additional words if it is full. The RFOVF flag and RFOV pin are reset  
to0” when either the INSYNC goes to0” or the device is reset.  
The SPI read instruction 0xF6 format is an 8-bit op-code followed by  
two 8-bit data words. The four most significant bits (MSB) of the first  
data word are always “0” followed by the first four MSB of theARINC  
717 word. The second data word contains the remaining 8-bits of  
the ARINC 717 word. The least significant bit (LSB) of the ARINC  
717 word is the LSB ofthe second 8-bit data word.  
The external RFIFO pin is programmable in the FIFO Status Pin  
Assignment Register (FSPIN<7:6>) to reflect the value of the  
RFFULL, RFHALF or the RFEMPTY status bit. Refer to the FSPIN  
Register Description for the bit values that assign the RFFULL,  
RFHALF or RFEMPTY status bit to the RFIFO pin. The default  
stateis assignment ofthe RFEMPTYbit tothe RFIFOpin.  
The format for read word and word count instruction 0xFE is the  
same as the read instruction with the addition of two additional 8-bit  
data bytes that contain the word count and the corresponding sync  
subframe information. The third 8-bit SPI data byte contains the 8  
MSB bits of the word count. The fourth data byte is comprised of  
remaining 5 bits of the word count as well as the two bit code for the  
subframe number in the same format as described in the RFXSTAT  
Register Description. Refer to Example 5 in Figure 5 for more  
details on the formatforthis instruction.  
Word Count Utility Register, WRDCNT, is used to cause the external  
MATCH pin to be set to”1” when a specific word count is reached in a  
specific subframe. WRDCNT<15:3> specifies the location in the  
subframe and WRDCNT<1:0> specifies the subframe that is  
monitored. MATCH is “1” until the next word is loaded into the  
Receive FIFO.  
The Match word and subframe bit assignments of the Word Count  
Utility Register, WRDCNT, are found inTable 8.  
SYNC DETECTION  
INSYNC  
ONES  
NULL  
SHIFT REGISTER  
SHIFT REGISTER  
SHIFT REGISTER  
HBP  
DECODER  
12-BIT SERIAL  
12-BIT SERIAL  
REGISTER  
HBP / BPRZ  
SELECT  
INPUT REGISTER  
12-BIT COMPARATOR  
32 WORD x 12-BIT  
RECEIVE FIFO  
WORD  
CLOCK  
BPRZ  
WORD COUNT  
&
DECODER  
ZEROS  
SUBFRAME  
DETECTION  
12-BIT SERIAL  
to Line Drivers  
INPUT REGISTER  
DATA CLOCK  
DIVIDER  
RFIFO  
ROVF  
ACLK  
CTRL0<0>  
SYNC0  
SYNC1  
CTRL0<6:4>  
RSEL  
FIGURE 8. ARINC 717 Receiver Block Diagram  
HOLT INTEGRATED CIRCUITS  
13  
HI-3717  
FUNCTIONAL DESCRIPTION (cont.)  
mostsignificant bit ofthe op-code instruction is “0” rather than a “1”.  
TRANSMITTER  
Data Transmission  
The ARINC 717 transmission begins when the first word is loaded  
into the Transmit FIFO. Each word is serially fed to both the HBP  
and BPRZ encoders at the data rate programmed in Control  
Register 0, CNTL0<6:4>. The output of each encoder drives its  
own ARINC 717 analog line driver. The slew rate of both the HBP  
and the BPRZ auxiliary outputs is controllable with CNTL0<2:1>.  
Refer to the CTRL0 Register Description for the individual bit values  
required forsetting the desired data and output slew rate.  
FIFOOperation  
The HI-3717 Transmit FIFO is loaded with ARINC 717 words  
awaiting transmission. SPI words are written to the next Transmit  
FIFO location with op-code 0x74 or 0x2 (Fast Write). If Transmit  
FIFO Status Register empty flag, the TFEMPTY (TXFSTAT<5>) bit,  
is “1” (FIFO empty), then up to 32 ARINC 717 12-bit words can be  
safely loaded via the SPI interface. If the TFEMPTY bit is “0” then  
less than 32 positions are available. If all 32 positions are filled,  
then the full flag, the TFFULL(TXFSTAT<7>) bit, is “1”. All attempts  
to load the Transmit FIFO are ignored until the TFFULL bit is “0”  
which indicates thatatleast one word can be loaded.  
SYSTEMOPERATION  
The receiver and transmitter always operate at the same data rate.  
Otherwise, they operate completely independent of each other.  
The only restrictions are:  
The Transmit FIFO half-full flag, the TFHALF (TXFSTAT<6>) bit in  
the Transmit FIFO Status Register, is equal to “0” when there are  
less than or more than 16 ARINC 717 words in the Transmit FIFO  
and equal to “1” when there are exactly 16 words in the FIFO. The  
host CPU can safely load 16 ARINC 717 words into the Transmit  
FIFOonly whenTFHALFis “1”.  
1. The Receive FIFO ignores any attempt to load any additional  
words if it is full and at least one location is not retrieved  
before the next validARINC 717 is received.  
2. The Transmit FIFO can store a maximum of 32 words and  
ignores any attempttostore additional words when itis full.  
The state of the TFFULL or TFHALF is available on the external  
TFIFO pin, depending on the value in FSPIN<5> of the FIFO Status  
PinAssignment Register (SeeTable 7). The state ofTFEMPTYflag  
is always on the externalTEMPTYpin.  
DC/DC Converter  
The HI-3717 requires only a single +3.3V power supply. An  
integrated inverting / non-inverting voltage doubler generates the  
rail voltages (±5.7V) which then power the line drivers to produce  
the required +5VARINC 717 HBPand ±5VARINC 717 BPRZ signal  
levels.  
It is the user’s responsibility to load the correct subframe sync mark  
in the first word of each subframe and ensure the Transmit FIFO is  
not left empty for more than one word time for continuous transmis-  
sions.  
The internal dual-polarity charge pump requires four external  
capacitors, two for each polarity generated by the charge pump.  
The SPI format for writing anARINC 717 word and Fast Word to the  
HI-3717 Transmit FIFO is the same as the read format, except the  
TXHA  
TXHB  
TXOUTHA, OUTHA  
HBP  
HBP  
ENCODER  
LINE DRIVER  
SLEW RATE  
&
TXOUTHB, OUTHB  
12 BIT PARALLEL  
LOAD SHIFT REGISTER  
LOOPBACK  
TEST  
NOCONV  
CONTROL  
TXOUTBA, OUTBA  
TXOUTBB, OUTBB  
TXBA  
BPRZ  
BPRZ  
LINE DRIVER  
ENCODER  
TXBB  
BIT CLOCK  
WORD CLOCK  
&
WORD CLOCK  
BIT CLOCK  
START  
SEQUENCE  
32 word x 12 bit FIFO  
ADDRESS  
WORD COUNTER  
TFIFO  
&
FIFO CONTROL  
TEMPTY  
LOAD  
INCREMENT  
WORD COUNT  
FIFO  
LOADING  
SEQUENCER  
SCK  
CS  
SI  
SPI COMMANDS  
SPI COMMANDS  
DATA  
CLOCK  
SPI INTERFACE  
DATA CLOCK  
DIVIDER  
ACLK  
SO  
CTRL0<6:4>  
FIGURE 9. ARINC 717 Transmitter Block Diagram  
HOLT INTEGRATED CIRCUITS  
14  
HI-3717  
FUNCTIONAL DESCRIPTION (cont.)  
Line Receiver Input Pins  
Pins C1+ and C1- connect the external “fly” capacitor, CFLY, to the  
positive portion of the charge pump, resulting in 5.7V at the V+ pin  
that is generated by an on-board bandgap reference voltage. An  
output “hold” capacitor, COUT, is placed between V+ and GND.  
COUT should be ten times the size of CFLY. The inverting  
negative portion of the converter works in a similar fashion, with  
CFLY and COUT placed between C2+ / C2- and V- / GND  
respectively. Note that low ESR capacitors should be used.  
Recommended values are given in the block diagram on page 2.  
The HI-3717 has two sets of Line Receiver input pins that are  
shared with the HBP and BPRZ line receivers, RINA/B and  
RINA/B-40. Only one pair may be used to connect to the ARINC  
717 bus. The unused pair must be left floating. The RINA/B pins  
may be connected directly to the ARINC 717 bus.  
The RINA/B-40 pins require an external 40K ohm resistor in series  
with each ARINC 717 input. The resistors do not affect the ARINC  
717 receiver level detection thresholds .  
When using the RINA/B-40 pins, each side of the ARINC 717 bus  
must be connected through a 40K ohm series resistor in order for  
the chip to detect the correct ARINC 717 levels. The typical  
ARINC 717 differential signal is translated and input to a window  
comparator and latch. The comparator levels are set so that with  
the external 40K ohm resistors, they are just below the standard  
minimum data threshold and in the case of the auxiliary BPRZ  
line receiver, just above the standard 2.5 volt BPRZ (ARINC 429)  
null threshold.  
Line Driver Operation  
The line drivers in the HI-3717 directly drive the ARINC 717  
buses. The two ARINC 717 HBP outputs (TXOUTHA and  
TXOUTHB) provide a differential voltage of ±5V in accordance  
with the Harvard Bi-Phase format. Control Register  
(CTRL0<6:4) controls the transmitter data rate and  
CTRL0<<2:1> controls the output slew rate.  
0
The two auxillary ARINC 717 BPRZ outputs (TXOUTBA and  
TXOUTBB) provide a differential voltage to produce a +10V  
One, a -10V Zero, and a 0 Volt Null. The transmitter data rate is  
the same as the HBP output which is also controlled by the same  
bits in Control Register 0 (CTRL0<6:4). The slew rate of the  
differential output signal is also controlled by Control Register 0  
(CTRL0<2:1>. No additional hardware is required to control the  
slope. Slope rate is set by an on-chip resistors and capacitors.  
By keeping excessive voltage outside the device, the RINA/B-40  
input option is helpful in applications where lightning protection is  
required.  
Please refer to the Holt AN-300 Application Note for additional in-  
formation and recommendations on lightning protection of Holt  
line drivers and line receivers.  
Master Reset  
Line Driver Output Pins  
Application of a Master Reset with a 100ns active low pulse to the  
external MR pin sets all registers to their default values, places  
the Receive and Transmit FIFOs to their empty state, and clears  
the sync detection logic. It also sets both the HBP and BPRZ out-  
puts to the high impedance state and disables input sampling of  
both analog line receivers..  
The Harvard Bi-phase (HBP) TXOUTHA and TXOUTHB pins as  
well as the Bi-Polar Return to Zero (BPRZ) TXOUTBA and  
TXOUTBB pins have 37.5 Ohms in series with each line driver  
output, and may be directly connected to an ARINC 717 bus.  
The OUTHA, OUTHB, OUTBA and OUTBB pins have 5 Ohms of  
internal series resistance and require an external 32.5 ohm  
resistor in series with each pin. OUTHA, OUTHB, OUTBA and  
OUTBB pins are for applications where external series resis-  
tance is applied, typically for lightning protection devices.  
Software Reset  
A software reset is also possible via the SPI communications in-  
terface by writing a “1” to the CTRL1<3>. This bit places both the  
Receive and Transmit FIFO’s in the empty state, clears the sync  
detection logic, sets both the HBP and BPRZ line drivers to a high  
impedance state and disables the input sampling of both analog  
line receivers. Unlike POR and MR, ALL other registers remain  
unchanged. The device is held in the reset state until a “0” is writ-  
ten to CTRL1<3>.  
Either the TXOUTHA & TXOUTHB outputs or the OUTHA &  
OUTHB outputs are used in an application but not both sets at  
the same time. Likewise, only one set of the auxiliary BPRZ  
output pins (TXOUTBA & TXOUTBB or OUTBA & OUTBB) are  
used. Using both set of pins on either output will produce  
unpredictable results.  
The line driver outputs TXOUTHA, TXOUTHB, OUTHA, OUTHB,  
TXOUTBA, TXOUTBB, OUTBA & OUtBB are in a high imped-  
ance state after any reset and when in the digital loopback test  
mode (CTRL1<0> = “1”) allowing multiple line drivers to be  
connected to a single ARINC 717 bus. Note that both analog line  
receivers are also disconnected from the HBP and BPRZ input  
data samplers during reset and when in the digital loopback  
mode.  
No DC/DC Converter Option  
The NOCONV pin is set to “1” to disable the internal DC/DC Con-  
verter and supply +5V & -5V to the V+ & V- pins respectively from  
an external power source. The “fly” capacitor pins can be left  
floating.  
No Internal Line Drive Option  
The HI-3717 also has digital outputs from both the HBP (TXHA &  
TXHB) and the BPRZ (TXBA & TXBB) encoders allowing the use  
of external ARINC 717 line drivers. All four of these output pins  
are active all the time and reflect the digital data sent to the data  
sampler in the digital loopback mode.  
The HI-3717 can be used without the internal line drivers if only  
the ARINC 717 receive function is required or if the user wants to  
use his own external ARINC 717 line drivers connected to the  
TXAH, TXBH, TXAB & TXBB digital transmitter outputs. For this  
option, NOCONV pin is set to “1” to disable the internal line driv-  
ers, V+ is connected to VDD & V- is left unconnected.  
HOLT INTEGRATED CIRCUITS  
15  
HI-3717  
TIMING DIAGRAMS  
t CPH  
tCYC  
tCES  
tCES  
CS  
tCHH  
t SCKF  
t CEH  
SCK  
tDS  
SI  
tDH  
t SCKR  
MSB  
LSB  
FIGURE 10. SPI Serial Input Timing  
t CPH  
CS  
tCYC  
tSCKH  
tSCKL  
SCK  
SO  
t CHZ  
t DV  
MSB  
LSB  
Hi Impedance  
Hi Impedance  
FIGURE 11. SPI Serial Output Timing  
HBP DATA  
BPRZ DATA  
INSYNC  
12 Data Bits  
tREMPTY  
RFIFO (RFEMPTY)  
RFIFO (RFFULL)  
12 Data Bits  
ROVF  
tROVF  
FIGURE 12. Receive FIFO Flag Timing  
2nd to  
LAST TRANSMIT FIFO WORD  
LAST WORD  
Bit 10  
Bit 11  
Bit 1  
Bit 2  
Bit 3  
Bit 5  
Bit 6  
Bit 7  
Bit 9  
Bit 10  
Bit 11  
Bit 0  
Bit 4  
Bit 8  
HBP DATA  
BPRZ DATA  
tTEMPTY  
TEMPTY  
FIGURE 13. Transmit FIFO Empty Flag Timing  
HOLT INTEGRATED CIRCUITS  
16  
HI-3717  
TIMING DIAGRAMS (cont.)  
HBP BIT  
HBP BIT  
HBP BIT  
Data Bit 0  
Data Bit 1  
Data Bit 11  
+5V  
+5V  
+5V  
TXOUTHA & OUTHA  
TXOUTHB & OUTHB  
0V  
0V  
+5V  
+5V  
0V  
0V  
0V  
tfx  
trx  
+5V  
+5V  
+5V  
V
DIFF  
90%  
10%  
(TXOUTHA - TXOUTHB  
&
0V  
-5V  
-5V  
10%  
90%  
OUTHA - OUTHB)  
one level  
zero level  
FIGURE 14. Harvard Bi-Phase (HBP) Output Waveforms  
BPRZ BIT  
BPRZ BIT  
BPRZ BIT  
Data Bit 0  
Data Bit 1  
Data Bit 11  
+5V  
+5V  
TXOUTBA & OUTBA  
TXOUTBB & OUTBB  
-5V  
+5V  
-5V  
-5V  
tfx  
+10V  
+10V  
90%  
V
tfx  
trx  
DIFF  
10%  
(TXOUTBA - TXOUTBB  
&
10%  
trx  
OUTBA - OUTBB)  
90%  
one level  
zero level  
null level  
-10V  
FIGURE 15. Bi-Polar Return to Zero (BPRZ) Output Waveforms  
Data Bit 1  
Data Bit 0  
Data Bit 11  
HARVARD BI-PHASE (HBP)  
TXHA  
+3.3V  
+3.3V  
+3.3V  
90%  
90%  
10%  
0V  
0V  
tH1f 0%  
tHr  
+3.3V  
+3.3V  
TXHB  
0V  
0V  
0V  
BI-POLAR RETURN ZERO (BPRZ)  
TXBA  
+3.3V  
+3.3V  
90%  
10%  
90%  
10%  
0V  
0V  
+3.3V  
tBr  
t
Bf  
TXBB  
0V  
0V  
0V  
one level  
null level  
zero level  
FIGURE 16. Harvard Bi-Phase (HBP) & Bi-Polar Return to Zero (BPRZ) Logic Output Waveforms  
HOLT INTEGRATED CIRCUITS  
17  
HI-3717  
ABSOLUTE MAXIMUM RATINGS  
Power Dissipation at 25°C  
Supply Voltages VDD ......................................... -0.3V to +5.0V  
Plastic Quad Flat Pack ............... 1.5 W, derate 10mW/°C  
V+ ......................................................... +7.0V  
V- ......................................................... -7.0V  
DC Current Drain per digital input pin ........................... ±10mA  
Storage Temperature Range ........................ -65°C to +150°C  
Voltage at pins RINxx-xx .................................. -120V to +120V  
Voltage at pins TXAOUT, TXBOUT, AMPA, AMPB ......... V- to V+  
Voltage at any other pin ...............................-0.3V to VDD +0.3V  
Operating Temperature Range (Industrial): ..... -40°C to +85°C  
(Hi-Temp): ..... -55°C to +125°C  
Solder temperature (Leads) .................... 280°C for 10 seconds  
(Package) .......................................... 220°C  
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.  
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).  
LIMITS  
TYP  
PARAMETER  
SYMBOL  
CONDITIONS  
UNIT  
MIN  
MAX  
HARVARD BI-PHASE (HBP) INPUTS  
-
Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)  
HBPDifferential Input Voltage: (RINAtoRINB)  
HI  
LO  
VIHH  
VILH  
Common mode voltages less than  
±25V with respect toGND  
2.0  
-8.0  
5.0  
-5.0  
8.0  
-2.0.  
V
V
HBP Input Voltage (Ref. toDFDAU Signal Ground)  
HI  
LO  
HI  
VIHHA  
VILHA  
VIHHB  
VILHB  
3.5  
-1.5  
-1.5  
3.5  
5.0  
0
6.5  
+1.5  
+1.5  
6.5  
V
V
V
V
RINA  
RINB  
0
LO  
5.0  
BI-POLARRETURN TOZERO(BPRZ) INPUTS - PinsRINA, RINB, RINA-40 (withexternal 40KOhms), RINB-40 (withexternal 40KOhms)  
BPRZDifferential Input Voltage: (RINAtoRINB)  
ONE  
ZERO  
NULL  
VIHB  
VILB  
VINUL  
Common mode voltages less than  
±25V with respect toGND  
6.5  
-13.0  
-2.5  
10.0  
-10.0  
0
13.0  
-6.5  
+2.5  
V
V
V
BPRZInput Voltage (Ref. toDFDAU Signal Ground)  
ONE  
ZERO  
ONE  
VIHBA  
VILBA  
VIHBB  
VILBB  
3.25  
-6.5  
-6.5  
3.25  
5.0  
-5.0  
-5.0  
5.0  
6.5  
-3.25  
-3.25  
6.5  
V
V
V
V
RINA  
RINB  
ZERO  
HARVARD BI-PHASE (HBP) & BI-POLARRETURN TOZERO(BPRZ) INPUTS  
Input Resistance:  
Differential  
To GND  
To VDD  
RI  
RG  
RH  
-
-
-
140  
140  
100  
-
-
-
KΩ  
KΩ  
KΩ  
Input Current:  
Input Sink  
Input Source  
IIH  
IIL  
200  
µA  
µA  
-450  
Input Capacitance:  
(Guaranteed but not tested)  
Differential  
To GND  
To VDD  
CI  
CG  
CH  
(RINAtoRINB)  
20  
20  
20  
pF  
pF  
pF  
LOGICINPUTS  
Input Voltage:  
Input Voltage HI  
Input Voltage LO  
VIH  
VIL  
80% VDD  
-1.5  
V
V
20% VDD  
1.5  
Input Current:  
Input Sink  
Input Source  
Pull-down Current (MR, SI, SCK,ACLK pins)  
Pull-up current (CS pin)  
IIH  
IIL  
IPD  
IPU  
µA  
µA  
µA  
µA  
60  
-60  
HOLT INTEGRATED CIRCUITS  
18  
HI-3717  
DC ELECTRICAL CHARACTERISTICS (cont.)  
VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).  
LIMITS  
TYP  
PARAMETER  
SYMBOL  
CONDITIONS  
UNIT  
MIN  
MAX  
HARVARD BI-PHASE (HBP) OUTPUTS-PinsTXOUTHA, TXOUTHB, (orOUTHA, OUTHB withexternal 32.5 Ohms)  
HBP output voltage (Differential)  
HI  
VOHH  
VOLH  
600 ohm load  
600 ohm load  
4.0  
5.0  
6.0  
V
V
(TXOUTHA to TXOUTHB or OUTHA to OUTHB)  
LO  
-6.0  
-5.0  
-4.0  
HBP output voltage (Ref to GND)  
HI  
LO  
HI  
VOHHA  
VOLHA  
VOHHB  
VOLHB  
4.5  
-0.5  
-0.5  
4.5  
5.0  
0
5.5  
+0.5  
+0.5  
5.5  
V
V
V
V
TXOUTHA or OUTHA  
TXOUTHB or OUTHB  
0
LO  
5.0  
BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS - Pins TXOUTBA, TXOUTBB, (or OUTBA, OUTBB with external 32.5 Ohms)  
BPRZ output voltage (Differential)  
(TXOUTBAto TXOUTBB or OUTBA to OUTBB)  
ONE  
ZERO  
NULL  
VOHB  
VOLB  
No load  
9.0  
-11.0  
-0.5  
10.0  
-10.0  
0
11.0  
-9.0  
+0.5  
V
V
V
VONUL  
BPRZ output voltage (Ref to GND)  
TXOUTBAor OUTBA  
ONE  
ZERO  
ONE  
VOHBA  
VOLBA  
VOHBB  
VOLBB  
No load  
4.5  
-5.5  
-5.5  
4.5  
5.0  
-5.0  
-5.0  
5.0  
5.5  
-4.5  
-4.5  
5.5  
V
V
V
V
TXOUTBB or OUTBB  
ZERO  
HARVARD BI-PHASE (HBP) and BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS  
Output current  
IOUT  
Momentary short-circuit current  
80  
mA  
LOGIC OUTPUTS (Including TXHA, TXHB, TXBA & TXBB)  
Output Voltage:  
Logic "1" Output Voltage  
Logic "0" Output Voltage  
VOH  
VOL  
IOH = -100µA  
IOL = 1.0mA  
90%VDD  
1.6  
V
V
10% VDD  
-1.0  
Output Current:  
Output Sink  
Output Source  
IOL  
IOH  
VOUT = 0.4V  
VOUT = VDD - 0.4V  
mA  
mA  
Output Capacitance:  
CO  
15  
pF  
OPERATING VOLTAGE RANGE  
VDD  
3.15  
3.45  
V
OPERATING SUPPLY CURRENT  
Transmitting Data at 8192 words/sec.  
Transmitting Data in 8192 words/sec.  
IDD  
Outputs Unloaded  
35  
mA  
mA  
IDDL  
600 Ohm Differential Output Load HBP  
400 Ohm Differential Output Load BPRZ  
120  
HOLT INTEGRATED CIRCUITS  
19  
HI-3717  
AC ELECTRICAL CHARACTERISTICS  
VDD = 3.3V, TA = Operating Temperature Range and ACLK=24MHz +0.1%  
LIMITS  
TYP  
PARAMETER  
SYMBOL  
UNITS  
MIN  
MAX  
SPI INTERFACE TIMING  
SCK clock period  
CS active after last SCK rising edge  
CS setup time to first SCK rising edge  
CS hold time after last SCK falling edge  
CS inactive between SPI instructions  
SPI SI Data set-up time to SCK rising edge  
SPI SI Data hold time after SCK rising edge  
SCK rise time  
tCYC  
tCHH  
tCES  
tCEH  
tCPH  
tDS  
100  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5
55  
10  
10  
tDH  
tSCKR  
tSCKF  
tSCKH  
tSCKL  
tDV  
10  
10  
SCK fall ime  
SCK pulse width high  
SCK pulse width low  
20  
25  
SO valid after SCK falling edge  
SO high-impedance after SCK falling edge  
MR pulse width  
35  
30  
tCHZ  
tMR  
40  
RECEIVER TIMING  
Delay - INSYNC high to REMPTY low (plus 12 data bits)  
Delay - RFFULL high to ROVF high (plus 12 data bits)  
tREMPTY  
tROVF  
100  
100  
ns  
ns  
TRANSMITTER TIMING  
TFEMPY flag high to beginningt of first data bit of last word in Transmit FIFO  
32 words / sec.  
64 words / sec.  
tTEMPTY (32 wps)  
tTEMPTY (64 wps)  
tTEMPTY (128 wps)  
tTEMPTY (256 wps)  
tTEMPTY (512 wps)  
tTEMPTY (1024 wps)  
tTEMPTY (2048 wps)  
tTEMPTY (4096 wps)  
tTEMPTY (8192 wps)  
2604  
1302  
651  
326  
163  
81.4  
41.7  
20.4  
10.2  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
128 words / sec.  
256 words / sec.  
512 words / sec.  
1024 words / sec.  
2048 words / sec.  
4094 words / sec.  
8192 words / sec.  
Line driver transition differential times (Both the Harvard Bi-Phase and Bi-Polar Return to Zero are set to the same slew rate)  
CNTL0<2:1> = 00  
high to low  
low to high  
high to low  
low to high  
high to low  
low to high  
tfx  
trx  
tfx  
trx  
tfx  
trx  
5.0  
5.0  
5.0  
5.0  
1.0  
1.0  
7.5  
7.5  
10  
10  
1.5  
1.5  
10  
10  
15  
15  
2.0  
2.0  
µs  
µs  
µs  
µs  
µs  
µs  
CNTL0<2:1> = 01 or 10  
CNTL0<2:1> = 11  
Transmitter digital outputs transition times  
Harvard Bi-Phase (HBP)  
high to low  
low to high  
high to low  
low to high  
tHf  
tHr  
tBf  
tBr  
3.0  
3.0  
3.0  
3.0  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
ns  
ns  
Bi-Polar Return to Zero (BPRZ)  
HOLT INTEGRATED CIRCUITS  
20  
HI-3717  
HEAT SINK - CHIP-SCALE PACKAGE ONLY  
The HI-3717PCx uses a 44-pin plastic chip-scale package.  
This package has a metal heat sink pad on its bottom  
surface. This heat sink is electrically isolated from the die.  
To enhance thermal dissipation, the heat sink can be  
soldered to matching circuit board pad.  
ORDERING INFORMATION  
HI - 3717 xx x x  
PART  
LEAD  
NUMBER  
FINISH  
Tin / Lead (Sn / Pb) Solder  
100% Matte Tin (Pb-free, RoHS compliant)  
Blank  
F
PART  
TEMPERATURE  
RANGE  
BURN  
IN  
NUMBER  
FLOW  
I
-40°C TO +85°C  
-55°C TO +125°C  
-55°C TO +125°C  
I
No  
No  
T
M
T
M
Yes  
PART  
PACKAGE  
NUMBER  
DESCRIPTION  
PC  
PQ  
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)  
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)  
HOLT INTEGRATED CIRCUITS  
21  
HI-3717  
REVISION HISTORY  
P/N  
Rev  
Date  
Description of Change  
DS3717 NEW 08/11/11 Initial Release  
DS3717  
Ds3717  
A
B
08/23/11 Corrected typographical errors. Deleted QFN power dissipation reference.  
11/4/11  
Updated SPI to 10MHz, added IDD limits, corrected example typographical error.  
HOLT INTEGRATED CIRCUITS  
22  
HI-3717 PACKAGE DIMENSIONS  
inches (millimeters)  
Package Type: 44PCS  
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)  
.276  
BSC  
.203 ± .006  
(5.15 ± .15)  
(7.00)  
.020  
BSC  
typ  
(0.50)  
.276  
(7.00)  
.203 ± .006  
(5.15 ± .15)  
Top View  
Bottom  
View  
BSC  
.010  
(0.25)  
.016 ± .002  
(0.40 ± .05)  
.039  
(1.00)  
.008  
(0.2)  
max  
typ  
BSC = “Basic Spacing between Centers”  
is theoretical true position dimension and  
has no tolerance. (JEDEC Standard 95)  
inches (millimeters)  
44-PIN PLASTIC QUAD FLAT PACK (PQFP)  
Package Type:  
44PTQS  
.006  
(.15)  
MAX.  
.0315  
(.80)  
BSC  
.547 ± .010  
(13.90 ± .25)  
SQ.  
.394 ± .004  
(10.0 ± .10)  
SQ.  
.014 ± ..002  
(.35 ± .05)  
.035 ± .006  
(.88 ± .15)  
.012  
(.30)  
R MAX.  
See Detail A  
.055 ± .002  
(1.4 ± .05)  
.063  
(1.6)  
MAX.  
0°< Θ < 7°  
.005  
(.13)  
R MIN.  
Detail A  
BSC = “Basic Spacing between Centers”  
is theoretical true position dimension and  
has no tolerance. (JEDEC Standard 95)  
HOLT INTEGRATED CIRCUITS  
23  
配单直通车
HI-3717PQI产品参数
型号:HI-3717PQI
是否Rohs认证:不符合
生命周期:Active
IHS 制造商:HOLT INTEGRATED CIRCUITS INC
零件包装代码:QFP
包装说明:LQFP,
针数:44
Reach Compliance Code:compliant
ECCN代码:7A994
HTS代码:8542.39.00.01
风险等级:5.6
Is Samacsys:N
地址总线宽度:
边界扫描:NO
最大时钟频率:24.024 MHz
通信协议:SYNC, BYTE
最大数据传输速率:0.01171875 MBps
外部数据总线宽度:
JESD-30 代码:S-PQFP-G44
JESD-609代码:e0
长度:10 mm
低功率模式:NO
湿度敏感等级:3
串行 I/O 数:1
端子数量:44
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:LQFP
封装形状:SQUARE
封装形式:FLATPACK
峰值回流温度(摄氏度):240
认证状态:Not Qualified
座面最大高度:1.6 mm
最大供电电压:3.45 V
最小供电电压:3.15 V
标称供电电压:3.3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:TIN LEAD
端子形式:GULL WING
端子节距:0.8 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:30
宽度:10 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL
Base Number Matches:1
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