HI-3717
FUNCTIONAL DESCRIPTION (cont.)
Line Receiver Input Pins
Pins C1+ and C1- connect the external “fly” capacitor, CFLY, to the
positive portion of the charge pump, resulting in 5.7V at the V+ pin
that is generated by an on-board bandgap reference voltage. An
output “hold” capacitor, COUT, is placed between V+ and GND.
COUT should be ten times the size of CFLY. The inverting
negative portion of the converter works in a similar fashion, with
CFLY and COUT placed between C2+ / C2- and V- / GND
respectively. Note that low ESR capacitors should be used.
Recommended values are given in the block diagram on page 2.
The HI-3717 has two sets of Line Receiver input pins that are
shared with the HBP and BPRZ line receivers, RINA/B and
RINA/B-40. Only one pair may be used to connect to the ARINC
717 bus. The unused pair must be left floating. The RINA/B pins
may be connected directly to the ARINC 717 bus.
The RINA/B-40 pins require an external 40K ohm resistor in series
with each ARINC 717 input. The resistors do not affect the ARINC
717 receiver level detection thresholds .
When using the RINA/B-40 pins, each side of the ARINC 717 bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC 717 levels. The typical
ARINC 717 differential signal is translated and input to a window
comparator and latch. The comparator levels are set so that with
the external 40K ohm resistors, they are just below the standard
minimum data threshold and in the case of the auxiliary BPRZ
line receiver, just above the standard 2.5 volt BPRZ (ARINC 429)
null threshold.
Line Driver Operation
The line drivers in the HI-3717 directly drive the ARINC 717
buses. The two ARINC 717 HBP outputs (TXOUTHA and
TXOUTHB) provide a differential voltage of ±5V in accordance
with the Harvard Bi-Phase format. Control Register
(CTRL0<6:4) controls the transmitter data rate and
CTRL0<<2:1> controls the output slew rate.
0
The two auxillary ARINC 717 BPRZ outputs (TXOUTBA and
TXOUTBB) provide a differential voltage to produce a +10V
One, a -10V Zero, and a 0 Volt Null. The transmitter data rate is
the same as the HBP output which is also controlled by the same
bits in Control Register 0 (CTRL0<6:4). The slew rate of the
differential output signal is also controlled by Control Register 0
(CTRL0<2:1>. No additional hardware is required to control the
slope. Slope rate is set by an on-chip resistors and capacitors.
By keeping excessive voltage outside the device, the RINA/B-40
input option is helpful in applications where lightning protection is
required.
Please refer to the Holt AN-300 Application Note for additional in-
formation and recommendations on lightning protection of Holt
line drivers and line receivers.
Master Reset
Line Driver Output Pins
Application of a Master Reset with a 100ns active low pulse to the
external MR pin sets all registers to their default values, places
the Receive and Transmit FIFOs to their empty state, and clears
the sync detection logic. It also sets both the HBP and BPRZ out-
puts to the high impedance state and disables input sampling of
both analog line receivers..
The Harvard Bi-phase (HBP) TXOUTHA and TXOUTHB pins as
well as the Bi-Polar Return to Zero (BPRZ) TXOUTBA and
TXOUTBB pins have 37.5 Ohms in series with each line driver
output, and may be directly connected to an ARINC 717 bus.
The OUTHA, OUTHB, OUTBA and OUTBB pins have 5 Ohms of
internal series resistance and require an external 32.5 ohm
resistor in series with each pin. OUTHA, OUTHB, OUTBA and
OUTBB pins are for applications where external series resis-
tance is applied, typically for lightning protection devices.
Software Reset
A software reset is also possible via the SPI communications in-
terface by writing a “1” to the CTRL1<3>. This bit places both the
Receive and Transmit FIFO’s in the empty state, clears the sync
detection logic, sets both the HBP and BPRZ line drivers to a high
impedance state and disables the input sampling of both analog
line receivers. Unlike POR and MR, ALL other registers remain
unchanged. The device is held in the reset state until a “0” is writ-
ten to CTRL1<3>.
Either the TXOUTHA & TXOUTHB outputs or the OUTHA &
OUTHB outputs are used in an application but not both sets at
the same time. Likewise, only one set of the auxiliary BPRZ
output pins (TXOUTBA & TXOUTBB or OUTBA & OUTBB) are
used. Using both set of pins on either output will produce
unpredictable results.
The line driver outputs TXOUTHA, TXOUTHB, OUTHA, OUTHB,
TXOUTBA, TXOUTBB, OUTBA & OUtBB are in a high imped-
ance state after any reset and when in the digital loopback test
mode (CTRL1<0> = “1”) allowing multiple line drivers to be
connected to a single ARINC 717 bus. Note that both analog line
receivers are also disconnected from the HBP and BPRZ input
data samplers during reset and when in the digital loopback
mode.
No DC/DC Converter Option
The NOCONV pin is set to “1” to disable the internal DC/DC Con-
verter and supply +5V & -5V to the V+ & V- pins respectively from
an external power source. The “fly” capacitor pins can be left
floating.
No Internal Line Drive Option
The HI-3717 also has digital outputs from both the HBP (TXHA &
TXHB) and the BPRZ (TXBA & TXBB) encoders allowing the use
of external ARINC 717 line drivers. All four of these output pins
are active all the time and reflect the digital data sent to the data
sampler in the digital loopback mode.
The HI-3717 can be used without the internal line drivers if only
the ARINC 717 receive function is required or if the user wants to
use his own external ARINC 717 line drivers connected to the
TXAH, TXBH, TXAB & TXBB digital transmitter outputs. For this
option, NOCONV pin is set to “1” to disable the internal line driv-
ers, V+ is connected to VDD & V- is left unconnected.
HOLT INTEGRATED CIRCUITS
15