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  • HI5760BIB图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • HI5760BIB
  • 数量65000 
  • 厂家INTERSIL 
  • 封装SOP-28 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • HI5760BIB图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • HI5760BIB
  • 数量98500 
  • 厂家INTERSIL 
  • 封装原厂封装 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • HI5760BIBZ图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • HI5760BIBZ
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • HI5760BIB图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • HI5760BIB
  • 数量4026 
  • 厂家INTERSIL 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • HI5760BIB图
  • 集好芯城

     该会员已使用本站13年以上
  • HI5760BIB
  • 数量13238 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • HI5760BIBZ-T图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • HI5760BIBZ-T
  • 数量11530 
  • 厂家Intersil 
  • 封装28-SOIC(7.5mm寬) 
  • 批号23+ 
  • 全新原装现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • HI5760BIBZ-T图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • HI5760BIBZ-T
  • 数量15735 
  • 厂家Intersil 
  • 封装28-SOIC(7.5mm寬) 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • HI5760BIB图
  • 深圳市雅维特电子有限公司

     该会员已使用本站15年以上
  • HI5760BIB
  • 数量5000 
  • 厂家INTERSIL 
  • 封装深圳原装现货0755-83975781 
  • 批号原厂原装 
  • QQ:767621813QQ:767621813 复制
    QQ:1152937841QQ:1152937841 复制
  • 0755-83975781 QQ:767621813QQ:1152937841
  • HI5760BIBZ图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • HI5760BIBZ
  • 数量2015 
  • 厂家INTERSIL 
  • 封装SOP/DIP 
  • 批号19889 
  • ★一级代理原装现货,特价热卖!
  • QQ:2752732883QQ:2752732883 复制
    QQ:240616963QQ:240616963 复制
  • 0755-25165869 QQ:2752732883QQ:240616963
  • HI5760BIB图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • HI5760BIB
  • 数量57639 
  • 厂家INTERSIL 
  • 封装7.2mm28 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • HI5760BIB-T图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • HI5760BIB-T
  • 数量4800 
  • 厂家Intersil 
  • 封装卓一原装现货供应 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • HI5760BIB图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • HI5760BIB
  • 数量15000 
  • 厂家INTERSIL 
  • 封装SOP 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • HI5760BIBZ图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • HI5760BIBZ
  • 数量5000 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号16+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62106431 QQ:857273081QQ:1594462451
  • HI5760BIB图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • HI5760BIB
  • 数量936 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507165QQ:2355507165 复制
    QQ:2355507162QQ:2355507162 复制
  • 86-0755-83210909 QQ:2355507165QQ:2355507162
  • HI5760BIBZ图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • HI5760BIBZ
  • 数量6328 
  • 厂家RENESAS-瑞萨. 
  • 封装SOP-28 
  • 批号▉▉:2年内 
  • ▉▉¥62.5元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • HI5760BIB图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • HI5760BIB
  • 数量13500 
  • 厂家TI 
  • 封装 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • HI5760BIB图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • HI5760BIB
  • 数量3200 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供货
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • HI5760BIB图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • HI5760BIB
  • 数量9000 
  • 厂家INTERSIL 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
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    QQ:2300949663QQ:2300949663 复制
  • 15821228847 QQ:2719079875QQ:2300949663
  • HI5760BIBZ图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • HI5760BIBZ
  • 数量65400 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号NEW 
  • 【◆全新原装现货◆绝对价格优势◆质量保证◆】
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • HI5760BIB图
  • 宇芯通实业(深圳)有限公司

     该会员已使用本站8年以上
  • HI5760BIB
  • 数量10000 
  • 厂家RENESAS/INTERSIL 
  • 封装10位,125/60MHz,高速D/A转换器 
  • 批号20+ 
  • 只做品牌原装假一赔十
  • QQ:2903107741QQ:2903107741 复制
  • 0755-84535756 QQ:2903107741
  • HI5760BIB图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • HI5760BIB
  • 数量3645 
  • 厂家INTERSIL 
  • 封装SOP-28 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • HI5760BIB图
  • 深圳市中福国际管理有限公司

     该会员已使用本站1年以上
  • HI5760BIB
  • 数量21000 
  • 厂家Renesas Electronics America Inc 
  • 封装28-SOIC 
  • 批号22+ 
  • 大量现货库存,2小时内发货
  • QQ:1664127491QQ:1664127491 复制
    QQ:2115067904QQ:2115067904 复制
  • 0755-82571134 QQ:1664127491QQ:2115067904
  • HI5760BIB图
  • 深圳市励创源科技有限公司

     该会员已使用本站2年以上
  • HI5760BIB
  • 数量35600 
  • 厂家INTERSIL 
  • 封装SOP-28 
  • 批号21+ 
  • 诚信经营,原装现货,假一赔十,欢迎咨询15323859243
  • QQ:815442201QQ:815442201 复制
    QQ:483601579QQ:483601579 复制
  • -0755-82711370 QQ:815442201QQ:483601579
  • HI5760BIBZ图
  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • HI5760BIBZ
  • 数量20000 
  • 厂家INTERSIL 
  • 封装SOP28 
  • 批号23+ 
  • 原装现货热卖!请联系吴先生 13681678667
  • QQ:617677003QQ:617677003 复制
  • 15618836863 QQ:617677003
  • HI5760BIB图
  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • HI5760BIB
  • 数量16680 
  • 厂家INTERSIL 
  • 封装SOP 
  • 批号16+ 
  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
  • QQ:799387964QQ:799387964 复制
    QQ:2777237833QQ:2777237833 复制
  • 0755-82566711 QQ:799387964QQ:2777237833
  • HI5760BIB图
  • 深圳市顺鑫诚电子科技有限公司

     该会员已使用本站14年以上
  • HI5760BIB
  • 数量5000 
  • 厂家INTELRSIL 
  • 封装SOIC 
  • 批号18+ 
  • 保证原装正品,欢迎来电咨询
  • QQ:1533095505QQ:1533095505 复制
    QQ:449551876QQ:449551876 复制
  • 0755-29486608 QQ:1533095505QQ:449551876
  • HI5760BIB图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • HI5760BIB
  • 数量660000 
  • 厂家RENESAS(瑞萨电子) 
  • 封装SOIC-28 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • HI5760BIB图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • HI5760BIB
  • 数量6600 
  • 厂家RENESAS/瑞萨 
  • 封装28SOIC 
  • 批号20+ 
  • 原盒原装原标签,市场最低价。
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
  • HI5760BIB图
  • 深圳德田科技有限公司

     该会员已使用本站7年以上
  • HI5760BIB
  • 数量
  • 厂家新年份 
  • 封装9600 
  • 批号 
  • 原装正品现货,可出样品!!!
  • QQ:229754250QQ:229754250 复制
  • 0755-83254070 QQ:229754250
  • HI5760BIB图
  • 深圳市捷立辉科技有限公司

     该会员已使用本站10年以上
  • HI5760BIB
  • 数量29686 
  • 厂家INTERSIL 
  • 封装SOIC-48 
  • 批号21+ 
  • 进口原装现货,公司真实库存ON代理渠道
  • QQ:1803576909QQ:1803576909 复制
  • -0755-82792948 QQ:1803576909

产品型号HI5760BIB的概述

芯片HI5760BIB的概述 HI5760BIB是一款高性能、低功耗的数字信号处理器,广泛应用于音频、视频及信号处理项目中。随着科技的发展,数字信号处理器在各种电子设备中发挥着越来越重要的作用。HI5760BIB以其良好的处理能力和高效的能耗管理成为业内备受关注的产品之一。 HI5760BIB主要设计用于处理高频信号,其架构旨在实现高速信号处理,并获得优异的信号完整性。产品通常集成多种功能,包括模拟信号转换、数字信号处理以及滤波等,适合用于多种复杂应用场合。 芯片HI5760BIB的详细参数 HI5760BIB的参数包含多个关键特性,例如其工作电压、功耗、处理速度等。这些参数对于设计人员在选择合适的芯片时具有重要价值。 1. 工作电压: HI5760BIB的工作电压范围通常在1.8V到3.3V之间,便于在多种电子设备中应用。 2. 功耗: 该芯片采用先进的工艺,功耗较低,能够在保持高性...

产品型号HI5760BIB的Datasheet PDF文件预览

HI5760  
Data Sheet  
November 1999  
File Number 4320.5  
10-Bit, 125/60MSPS, High Speed D/A  
Converter  
Features  
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS  
• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V  
• Power Down Mode . . . . . . . . . . 23mW at 5V, 10mW at 3V  
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . ±1 LSB  
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA  
• SFDR to Nyquist at 5MHz Output . . . . . . . . . . . . . .68dBc  
The HI5760 is a 10-bit, 125MSPS, high speed, low power,  
D/A converter which is implemented in an advanced CMOS  
process. Operating from a single +3V to +5V supply, the  
converter provides 20mA of full scale output current and  
includes edge-triggered CMOS input data latches. Low glitch  
energy and excellent frequency domain performance are  
achieved using a segmented current source architecture. For  
an equivalent performance dual version, see the HI5728.  
• Internal 1.2V Temperature Compensated Bandgap  
Voltage Reference  
This device complements the CommLink™ HI5X60 family of  
high speed converters offered by Intersil, which includes 8,  
10, 12, and 14-bit devices.  
• Single Power Supply from +5V to +3V  
• CMOS Compatible Inputs  
Ordering Information  
• Excellent Spurious Free Dynamic Range  
PART  
NUMBER  
TEMP.  
RANGE ( C) PACKAGE  
PKG.  
NO.  
CLOCK  
SPEED  
o
Applications  
HI5760BIB  
HI5760IA  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
25  
28 Ld SOIC  
M28.3  
125MHz  
• Cable Modems  
28 Ld TSSOP M28.173 125MHz  
28 Ld SOIC M28.3 60MHz  
28 Ld TSSOP M28.173 60MHz  
Evaluation Platform 125MHz  
• Set Top Boxes  
HI5760/6IB†  
HI5760/6IA†  
HI5760EVAL1  
• Wireless Communications  
• Direct Digital Frequency Synthesis  
• Signal Reconstruction  
Test Instrumentation  
Contact factory for availability.  
• High Resolution Imaging Systems  
• Arbitrary Waveform Generators  
Pinout  
HI5760 (SOIC, TSSOP)  
TOP VIEW  
D9 (MSB)  
D8  
1
2
3
4
5
6
7
8
9
CLK  
28  
27 DV  
DD  
26 DCOM  
25 NC  
D7  
D6  
D5  
24 AV  
DD  
D4  
23 NC  
D3  
22 IOUTA  
21 IOUTB  
D2  
D1  
20  
ACOM  
D0 (LSB) 10  
NC 11  
19 COMP1  
18 FSADJ  
17 REFIO  
16 REFLO  
15 SLEEP  
NC 12  
NC 13  
NC 14  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
CommLink™ is a trademark of Intersil Corporation.  
1
HI5760  
Typical Applications Circuit  
HI5760  
NC  
(11-14, 25)  
(15) SLEEP  
(16) REFLO  
DCOM  
ACOM  
D9 (MSB) (1)  
D8 (2)  
D9  
(17) REFIO  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
0.1µF  
D7 (3)  
D6 (4)  
(18) FSADJ  
(22) IOUTA  
D5 (5)  
R
SET  
2kΩ  
D4 (6)  
D3 (7)  
D/A OUT  
50Ω  
50Ω  
D2 (8)  
D1 (9)  
D0 (LSB) (10)  
D0  
(21) IOUTB  
D/A OUT  
CLK (28)  
(23) NC  
50Ω  
(19) COMP1  
DCOM (26)  
0.1µF  
(20) ACOM  
FERRITE  
BEAD  
FERRITE  
BEAD  
+5V OR +3V (V  
)
DD  
(24) AV  
DD  
DV  
DD  
(27)  
+
+
10µH  
10µH  
10µF  
10µF  
0.1µF  
0.1µF  
Functional Block Diagram  
IOUTA IOUTB  
(LSB) D0  
D1  
CASCODE  
CURRENT  
SOURCE  
D2  
D3  
5 LSBs  
+
36  
36  
D4  
SWITCH  
MATRIX  
LATCH  
LATCH  
31 MSB  
D5  
D6  
SEGMENTS  
UPPER  
5-BIT  
31  
D7  
DECODER  
D8  
(MSB) D9  
COMP1  
CLK  
INT/EXT  
VOLTAGE  
REFERENCE  
BIAS  
GENERATION  
INT/EXT  
REFERENCE  
SELECT  
FSADJ  
SLEEP  
AV  
ACOM DV  
DD  
DCOM  
REFLO  
REFIO  
DD  
2
HI5760  
Absolute Maximum Ratings  
Thermal Information  
o
Digital Supply Voltage DV  
DD  
to DCOM . . . . . . . . . . . . . . . . . . +5.5V  
to ACOM. . . . . . . . . . . . . . . . . . +5.5V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
JA  
Analog Supply Voltage AV  
DD  
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature  
70  
117  
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V  
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DV + 0.3V  
DD  
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . ±50µA  
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV + 0.3V  
o
HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C  
o
o
DD  
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA  
o
Analog Output Current (I  
OUT  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
o
Electrical Specifications  
AV  
DD  
= DV  
DD  
= +5V, V  
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values  
A
REF  
HI5760  
= -40 C TO 85 C  
o
o
T
A
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
10  
-1  
-
-
+1  
Bits  
LSB  
Integral Linearity Error, INL  
Differential Linearity Error, DNL  
“Best Fit” Straight Line (Note 7)  
±0.5  
±0.25  
(Note 7)  
(Note 7)  
(Note 7)  
-0.5  
-0.025  
-
+0.5  
+0.025  
-
LSB  
Offset Error, I  
% FSR  
ppm  
OS  
Offset Drift Coefficient  
0.1  
o
FSR/ C  
Full Scale Gain Error, FSE  
With External Reference (Notes 2, 7)  
With Internal Reference (Notes 2, 7)  
With External Reference (Note 7)  
-10  
-10  
-
±2  
±1  
+10  
+10  
-
% FSR  
% FSR  
ppm  
Full Scale Gain Drift  
±50  
o
FSR/ C  
With Internal Reference (Note 7)  
(Note 3)  
-
±100  
-
ppm  
FSR/ C  
o
Full Scale Output Current, I  
2
-
-
20  
mA  
V
FS  
Output Voltage Compliance Range  
-0.3  
1.25  
DYNAMIC CHARACTERISTICS  
Maximum Clock Rate, f  
Output Settling Time, (t  
(Note 3)  
125  
-
-
-
-
-
-
-
-
-
-
MHz  
ns  
CLK  
)
0.2% (±1 LSB, equivalent to 9 Bits) (Note 7)  
0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7)  
-
-
-
-
-
-
-
-
20  
35  
5
SETT  
ns  
Singlet Glitch Area (Peak Glitch)  
Output Rise Time  
R
= 25(Note 7)  
pV•s  
ns  
L
Full Scale Step  
Full Scale Step  
1.0  
1.5  
10  
50  
30  
Output Fall Time  
ns  
Output Capacitance  
Output Noise  
pF  
IOUTFS = 20mA  
IOUTFS = 2mA  
pA/Hz  
pA/Hz  
3
HI5760  
o
Electrical Specifications  
PARAMETER  
AV  
DD  
= DV  
DD  
= +5V, V  
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)  
REF  
A
HI5760  
= -40 C TO 85 C  
o
o
T
A
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz  
Spurious Free Dynamic Range,  
SFDR Within a Window  
f
= 125MSPS, f  
= 100MSPS, f  
= 32.9MHz, 10MHz Span (Notes 4, 7)  
= 5.04MHz, 4MHz Span (Notes 4, 7)  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75  
76  
75  
76  
78  
71  
71  
76  
54  
64  
52  
60  
68  
74  
63  
55  
68  
73  
73  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
CLK  
OUT  
f
CLK  
OUT  
f
= 60MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 10.1MHz, 10MHz Span (Notes 4, 7)  
= 5.02MHz, 2MHz Span (Notes 4, 7)  
= 1.00MHz, 2MHz Span (Notes 4, 7)  
CLK  
OUT  
OUT  
OUT  
f
CLK  
f
CLK  
Total Harmonic Distortion (THD) to  
Nyquist  
f
f
f
= 100MSPS, f  
= 2.00MHz (Notes 4, 7)  
OUT  
CLK  
CLK  
CLK  
= 50MSPS, f  
= 50MSPS, f  
= 2.00MHz (Notes 4, 7)  
OUT  
OUT  
= 1.00MHz (Notes 4, 7)  
Spurious Free Dynamic Range,  
SFDR to Nyquist  
f
= 125MSPS, f  
= 125MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 100MSPS, f  
= 32.9MHz, 62.5MHz Span (Notes 4, 7)  
= 10.1MHz, 62.5MHz Span (Notes 4, 7)  
= 40.4MHz, 50MHz Span (Notes 4, 7)  
= 20.2MHz, 50MHz Span (Notes 4, 7)  
= 5.04MHz, 50MHz Span (Notes 4, 7)  
= 2.51MHz, 50MHz Span (Notes 4, 7)  
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
f
= 60MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 10.1MHz, 30MHz Span (Notes 4, 7)  
= 20.2MHz, 25MHz Span (Notes 4, 7)  
= 5.02MHz, 25MHz Span (Notes 4, 7)  
= 2.51MHz, 25MHz Span (Notes 4, 7)  
= 1.00MHz, 25MHz Span (Notes 4, 7)  
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz  
Spurious Free Dynamic Range,  
SFDR Within a Window  
f
= 60MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 10.1MHz, 10MHz Span (Notes 4, 7)  
= 5.02MHz, 2MHz Span (Notes 4, 7)  
= 1.00MHz, 2MHz Span (Notes 4, 7)  
-
-
-
-
-
-
-
-
-
-
-
-
75  
76  
78  
71  
76  
56  
63  
55  
68  
73  
73  
71  
-
-
-
-
-
-
-
-
-
-
-
-
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
CLK  
OUT  
OUT  
OUT  
f
CLK  
f
CLK  
Total Harmonic Distortion (THD) to  
Nyquist  
f
f
= 50MSPS, f  
= 50MSPS, f  
= 2.00MHz (Notes 4, 7)  
= 1.00MHz (Notes 4, 7)  
CLK  
CLK  
OUT  
OUT  
Spurious Free Dynamic Range,  
SFDR to Nyquist  
f
= 60MSPS, f  
= 60MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 50MSPS, f  
= 25MSPS, f  
= 20.2MHz, 30MHz Span (Notes 4, 7)  
= 10.1MHz, 30MHz Span (Notes 4, 7)  
= 20.2MHz, 25MHz Span (Notes 4, 7)  
= 5.02MHz, 25MHz Span (Notes 4, 7)  
= 2.51MHz, 25MHz Span (Notes 4, 7)  
= 1.00MHz, 25MHz Span (Notes 4, 7)  
= 5.02MHz, 25MHz Span (Notes 4, 7)  
CLK  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
f
CLK  
VOLTAGE REFERENCE  
Internal Reference Voltage, V  
FSADJ  
Pin 18 Voltage with Internal Reference  
1.04  
1.16  
±60  
0.1  
1.28  
V
o
Internal Reference Voltage Drift  
-
-
-
-
ppm/ C  
Internal Reference Output Current  
Sink/Source Capability  
µA  
Reference Input Impedance  
-
-
1
-
-
MΩ  
Reference Input Multiplying Bandwidth (Note 7)  
1.4  
MHz  
4
HI5760  
o
Electrical Specifications  
AV  
DD  
= DV  
DD  
= +5V, V  
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)  
REF  
A
HI5760  
= -40 C TO 85 C  
o
o
T
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DIGITAL INPUTS D9-D0, CLK  
Input Logic High Voltage with  
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
3.5  
2.1  
-
5
3
0
0
-
V
V
V
V
5V Supply, V  
IH  
Input Logic High Voltage with  
3V Supply, V  
-
IH  
Input Logic Low Voltage with  
5V Supply, V  
1.3  
0.9  
IL  
Input Logic Low Voltage with  
3V Supply, V  
-
IL  
Input Logic Current, I  
-10  
-10  
-
-
-
+10  
+10  
-
µA  
µA  
pF  
IH  
IL  
Input Logic Current, I  
Digital Input Capacitance, C  
IN  
5
TIMING CHARACTERISTICS  
Data Setup Time, t  
See Figure 41 (Note 3)  
See Figure 41 (Note 3)  
See Figure 41  
3
3
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
SU  
Data Hold Time, t  
HLD  
Propagation Delay Time, t  
1
-
PD  
CLK Pulse Width, t  
, t  
PW1 PW2  
See Figure 41 (Note 3)  
4
POWER SUPPLY CHARACTERISTICS  
AV  
DV  
Power Supply  
Power Supply  
(Note 8)  
2.7  
5.0  
5.0  
23  
4
5.5  
V
V
DD  
(Note 8)  
2.7  
5.5  
DD  
Analog Supply Current (I  
)
(5V or 3V, IOUTFS = 20mA)  
(5V or 3V, IOUTFS = 2mA)  
(5V, IOUTFS = Don’t Care) (Note 5)  
(3V, IOUTFS = Don’t Care) (Note 5)  
(5V or 3V, IOUTFS = Don’t Care)  
(5V, IOUTFS = 20mA) (Note 6)  
(5V, IOUTFS = 2mA) (Note 6)  
(5V, IOUTFS = 20mA) (Note 9)  
(3.3V, IOUTFS = 20mA) (Note 9)  
(3V, IOUTFS = 20mA) (Note 6)  
(3V, IOUTFS = 20mA) (Note 9)  
(3V, IOUTFS = 2mA) (Note 6)  
Single Supply (Note 7)  
-
30  
mA  
AVDD  
-
-
mA  
Digital Supply Current (I  
DVDD  
)
-
3
5
mA  
-
1.5  
1.6  
165  
70  
150  
75  
85  
67  
27  
-
-
mA  
Supply Current (I  
) Sleep Mode  
-
3
mA  
AVDD  
Power Dissipation  
-
-
mW  
mW  
mW  
mW  
mW  
mW  
mW  
% FSR/V  
-
-
-
-
-
-
-
-
-
-
-
-
Power Supply Rejection  
NOTES:  
-0.2  
+0.2  
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R  
ratio should be 31.969.  
(typically 625µA). Ideally the  
SET  
3. Parameter guaranteed by design or characterization and not production tested.  
4. Spectral measurements made with differential coupled transformer.  
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.  
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.  
7. See ‘Definition of Specifications’.  
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV  
and  
DD  
AV  
DD  
do not have to be equal.  
9. Measured with the clock at 60MSPS and the output frequency at 10MHz.  
5
HI5760  
Typical Performance Curves, 5V Power Supply  
80  
75  
70  
65  
60  
55  
50  
76  
74  
72  
70  
-6dBFS  
-6dBFS  
0dBFS  
-12dBFS  
68  
66  
64  
62  
60  
-12dBFS  
0dBFS  
1
2
3
4
5
6
7
8
9
10  
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6 1.8  
2
OUTPUT FREQUENCY (MHz)  
OUTPUT FREQUENCY (MHz)  
FIGURE 1. SFDR vs f  
, CLOCK = 5MSPS  
OUT  
FIGURE 2. SFDR vs f  
, CLOCK = 25MSPS  
OUT  
80  
75  
70  
65  
60  
55  
0dBFS  
-6dBFS  
75  
70  
-12dBFS  
-6dBFS  
65  
60  
55  
-12dBFS  
0dBFS  
50  
45  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
OUTPUT FREQUENCY (MHz)  
OUTPUT FREQUENCY (MHz)  
FIGURE 3. SFDR vs f  
, CLOCK = 50MSPS  
FIGURE 4. SFDR vs f  
, CLOCK =100MSPS  
OUT  
OUT  
75  
80  
75  
70  
65  
60  
55  
50  
45  
25MSPS  
70  
65  
60  
55  
50  
45  
50MSPS  
100MSPS  
6dBFS  
-12dBFS  
125MSPS  
0dBFS  
30  
0
5
10  
15  
20  
25  
35  
40  
45  
50  
-25  
-20  
-15  
-10  
-5  
0
AMPLITUDE (dBFS)  
OUTPUT FREQUENCY (MHz)  
FIGURE 5. SFDR vs f  
, CLOCK = 125MSPS  
FIGURE 6. SFDR vs AMPLITUDE, f = 10  
/f  
OUT  
CLK OUT  
6
HI5760  
Typical Performance Curves, 5V Power Supply (Continued)  
75  
70  
65  
60  
55  
50  
45  
40  
80  
75  
70  
65  
60  
55  
50  
45  
40  
25MSPS  
50MSPS  
25MSPS  
(3.38/3.63MHz)  
100MSPS  
50MSPS  
(6.75/7.25MHz)  
125MSPS  
100MSPS  
(13.5/14.5MHz)  
125MSPS  
(16.9/18.1MHz)  
-25  
-20  
-15  
-10  
-5  
0
-25  
-20  
-15  
-10  
-5  
0
AMPLITUDE (dBFS)  
AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)  
FIGURE 7. SFDR vs AMPLITUDE, f  
/f  
CLK OUT  
= 5  
FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f /f = 7  
CLK OUT  
75  
75  
2.5MHz  
10MHz  
70  
65  
60  
55  
50  
45  
40  
70  
-6dBFS DIFF  
0dBFS DIFF  
65  
20MHz  
60  
40MHz  
55  
-6dBFS SINGLE  
50  
0dBFS SINGLE  
45  
0
5
10  
15  
20  
25  
30  
35  
40  
2
4
6
8
10  
12  
14  
16  
18  
20  
I
(mA)  
OUTPUT FREQUENCY (MHz)  
OUT  
FIGURE 9. SFDR vs I  
, CLOCK = 100MSPS  
FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED,  
CLOCK = 100MSPS  
OUT  
80  
75  
70  
65  
60  
55  
50  
45  
40  
-10  
2.5MHz  
f
= 100MSPS  
-20  
CLK  
f
= 9.95MHz  
OUT  
AMPLITUDE = 0dBFS  
SFDR = 64dBc  
-30
10.1MHz  
-40  
14dB EXTERNAL ANALYZER ATTENUATION  
-50  
-60
-70
-80
-90  
40.4MHz  
-100  
-110  
-40  
-20  
0
20  
40  
60  
80  
0
50  
FREQUENCY (MHz)  
5MHz/DIV  
o
TEMPERATURE ( C)  
FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS  
FIGURE 12. SINGLE TONE SFDR  
7
HI5760  
Typical Performance Curves, 5V Power Supply (Continued)  
-10  
-20  
f
= 100MSPS  
CLK  
= 100MSPS  
f
CLK  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-30  
f
= 3.8,4.4,5.6,6.2MHz  
OUT  
f
= 13.5/14.5MHz  
OUT  
COMBINED PEAK  
COMBINED PEAK  
-40
AMPLITUDE = 0dBFS  
SFDR = 71.4dBc  
(IN A WINDOW)  
AMPLITUDE = 0dBFS  
SFDR = 62.9dBc  
-50  
14dB EXTERNAL  
ANALYZER ATTENUATION  
-60  
-70  
-80  
-90  
-100  
-110
0
5MHz/div  
50  
5MHz/DIV  
0.5  
15  
FREQUENCY (MHz)  
1.45MHz/DIV  
FIGURE 13. TWO TONE, CLOCK = 100MSPS  
FIGURE 14. FOUR-TONE, CLOCK = 100MSPS  
-20  
-30  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
f
= 50MSPS  
CLK  
f
= 100MSPS  
CLK  
= 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHz  
f
= 1.9,2.2,2.8,3.1MHz  
COMBINED PEAK  
AMPLITUDE = 0dBFS  
SFDR = 73.6dBc  
(IN A WINDOW)  
OUT  
f
OUT  
COMBINED PEAK AMPLITUDE = 0dBFS  
SFDR = 67dBc (IN A WINDOW)  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
0.5  
950kHz/DIV  
10  
1.95MHz/DIV  
20  
0.5  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS  
FIGURE 16. FOUR-TONE, CLOCK = 50MSPS  
0.4  
0.2  
0
0.4  
0.2  
0
-0.2  
-0.4  
-0.2  
-0.4  
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
CODE  
CODE  
FIGURE 17. DIFFERENTIAL NONLINEARITY  
FIGURE 18. INTEGRAL NONLINEARITY  
8
HI5760  
Typical Performance Curves, 5V Power Supply (Continued)  
160  
155  
150  
145  
140  
135  
130  
125  
120  
115  
110  
105  
0
20  
40  
60  
80  
100  
120  
CLOCK RATE (MSPS)  
FIGURE 19. POWER vs CLOCK RATE, f  
/f  
= 10, I  
= 20mA  
OUT  
CLK OUT  
Typical Performance Curves, 3V Power Supply  
80  
75  
70  
65  
80  
0dBFS  
-6dBFS  
75  
-6dBFS  
70  
0dBFS  
65  
-12dBFS  
60  
-12dBFS  
55  
60  
1
50  
2
3
4
5
6
7
8
9
10  
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6 1.8  
2
OUTPUT FREQUENCY (MHz)  
OUTPUT FREQUENCY (MHz)  
FIGURE 20. SFDR vs f  
, CLOCK = 5MSPS  
FIGURE 21. SFDR vs f  
0dBFS  
, CLOCK = 25MSPS  
OUT  
OUT  
80  
75  
70  
65  
60  
55  
50  
80  
75  
70  
65  
60  
55  
50  
45  
-6dBFS  
-6dBFS  
-12dBFS  
-12dBFS  
0dBFS  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
OUTPUT FREQUENCY (MHz)  
OUTPUT FREQUENCY (MHz)  
FIGURE 22. SFDR vs f  
, CLOCK = 50MSPS  
FIGURE 23. SFDR vs f  
, CLOCK = 100MSPS  
OUT  
OUT  
9
HI5760  
Typical Performance Curves, 3V Power Supply (Continued)  
80  
75  
70  
65  
60  
55  
50  
45  
80  
75  
70  
65  
60  
55  
50  
45  
0dBFS  
25MSPS  
50MSPS  
100MSPS  
125MSPS  
-6dBFS  
-12dBFS  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
-25  
-20  
-15  
-10  
-5  
0
OUTPUT FREQUENCY (MHz)  
AMPLITUDE (dBFS)  
FIGURE 24. SFDR vs f  
, CLOCK = 125MSPS  
25MSPS  
FIGURE 25. SFDR vs AMPLITUDE, f  
/f = 10  
CLK OUT  
OUT  
75  
70  
80  
75  
70  
65  
60  
55  
50  
45  
40  
25MSPS  
65  
(3.38/3.63MHz)  
50MSPS  
60  
100MSPS  
50MSPS  
(6.75/7.25MHz)  
5MSPS  
55  
100MSPS  
125MSPS  
(13.5/14.5MHz)  
50  
45  
40  
125MSPS  
(16.9/18.1MHz)  
-25  
-20  
-15  
-10  
-5  
0
-25  
-20  
-15  
-10  
-5  
0
AMPLITUDE (dBFS)  
AMPLITUDE (dBFS)  
FIGURE 26. SFDR vs AMPLITUDE, f  
/f  
= 5  
FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, f  
/f  
CLK OUT  
= 7  
CLK OUT  
80  
80  
2.5MHz  
75  
70  
65  
60  
55  
50  
45  
75  
70  
65  
60  
55  
50  
45  
0dBFS DIFF  
10MHz  
20MHz  
-6dBFS SINGLE  
-6dBFS DIFF  
40MHz  
0dBFS SINGLE  
0
5
10  
15  
20  
25  
30  
35  
40  
2
4
6
8
10  
12  
14  
16  
18  
20  
I
(MA)  
OUT  
OUTPUT FREQUENCY (MHz)  
FIGURE 28. SFDR vs I  
, CLOCK = 100MSPS  
FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED,  
CLOCK = 100MSPS  
OUT  
10  
HI5760  
Typical Performance Curves, 3V Power Supply (Continued)  
80  
75  
70  
65  
60  
55  
50  
45  
40  
-10  
-20  
f
= 100MSPS  
CLK  
f
2.5MHz  
= 9.95MHz  
OUT  
AMPLITUDE = 0dBFS  
SFDR = 63dBc  
14dB EXTERNAL  
ANALYZER ATTENUATION  
-30  
10.1MHz  
-40  
-50  
-60  
-70  
-80  
40.4MHz  
60  
-90  
-100  
-110  
-40  
-20  
0
20  
40  
80  
0
5MHz/DIV  
50  
o
TEMPERATURE ( C)  
FREQUENCY (MHz)  
FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS  
-20  
FIGURE 31. SINGLE TONE SFDR  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
f
= 100MSPS  
CLK  
f
= 100MSPS  
CLK  
= 13.5/14.5MHz  
-30  
-40  
f
= 3.8,4.4,5.6,6.2MHz  
OUT  
f
OUT  
COMBINED PEAK  
COMBINED PEAK  
AMPLITUDE = 0dBFS  
SFDR = 70.6dBc  
(IN A WINDOW)  
AMPLITUDE = 0dBFS  
SFDR = 61.5dBc  
-50  
14dB EXTERNAL  
ANALYZER ATTENUATION  
-60  
-70  
-80  
-90  
-100  
-110  
0.5  
1.45MHz/DIV  
15  
0
5MHz/DIV  
50  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 32. TWO-TONE, CLOCK = 100MSPS  
FIGURE 33. FOUR-TONE, CLOCK = 100MSPS  
-20  
-30  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
f
= 100MSPS  
CLK  
f
= 50MSPS  
CLK  
f
= 2.6, 3.2, 3.8, 4.4,  
OUT  
f
= 1.9, 2.2, 2.8, 3.1MHz  
COMBINED PEAK  
AMPLITUDE = 0dBFS  
SFDR = 74.2dBc  
OUT  
5.6, 6.2, 6.8MHz  
-40  
COMBINED PEAK  
-50  
AMPLITUDE = 0dBFS  
SFDR = 67.4dBc  
(IN A WINDOW)  
(IN A WINDOW)  
-60  
-70  
-80  
-90  
-100  
-110  
0.5  
1.95MHz/DIV  
20  
0
950kHz/DIV  
10  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS  
FIGURE 35. FOUR-TONE, CLOCK = 50MSPS  
11  
HI5760  
Typical Performance Curves, 3V Power Supply (Continued)  
0.4  
0.2  
0
0.4  
0.2  
0
-0.2  
-0.4  
-0.2  
-0.4  
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
CODE  
CODE  
FIGURE 36. DIFFERENTIAL NONLINEARITY  
FIGURE 37. INTEGRAL NONLINEARITY  
76  
74  
72  
70  
68  
66  
64  
62  
60  
0
20  
40  
60  
80  
100  
120  
CLOCK RATE (MSPS)  
FIGURE 38. POWER vs CLOCK RATE, f  
/f  
= 10, I  
= 20mA  
CLK OUT  
OUT  
12  
HI5760  
Timing Diagrams  
50%  
CLK  
D9-D0  
1
GLITCH AREA =  
/ (H x W)  
2
V
1
/
LSB ERROR BAND  
2
HEIGHT (H)  
I
OUT  
t(ps)  
WIDTH (W)  
t
SETT  
t
PD  
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM  
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT  
METHOD  
t
t
PW2  
PW1  
50%  
CLK  
t
t
SU  
t
SU  
SU  
t
HLD  
t
t
HLD  
HLD  
D9-D0  
t
SETT  
t
PD  
I
OUT  
t
t
SETT  
SETT  
t
t
PD  
PD  
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM  
13  
HI5760  
either T  
range) per degree C.  
or T  
. The units are ppm of FSR (full scale  
Definition of Specifications  
MIN  
MAX  
Integral Linearity Error, INL, is the measure of the worst  
case point that deviates from a best fit straight line of data  
values along the transfer curve.  
Power Supply Rejection, is measured using a single power  
supply. Its nominal +5V is varied ±10% and the change in the  
DAC full scale output is noted.  
Differential Linearity Error, DNL, is the measure of the  
step size output deviation from code to code. Ideally the step  
size should be 1 LSB. A DNL specification of 1 LSB or less  
guarantees monotonicity.  
Reference Input Multiplying Bandwidth, is defined as the  
3dB bandwidth of the voltage reference input. It is measured  
by using a sinusoidal waveform as the external reference  
with the digital inputs set to all 1s. The frequency is  
increased until the amplitude of the output waveform is 0.707  
of its original value.  
Output Settling Time, is the time required for the output  
voltage to settle to within a specified error band measured  
from the beginning of the output transition. In the case of the  
HI5760, the measurement was done by switching from code  
0 to 256, or quarter scale. Termination impedance was 25Ω  
due to the parallel resistance of the output 50and the  
oscilloscope’s 50input. This also aids the ability to resolve  
the specified error band without overdriving the oscilloscope.  
Internal Reference Voltage Drift, is defined as the  
maximum deviation from the value measured at room  
temperature to the value measured at either Tmin or Tmax.  
The units are ppm per degree C.  
Detailed Description  
Singlet Glitch Area, is the switching transient appearing on  
the output during a code transition. It is measured as the  
area under the overshoot portion of the curve and is  
expressed as a Volt-Time specification.  
The HI5760 is a 10-bit, current out, CMOS, digital to analog  
converter. Its maximum update rate is 125MSPS and can be  
powered by either single or dual power supplies in the  
recommended range of +3V to +5V. It consumes less than  
165mW of power when using a +5V supply with the data  
switching at 100MSPS. The architecture is based on a  
segmented current source arrangement that reduces glitch  
by reducing the amount of current switching at any one time.  
The five MSBs are represented by 31 major current sources  
of equivalent current. The five LSBs are comprised of binary  
weighted current sources. Consider an input waveform to the  
converter which is ramped through all the codes from 0 to  
1023. The five LSB current sources would begin to count up.  
When they reached the all high state (decimal value of 31)  
and needed to count to the next code, they would all turn off  
and the first major current source would turn on. To continue  
counting upward, the 5 LSBs would count up another 31  
codes, and then the next major current source would turn on  
and the five LSBs would all turn off. The process of the  
single, equivalent, major current source turning on and the  
five LSBs turning off each time the converter reaches  
another 31 codes greatly reduces the glitch at any one  
switching point. In previous architectures that contained all  
binary weighted current sources or a binary weighted  
resistor ladder, the converter might have a substantially  
larger amount of current turning on and off at certain, worst-  
case transition points such as mid-scale and quarter scale  
transitions. By greatly reducing the amount of current  
switching at certain ‘major’ transitions, the overall glitch of  
the converter is dramatically reduced, improving settling  
times and transient problems.  
Full Scale Gain Error, is the error from an ideal ratio of 32  
between the output current and the full scale adjust current  
(through R  
).  
SET  
Full Scale Gain Drift, is measured by setting the data inputs  
to all ones and measuring the output voltage through a  
known resistance as the temperature is varied from T  
to  
MIN  
T
. It is defined as the maximum deviation from the value  
MAX  
measured at room temperature to the value measured at  
either T or T . The units are ppm of FSR (full scale  
MIN  
MAX  
range) per degree C.  
Total Harmonic Distortion, THD, is the ratio of the DAC  
output fundamental to the RMS sum of the first five  
harmonics.  
Spurious Free Dynamic Range, SFDR, is the amplitude  
difference from the fundamental to the largest harmonically or  
non-harmonically related spur within the specified window.  
Output Voltage Compliance Range, is the voltage limit  
imposed on the output. The output impedance load should  
be chosen such that the voltage developed does not violate  
the compliance range.  
Offset Error, is measured by setting the data inputs to all  
zeros and measuring the output voltage through a known  
resistance. Offset error is defined as the maximum deviation  
of the output current from a value of 0mA.  
Offset Drift, is measured by setting the data inputs to all  
zeros and measuring the output voltage through a known  
resistance as the temperature is varied from T  
to T  
.
MAX  
MIN  
It is defined as the maximum deviation from the value  
measured at room temperature to the value measured at  
14  
HI5760  
If the full scale output current is set to 20mA by using the  
internal voltage reference (1.16V) and a 1.86kR  
resistor, then the input coding to output current will resemble  
Digital Inputs and Termination  
SET  
The HI5760 digital inputs are guaranteed to CMOS levels.  
However, TTL compatibility can be achieved by lowering the  
supply voltage to 3V due to the digital threshold of the input  
buffer being approximately half of the supply voltage. The  
internal register is updated on the rising edge of the clock. To  
minimize reflections, proper termination should be  
implemented. If the lines driving the clock and the digital  
inputs are 50lines, then 50termination resistors should  
be placed as close to the converter inputs as possible to the  
digital ground plane (if separate grounds are used).  
the following:  
TABLE 1. INPUT CODING vs OUTPUT CURRENT  
INPUT CODE (D9-D0)  
11111 11111  
IOUTA (mA)  
IOUTB (mA)  
20  
10  
0
0
10000 00000  
10  
20  
00000 00000  
Outputs  
Ground Plane(s)  
IOUTA and IOUTB are complementary current outputs. The  
sum of the two currents is always equal to the full scale  
output current minus one LSB. If single ended use is  
desired, a load resistor can be used to convert the output  
current to a voltage. It is recommended that the unused  
output be either grounded or equally terminated. The voltage  
developed at the output must not violate the output voltage  
If separate digital and analog ground planes are used, then  
all of the digital functions of the device and their  
corresponding components should be over the digital ground  
plane and terminated to the digital ground plane. The same  
is true for the analog components and the analog ground  
plane. The converter will function properly with a single  
ground plane, as the Evaluation Board is configured in this  
matter. Refer to the AppNote on the HI5760 Evaluation  
Board for further discussion of the ground plane(s) upon  
availability.  
compliance range of -0.3V to 1.25V. R  
should be  
LOAD  
chosen so that the desired output voltage is produced in  
conjunction with the output full scale current, which is  
described above in the ‘Reference’ section. If a known line  
impedance is to be driven, then the output load resistor  
should be chosen to match this impedance. The output  
voltage equation is:  
Noise Reduction  
To minimize power supply noise, 0.1µF capacitors should be  
placed as close as possible to the converter’s power supply  
pins, AV  
and DV . Also, should the layout be designed  
DD  
DD  
V
= I  
OUT  
X R .  
LOAD  
OUT  
using separate digital and analog ground planes, these  
capacitors should be terminated to the digital ground for  
These outputs can be used in a differential-to-single-ended  
arrangement to achieve better harmonic rejection. The  
SFDR measurements in this data sheet were performed with  
a 1:1 transformer on the output of the DAC (see Figure 1).  
With the center tap grounded, the output swing of pins 21  
and 22 will be biased at zero volts. It is important to note  
here that the negative voltage output compliance range limit  
DV  
and to the analog ground for AV . Additional filtering  
DD  
DD  
of the power supplies on the board is recommended. See  
the AppNote on the HI5760 Evaluation Board for more  
information upon availability.  
Voltage Reference  
The internal voltage reference of the device has a nominal  
value of +1.2V with a ±60 ppm/oC drift coefficient over the  
full temperature range of the converter. It is recommended  
that a 0.1µF capacitor be placed as close as possible to the  
REFIO pin, connected to the analog ground. The REFLO  
pin (16) selects the reference. The internal reference can  
be selected if pin 16 is tied low (ground). If an external  
reference is desired, then pin 16 should be tied high (to the  
analog supply voltage) and the external reference driven  
into REFIO, pin 17. The full scale output current of the  
converter is a function of the voltage reference used and  
is -300mV, imposing a maximum of 600mV  
amplitude  
P-P  
with this configuration. The loading as shown in Figure 1 will  
result in a 500mV signal at the output of the transformer if  
the full scale output current of the DAC is set to 20mA.  
V
= (2 x I  
x R )V  
OUT EQ  
OUT  
50Ω  
100Ω  
50Ω  
IOUTB  
IOUTA  
PIN 21  
50Ω  
PIN 22  
HI5760  
the value of R  
. I should be within the 2mA to 20mA  
SET OUT  
range, through operation below 2mA is possible, with  
performance degradation.  
FIGURE 42.  
If the internal reference is used, V  
FSADJ  
will equal  
approximately 1.16V (pin 18). If an external reference is used,  
will equal the external reference. The calculation for  
V
= 2 x I  
x R , where R is ~12.5.  
EQ EQ  
OUT  
OUT  
V
FSADJ  
I
(Full Scale) is:  
OUT  
I
(Full Scale) = (V  
/R  
)x 32.  
OUT  
FSADJ SET  
15  
HI5760  
Pin Descriptions  
PIN NO.  
PIN NAME  
PIN DESCRIPTION  
1-10  
D9 (MSB) Through Digital Data Bit 9, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).  
D0 (LSB)  
11-14  
15  
NC  
No Connect. Recommend ground.  
SLEEP  
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep  
pin has internal 20µA active pulldown current.  
16  
17  
18  
REFLO  
REFIO  
FSADJ  
Connect to analog ground to enable internal 1.2V reference or connect to AV  
reference.  
to disable internal  
DD  
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is  
enabled. Use 0.1µF cap to ground when internal reference is enabled.  
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output  
Current = 32 x V  
/R .  
FSADJ SET  
19  
20  
21  
COMP1  
ACOM  
IOUTB  
For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AV  
.
DD  
Analog Ground.  
The complimentary current output of the device. Full scale output current is achieved when all input bits  
are set to binary 0.  
22  
23  
IOUTA  
NC  
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.  
Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to  
ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit  
and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.)  
24  
25  
26  
27  
28  
AV  
DD  
Analog Supply (+3V to +5V).  
NC  
DCOM  
DV  
No Connect. (For upward compatibility to 12 and 14b devices, pin 25 needs to be grounded to ACOM.)  
Digital Ground.  
Digital Supply (+3V to +5V).  
DD  
CLK  
Input for clock. Positive edge of clock latches data.  
16  
HI5760  
Small Outline Plastic Packages (SOIC)  
M28.3 (JEDEC MS-013-AE ISSUE C)  
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE  
INDEX  
0.25(0.010)  
M
B M  
H
AREA  
INCHES  
MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
2.35  
0.10  
0.33  
0.23  
MAX  
2.65  
0.30  
0.51  
0.32  
18.10  
7.60  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0926  
0.0040  
0.013  
0.1043  
0.0118  
0.0200  
0.0125  
-
-
1
2
3
L
9
SEATING PLANE  
A
0.0091  
0.6969  
0.2914  
-
-A-  
0.7125 17.70  
3
o
h x 45  
D
0.2992  
7.40  
4
0.05 BSC  
1.27 BSC  
-
-C-  
α
H
h
0.394  
0.01  
0.419  
0.029  
0.050  
10.00  
0.25  
0.40  
10.65  
0.75  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
0.016  
6
0.25(0.010) M  
C
A M B S  
N
α
28  
28  
7
o
o
o
o
0
8
0
8
-
NOTES:  
Rev. 0 12/93  
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2  
of Publication Number 95.  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusion and gate burrs shall not exceed  
0.15mm (0.006 inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. In-  
terlead flash and protrusions shall not exceed 0.25mm (0.010  
inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual  
index feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater  
above the seating plane, shall not exceed a maximum value of  
0.61mm (0.024 inch)  
10. Controlling dimension: MILLIMETER. Converted inch dimen-  
sions are not necessarily exact.  
17  
HI5760  
Thin Shrink Small Outline Plastic Packages (TSSOP)  
M28.173  
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC  
PACKAGE  
INDEX  
AREA  
0.25(0.010)  
M
B M  
E
E1  
-B-  
INCHES  
MIN  
MILLIMETERS  
GAUGE  
PLANE  
SYMBOL  
MAX  
0.047  
0.006  
0.051  
0.0118  
0.0079  
0.386  
0.177  
MIN  
-
MAX  
1.20  
0.15  
1.05  
0.30  
0.20  
9.80  
4.50  
NOTES  
A
A1  
A2  
b
-
-
1
2
3
0.002  
0.031  
0.0075  
0.0035  
0.378  
0.169  
0.05  
0.80  
0.19  
0.09  
9.60  
4.30  
-
L
-
0.25  
0.010  
0.05(0.002)  
SEATING PLANE  
A
9
-A-  
D
c
-
D
E1  
e
3
-C-  
4
α
A2  
e
A1  
0.026 BSC  
0.65 BSC  
-
c
b
0.10(0.004)  
E
0.246  
0.256  
6.25  
0.45  
6.50  
0.75  
-
0.10(0.004) M  
C
A M B S  
L
0.0177  
0.0295  
6
N
α
28  
28  
7
o
o
o
o
NOTES:  
0
8
0
8
-
1. These package dimensions are within allowable dimensions of  
JEDEC MO-153-AE, Issue E.  
Rev. 0 6/98  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm  
(0.006 inch) per side.  
4. Dimension “E1” does not include interlead flash or protrusions. Inter-  
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per  
side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. Dimension “b” does not include dambar protrusion. Allowable dambar  
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-  
sion at maximum material condition. Minimum space between protru-  
sion and adjacent lead is 0.07mm (0.0027 inch).  
10. Controlling dimension: MILLIMETER. Converted inch dimensions  
are not necessarily exact. (Angles in degrees)  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
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FAX: (886) 2 2715 3029  
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TEL: (321) 724-7000  
FAX: (321) 724-7240  
18  
配单直通车
HI5760BIB产品参数
型号:HI5760BIB
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Contact Manufacturer
IHS 制造商:ROCHESTER ELECTRONICS LLC
零件包装代码:SOIC
包装说明:SOP,
针数:28
Reach Compliance Code:unknown
风险等级:5.74
最大模拟输出电压:1.25 V
最小模拟输出电压:-0.3 V
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:PARALLEL, WORD
JESD-30 代码:R-PDSO-G28
JESD-609代码:e0
长度:17.9 mm
最大线性误差 (EL):0.0977%
湿度敏感等级:1
位数:10
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240
认证状态:Not Qualified
座面最大高度:2.65 mm
标称安定时间 (tstl):0.035 µs
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:TIN LEAD
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm
Base Number Matches:1
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