HI5812
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
Power Supplies and Grounding
V
and V are the digital supply pins: they power all
DD
SS
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V and V
DD SS
The input will continue to track until the end of period 3, the
same as when free running.
lines, V should have a low impedance path to digital
SS
ground and V
should be well bypassed.
DD
Figure 2 illustrates the same operation as above but with an
Except for V +, which is a substrate connection to V , all
AA
DD
external clock. If STRT is removed (at least t STRT) before
R
pins have protection diodes connected to V
and V .
DD
SS
clock period 2, a low signal applied to STRT will drop the
DRDY flag as before, and with the first positive-going clock
Input transients above V
the digital supplies.
or below V will get steered to
SS
DD
edge that meets the (t STRT) setup time, the converter will
SU
continue with clock period 3.
The V + and V - terminals supply the charge-balancing
AA AA
comparator only. Because the comparator is autobalanced
between conversions, it has good low-frequency supply
rejection. It does not reject well at high frequencies however;
Clock
The HI5812 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are
V
- should be returned to a clean analog ground and V +
AA AA
should be RC decoupled from the digital supply as shown in
Figure 22.
synchronized with the rising edge of the clock signal.
Figure 21 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.
There is approximately 50Ω of substrate impedance
between V
and V +. This can be used, for example, as
AA
DD
part of a low-pass RC filter to attenuate switching supply
noise. A 10µF capacitor from V + to ground would
AA
The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.
attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from V
to V + to
DD
AA
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low
distortion sine wave is applied to the input of the A/D
converter. The input is sampled by the A/D and its output
stored in RAM. The data is than transformed into the
frequency domain with a 4096 point FFT and analyzed to
evaluate the converters dynamic performance such as SNR
and THD. See typical performance characteristics.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minimum frequency shown in the
specifications. In the above two cases, a further restriction
applies in that the clock should not be shut off during the
third sample period for more than 1ms. This might cause an
internal charge-pump voltage to decay.
Signal-To-Noise Ratio
The signal to noise ratio (SNR) is the measured RMS signal
to RMS sum of noise at a specified input and sampling
frequency. The noise is the RMS sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N + 1.76)
dB. For an ideal 12-bit converter the SNR is 74dB.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum t
and
LOW
times shown in the specifications. A violation may
t
HIGH
cause an internal miscount and invalidate the results.
Differential and integral linearity errors will degrade SNR.
INTERNAL
ENABLE
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
CLOCK
CLK
OPTIONAL
EXTERNAL
CLOCK
Signal-To-Noise + Distortion Ratio
100kΩ
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
18pF
Sinewave Signal Power
SINAD = 10 Log
FIGURE 21. INTERNAL CLOCK CIRCUITRY
Noise + Harmonic Power (2nd - 6th)
12
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