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HIP6301

®

Data Sheet

December 27, 2004

FN4765.6

Microprocessor CORE Voltage Regulator

Multi-Phase Buck PWM Controller

Features

• Multi-Phase Power Conversion

The HIP6301 multi-phase PWM control IC together with its

companion gate drivers, the HIP6601B, HIP6602B,

HIP6603B or HIP6604B and external MOSFETs provides a

precision voltage regulation system for advanced

• Precision Channel Current Sharing

- Loss Less Current Sampling - Uses r

DS(ON)

• Precision CORE Voltage Regulation

- ±1% System Accuracy Over Temperature

microprocessors. Multiphase power conversion is a marked

departure from earlier single phase converter configurations

previously employed to satisfy the ever increasing current

demands of modern microprocessors. Multi-phase

convertors, by distributing the power and load current results

in smaller and lower cost transistors with fewer input and

output capacitors. These reductions accrue from the higher

effective conversion frequency with higher frequency ripple

current due to the phase interleaving process of this

topology. For example, a three phase convertor operating at

350kHz will have a ripple frequency of 1.05MHz. Moreover,

greater convertor bandwidth of this design results in faster

response to load transients.

• Microprocessor Voltage Identification Input

- 5-Bit VID Input

- 1.100V to 1.850V in 25mV Steps

- Programmable “Droop” Voltage

• Fast Transient Recovery Time

• Over Current Protection

• Automatic Selection of 2, 3, or 4 Phase Operation

• High Ripple Frequency, (Channel Frequency) Times

Number Channels . . . . . . . . . . . . . . . . . .100kHz to 6MHz

• Pb-Free Available (RoHS Compliant)

Outstanding features of this controller IC include

programmable VID codes from the microprocessor that

range from 1.100V to 1.850V with a system accuracy of

±1%. Pull up currents on these VID pins eliminates the need

for external pull up resistors. In addition “droop”

compensation, used to reduce the overshoot or undershoot

of the CORE voltage, is easily programmed with a single

resistor.

Ordering Information

PART NUMBER

TEMP. (°C)

PACKAGE PKG. DWG #

HIP6301CB

0 to 70

20 Ld SOIC

M20.3

HIP6301CBZ

(Note)

0 to 70

20 Ld SOIC

(Pb-free)

HIP6301CB-T

20 Ld SOIC Tape and Reel

HIP6301CBZ-T

(Note)

20 Ld SOIC Tape and Reel

(Pb-free)

Another feature of this controller IC is the PGOOD monitor

circuit which is held low until the CORE voltage increases,

during its Soft-Start sequence, to within 10% of the

programmed voltage. Overvoltage, 15% above programmed

CORE voltage, results in the converter shutting down and

turning the lower MOSFETs ON to clamp and protect the

microprocessor. Under voltage is also detected and results

in PGOOD low if the CORE voltage falls 10% below the

programmed level. Overcurrent protection reduces the

regulator current to less than 25% of the programmed trip

value. These features provide monitoring and protection for

the microprocessor and power system.

HIP6301CBZA-T

(Note)

20 Ld SOIC Tape and Reel

(Pb-free)

HIP6301EVAL2

Evaluation Platform

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding

compounds/die attach materials and 100% matte tin plate termination finish, which are

RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinout

HIP6301 (SOIC)

TOP VIEW

1

2

20

19

18

17

16

15

14

13

12

11

VID4

VID3

V

CC

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

3

VID2

4

VID1

5

VID0

6

COMP

FB

7

8

FS/DIS

GND

9

10

VSEN

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HIP6301

Block Diagram

V

PGOOD

CC

POWER-ON

RESET (POR)

+

-

VSEN

THREE

STATE

UV

OV

LATCH

X 0.9

CLOCK AND

S

SAWTOOTH

GENERATOR

FS/EN

PWM1

+

-

+

OVP

+

-

∑

X1.15

PWM

-

+

SOFT-

+

-

∑

START

AND FAULT

LOGIC

PWM2

PWM

-

COMP

+

-

∑

PWM

PWM3

PWM4

-

VID0

VID1

VID2

VID3

VID4

+

D/A

+

-

∑

PWM

+

-

E/A

-

PHASE

NUMBER

CHANNEL

DETECTOR

CURRENT

CORRECTION

FB

ISEN1

I_TOT

+

ISEN2

ISEN3

+

∑

+

OC

-

ISEN4

I_TRIP

GND

FN4765.6

December 27, 2004

2

HIP6301

Simplified Power System Diagram

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

VSEN

PWM 1

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 2

MICROPROCESSOR

HIP6301

PWM 3

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 4

VID

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

Functional Pin Description

1

2

20

19

18

17

16

15

14

13

12

11

VID4

VID3

V

CC

GND (Pin 9)

PGOOD

PWM4

ISEN4

ISEN1

PWM1

PWM2

ISEN2

ISEN3

PWM3

Bias and reference ground. All signals are referenced to this

pin.

3

VID2

4

VID1

VSEN (Pin 10)

5

VID0

6

Power good monitor input. Connect to the microprocessor-

CORE voltage.

COMP

FB

7

8

FS/DIS

GND

PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and

PWM4 (Pin 18)

9

10

VSEN

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601B/2B/3B/4B driver. For

systems which use 3 channels, connect PWM4 high. Two

channel systems connect PWM3 and PWM4 high.

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)

and VID0 (Pin 5)

ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and

ISEN4 (Pin 17)

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The HIP6301 decodes

VID bits to establish the output voltage. See Table 1.

Current sense inputs from the individual converter channel’s

phase nodes. Unused sense lines MUST be left open.

COMP (Pin 6)

PGOOD (Pin 19)

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

Power good. This pin is an open-drain logic signal that

indicates when the microprocessor CORE voltage (VSEN

pin) is within specified limits and Soft-Start has timed out.

FB (Pin 7)

Inverting input of the internal error amplifier.

V

(Pin 20)

CC

Bias supply. Connect this pin to a 5V supply.

FS/DIS (Pin 8)

Channel frequency, F , select and disable. A resistor from

SW

this pin to ground sets the switching frequency of the

FN4765.6

3

December 27, 2004

HIP6301

Typical Application - 2 Phase Converter Using HIP6601B Gate Drivers

+12V

V

= +5V

IN

BOOT

PVCC

VCC

UGATE

+5V

PHASE

DRIVER

HIP6601B

PWM

LGATE

GND

COMP

V

FB

CC

VSEN

+V

CORE

PWM4

PWM3

+12V

PGOOD

PWM2

PWM1

V

= +5V

IN

VID4

VID3

BOOT

PVCC

UGATE

PHASE

VID2

VID1

MAIN

CONTROL

HIP6301

VCC

DRIVER

HIP6601B

VID0

PWM

NC

ISEN4

LGATE

GND

ISEN3

ISEN2

ISEN1

FS/DIS

GND

FN4765.6

December 27, 2004

4

HIP6301

Typical Application - 4 Phase Converter Using HIP6602B Gate Drivers

V

= +12V

IN

+12V

BOOT1

UGATE1

PHASE1

L

01

V

CC

LGATE1

PVCC

+5V

DUAL

DRIVER

HIP6602B

+5V

V

+12V

IN

BOOT2

FB

COMP

V

CC

VSEN

UGATE2

PHASE2

L

02

ISEN1

PWM1

PWM2

PGOOD

VID4

PWM2

ISEN2

LGATE2

VID3

GND

VID2

VID1

VID0

MAIN

CONTROL

HIP6301

+V

CORE

ISEN3

FS/DIS

PWM3

PWM4

V

IN

+12V

BOOT3

GND

ISEN4

UGATE3

PHASE3

L

03

V

CC

LGATE3

PVCC

DUAL

DRIVER

HIP6602B

+5V

V

+12V

BOOT4

IN

UGATE4

PHASE4

L

04

PWM3

PWM4

LGATE4

GND

FN4765.6

December 27, 2004

5

HIP6301

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to V + 0.3V

Thermal Resistance (Typical, Note 1)

θ

(°C/W)

CC

JA

CC

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65 C to 150°C

65

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

o

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Operating Conditions: V = 5V, T = 0°C to 70°C, Unless Otherwise Specified

CC

A

PARAMETER

INPUT SUPPLY POWER

Input Supply Current

TEST CONDITIONS

MIN

TYP MAX UNITS

R

= 100kΩ

-

10

15

4.5

mA

V

T

EN = 0V

4.25

3.75

8.8

POR (Power-On Reset) Threshold

V

Rising

Falling

4.38

3.88

4.5

CC

4.00

V

REFERENCE AND DAC

System Accuracy

Percent system deviation from programmed VID Codes

DAC Programming Input Low Threshold Voltage

DAC Programming Input High Threshold Voltage

VIDx = 0V or VIDx = 3V

-1

-

1

0.8

-

%

V

DAC (VID0 - VID3) Input Low Voltage

DAC (VID0 - VID3) Input High Voltage

VID Pull-Up

2.0

10

-

V

20

40

µA

CHANNEL GENERATOR, SAWTOOTH GENERATOR and Maximum PWM Duty Cycle

Frequency, F = 100kΩ, ±1%

R

224

280

-

336

1.5

1.0

-

kHz

MHz

V

SW

T

Adjustment Range

Disable Voltage

See Figure 10

0.05

Maximum voltage at FS/DIS to disable controller. I

= 1mA.

-

1.2

1.33

75

FS/DIS

Sawtooth Amplitude

PWM Maximum Duty Cycle

ERROR AMPLIFIER

DC Gain

Amplitude of Sawtooh Generator at Channel Comparator Input

Vp-p

%

-

R

C

R

= 10K to ground

-

72

18

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product

Slew Rate

= 100pF, R = 10K to ground

-

L

= 100pF, R = 10K to ground

L

5.3

4.1

0.16

Maximum Output Voltage

Minimum Output Voltage

= 10K to ground

3.6

-

0.5

V

I

SEN

Full Scale Input Current

Overcurrent Trip Level

-

50

-

µA

-67.5

-87.5

POWER GOOD MONITOR

Undervoltage Threshold

PGOOD Low Output Voltage

VSEN Rising

VSEN Falling

-

0.92

0.90

0.18

-

V

DAC

V

DAC

V

I

= 4mA

0.4

PGOOD

FN4765.6

December 27, 2004

6

HIP6301

Electrical Specifications Operating Conditions: V = 5V, T = 0°C to 70°C, Unless Otherwise Specified (Continued)

CC

A

PARAMETER

PROTECTION

TEST CONDITIONS

MIN

TYP MAX UNITS

Overvoltage Threshold

VSEN Rising

1.12

-

1.15

2

1.2

-

V

DAC

%

Percent Overvoltage Hysteresis

VSEN Falling after Overvoltage

R

IN

FB

V

IN

HIP6303

ERROR

AMPLIFIER

COMPARATOR

L

Q1

01

-

PWM1

CORRECTION

PWM

-

HIP6601B

CIRCUIT

+

∑

I

L1

+

-

Q2

PHASE

PROGRAMMABLE

REFERENCE

DAC

R

ISEN1

+

CURRENT

SENSING

I

SEN1

∑

-

I AVERAGE

CURRENT

AVERAGING

V

CORE

C

R

OUT

LOAD

R

ISEN2

I

SEN2

+

CURRENT

SENSING

∑

V

IN

PHASE

-

COMPARATOR

+

L

Q3

02

∑

+

-

PWM2

PWM

HIP6601B

CORRECTION

CIRCUIT

I

L2

Q4

FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE HIP6301 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER

CHANNEL REGULATOR

drive the Error Amplifier output either high or low, depending

upon the CORE voltage. Low CORE voltage makes the

amplifier output move towards a higher output voltage level.

Amplifier output voltage is applied to the positive inputs of

the Comparators via the Correction summing networks. Out-

of-phase sawtooth signals are applied to the two

Comparators inverting inputs. Increasing Error Amplifier

voltage results in increased Comparator output duty cycle.

This increased duty cycle signal is passed through the PWM

CIRCUIT with no phase reversal and on to the HIP6601B,

again with no phase reversal for gate drive to the upper

MOSFETs, Q1 and Q3. Increased duty cycle or ON time for

the MOSFET transistors results in increased output voltage

to compensate for the low output voltage sensed.

Operation

Figure 1 shows a simplified diagram of the voltage regulation

and current control loops. Both voltage and current feedback

are used to precisely regulate voltage and tightly control

output currents, I and I , of the two power channels. The

L1 L2

voltage loop comprises the Error Amplifier, Comparators,

gate drivers and output MOSFETs. The Error Amplifier is

essentially connected as a voltage follower that has as an

input, the Programmable Reference DAC and an output that

is the CORE voltage.

Voltage Loop

Feedback from the CORE voltage is applied via resistor R

to the inverting input of the Error Amplifier. This signal can

IN

FN4765.6

7

December 27, 2004

HIP6301

Current Loop

The current control loop works in a similar fashion to the

voltage control loop, but with current control information

applied individually to each channel’s Comparator. The

information used for this control is the voltage that is

PWM 1

PWM 2

PWM 3

PWM 4

developed across r

of each lower MOSFET, Q2 and

DS(ON)

Q4, when they are conducting. A single resistor converts and

scales the voltage across the MOSFETs to a current that is

applied to the Current Sensing circuit within the HIP6301.

Output from these sensing circuits is applied to the current

averaging circuit. Each PWM channel receives the difference

current signal from the summing circuit that compares the

average sensed current to the individual channel current.

When a power channel’s current is greater than the average

current, the signal applied via the summing Correction circuit

to the Comparator, reduces the output pulse width of the

Comparator to compensate for the detected “above average”

current in that channel.

FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz

Power supply ripple frequency is determined by the channel

Droop Compensation

frequency, F , multiplied by the number of active channels.

SW

In addition to control of each power channel’s output current,

the average channel current is also used to provide CORE

voltage “droop” compensation. Average full channel current

For example, if the channel frequency is set to 250kHz and

there are three phases, the ripple frequency is 750kHz.

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

is defined as 50µA. By selecting an input resistor, R , the

amount of voltage droop required at full load current can be

programmed. The average current driven into the FB pin

IN

results in a voltage increase across resistor R that is in the

IN

direction to make the Error Amplifier “see” a higher voltage at

the inverting input, resulting in the Error Amplifier adjusting

Initialization

The HIP6301 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to

the output voltage lower. The voltage developed across R

IN

is equal to the “droop” voltage. See the “Current Sensing and

Balancing” section for more details.

the V

pin of the HIP6301. Oscillator, Sawtooth Generator,

CC

Soft-Start and other functions are initialized during this

interval. These circuits are controlled by POR, Power-On

Reset. During this interval, the PWM outputs are driven to a

three state condition that makes these outputs essentially

open. This state results in no gate drive to the output

MOSFETs.

Applications and Convertor Start-Up

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601B, HIP6602B

HIP6603B or HIP6604B MOSFET driver interfaces with the

HIP6301. For more information, see the HIP6601B or

HIP6602B data sheets.

Once the V

CC

voltage reaches 4.375V (+125mV), a voltage

level to insure proper internal function, the PWM outputs are

enabled and the Soft-Start sequence is initiated. If for any

The HIP6301 is capable of controlling up to 4 PWM power

reason, the V

voltage drops below 3.875V (+125mV), the

CC

channels. Connecting unused PWM outputs to V

CC

POR circuit shuts the converter down and again three states

the PWM outputs.

automatically sets the number of channels. The phase

o

relationship between the channels is 360 /number of active

PWM channels. For example, for three channel operation,

the PWM outputs are separated by 120 . Figure 2 shows the

Soft-Start

o

After the POR function is completed with V

reaching

CC

PWM output signals for a four channel system. In all cases

the maximum duty cycle is 75%.

4.375V, the Soft-Start sequence is initiated. Soft-Start, by its

slow rise in CORE voltage from zero, avoids an overcurrent

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the HIP6301, therefore, the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

FN4765.6

8

December 27, 2004

HIP6301

For the first 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles the PWM output remains low, clamping the lower

output MOSFETs to ground, see Figure 3. The time

variability is due to the Error Amplifier, Sawtooth Generator

and Comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

PWM 1

OUTPUT

DELAY TIME

PGOOD

V

CORE

5V

V

CC

The Soft-Start time or delay time, DT = 2048/F . For an

SW

oscillator frequency, F , of 200kHz, the first 32 cycles or

V

= 12V

SW

IN

160µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of

10.24ms.

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

V COMP

Figure 3 shows the start-up sequence as initiated by a fast

rising 5V supply, V

applied to the HIP6301. Note the

CC,

short rise to the three state level in PWM 1 output during first

32 PWM cycles.

DELAY TIME

PGOOD

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the Channel Frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram on page 2).

V

CORE

5V

V

CC

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is an open drain NMOS

V

= 12V

IN

transistor. On rising V , the pull-up resistor begins to move

CC

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

PGOOD output slightly positive before the NMOS transistor

pulls “down”, generating the slight rise in PGOOD output

voltage.

12V ATX

SUPPLY

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the HIP6301 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the HIP6303 will sense an overcurrent

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

PGOOD

V

CORE

5 V ATX

SUPPLY

V

= 5V, CORE LOAD CURRENT = 31A

FREQUENCY 200kHz

IN

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

FN4765.6

December 27, 2004

9

HIP6301

Overcurrent

Fault Protection

In the event of an overcurrent condition, the overcurrent

protection circuit reduces the average current delivered to

less than 25% of the current limit. When an overcurrent

condition is detected, the controller forces all PWM outputs

into a three state mode. This condition results in the gate

driver removing drive to the output stages. The HIP6301

goes into a wait delay timing cycle that is equal to the Soft-

Start ramp time. PGOOD also goes “low” during this time

due to VSEN going below its threshold voltage. To lower the

average output dissipation, the Soft-Start initial wait time is

increased from 32 to 2048 cycles, then the Soft-Start ramp is

initiated. At a PWM frequency of 200kHz, for instance, an

overcurrent detection would cause a dead time of 10.24ms,

then a ramp of 10.08ms.

The HIP6301 protects the microprocessor and the entire

power system from damaging stress levels. Within the

HIP6301 both Overvoltage and Overcurrent circuits are

incorporated to protect the load and regulator.

Overvoltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE overvoltage condition is detected when the

VSEN pin goes more than 15% above the programmed VID

level.

The overvoltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning V

POR and Soft-Start sequence.

high to initiate a

CC

At the end of the delay, PWM outputs are restarted and the

soft-start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

During a latched overvoltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, resulting in the lower or synchronous rectifier

MOSFETs to conduct and shunt the CORE voltage to

ground to protect the load.

Figure 6 shows the supply shorted under operation and the

hiccup operating mode described above. Note that due to

the high short circuit current, overcurrent is detected before

completion of the start-up sequence so the delay is not quite

as long as the normal Soft-Start cycle.

If after this event, the CORE voltage falls below the

overvoltage limit (plus some hysteresis), the PWM outputs

will three state. The HIP6601B family drivers pass the three

state information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

destructive ringing of the capacitors and output inductors. If

the conditions that caused the overvoltage still persist, the

SHORT APPLIED HERE

PGOOD

SHORT

CURRENT

50A/Div

PWM outputs will be cycled between three state and V

clamped to ground, as a hysteretic shunt regulator.

CORE

HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY

CORE LOAD CURRENT = 31A, 5V LOAD = 5A

SUPPLY FREQUENCY = 200kHz, V = 12V

IN

Undervoltage

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

The VSEN pin also detects when the CORE voltage falls

more than 10% below the VID programmed level. This

causes PGOOD to go low, but has no other effect on

operation and is not latched. There is also hysteresis in this

detection point.

FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP

FN4765.6

10

December 27, 2004

HIP6301

CORE Voltage Programming

The voltage identification pins (VID0, VID1, VID3, and VID4)

Table 1 shows the nominal DAC voltage as a function of the

VID codes. The power supply system is ±1% accurate over

the operating temperature and voltage range.

set the CORE output voltage. Each VID pin is pulled to V

CC

by an internal 20µA current source and accepts open-

collector/open-drain/open-switch-to-ground or standard low-

voltage TTL or CMOS signals.

TABLE 1. VOLTAGE IDENTIFICATION CODES

TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)

VID4

1

VID3

1

VID2

1

VID1

1

VID0

1

VDAC

Off

VID4

0

VID3

1

VID2

1

VID1

1

VID0

1

VDAC

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1

0

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

FN4765.6

11

December 27, 2004

HIP6301

R

IN

C

R

c

FB

COMP

FB

V

IN

HIP6301

SAWTOOTH

COMPARATOR

L

Q1

01

ERROR

AMPLIFIER

GENERATOR

V

-

CORE

PWM

HIP6601B

+

CIRCUIT

CORRECTION

+

PWM

I

L

-

Q2

+

-

PHASE

DIFFERENCE

REFERENCE

DAC

R

ISEN

I

+

CURRENT

SENSING

SEN

-

ONLY ONE OUTPUT

STAGE SHOWN

CURRENT

SENSING

FROM

TO OTHER

CHANNELS

OTHER

CHANNELS

INDUCTOR

CURRENT(S)

FROM

AVERAGING

OTHER

CHANNELS

TO OVER

CURRENT

TRIP

+

-

REFERENCE

COMPARATOR

FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING

Overcurrent, Selecting R

Current Sensing and Balancing

ISEN

The current detected through the R

resistor is averaged

ISEN

Overview

with the current(s) detected in the other 1, 2, or 3 channels.

The averaged current is compared with a trimmed, internally

generated current, and used to detect an overcurrent

condition.

The HIP6301 samples the on-state voltage drop across each

synchronous rectifier FET, Q2, as an indication of the

inductor current in that phase, see Figure 7. Neglecting AC

effects (to be discussed later), the voltage drop across Q2 is

The nominal current through the R

ISEN

50µA at full output load current, and the nominal trip point for

resistor should be

simply r

(Q2) x inductor current (I ). Note that I , the

DS(ON)

L L

inductor current, is either 1/2, 1/3, or 1/4 of the total current

overcurrent detection is 165% of that value, or 82.5µA

(I ), depending on how many phases are in use.

LT

(I )r

(Q2)

DS(ON)

50µA

L

Therefore, R

= ---------------------------------------------- .

The voltage at Q2’s drain, the PHASE node, is applied to the

ISEN

R

resistor to develop the I

current to the HIP6301

ISEN

For a full load of 25A per phase, and an r

DS(ON)

(Q2) of

ISEN pin. This pin is held at virtual ground, so the current

4mΩ, R

= 2kΩ.

ISEN

The overcurrent trip point would be 165% of 25A, or ~ 41A

per phase. The R value can be adjusted to change the

r

(Q2)

DS(ON)

R

through R

is

I

ISEN

current provides ^Iin^Sf^Eo^Nrmation to perform the

= ------------------------------------

L

The I

ISEN

following functions:

overcurrent trip point, but it is suggested to stay within ±25%

of nominal.

1. Detection of an overcurrent condition

2. Reduce the regulator output voltage with increasing load

current (droop)

Droop, Selection of R

IN

The average of the currents detected through the R

ISEN

resistors is also steered to the FB pin. There is no DC return

3. Balance the I currents in multiple channels

L

path connected to the FB pin except for R , so the average

IN

FN4765.6

12

December 27, 2004

HIP6301

current creates a voltage drop across R . This drop

IN

Where: V

= DC value of the output or V voltage

ID

CORE

increases the apparent V

voltage with increasing load

V

= DC value of the input or supply voltage

CORE

IN

current, causing the system to decrease V

to maintain

L = value of the inductor

= switching frequency

CORE

balance at the FB pin. This is the desired “droop” voltage

F

SW

used to maintain V

conditions.

within limits under transient

CORE

Example: For V

=1.6V,

=12V,

CORE

V

IN

With a high dv/dt load transient, typical of high performance

microprocessors, the largest deviations in output voltage

occur at the leading and trailing edges of the load transient.

In order to fully utilize the output-voltage tolerance range, the

output voltage is positioned in the upper half of the range

when the output is unloaded and in the lower half of the

range when the controller is under full load. This droop

compensation allows larger transient voltage deviations and

thus reduces the size and cost of the output filter

components.

L =1.3µH,

= 250kHz,

F

SW

= 4.3A

Then i

PK-PK

25

20

15

10

5

R

should be selected to give the desired “droop” voltage at

IN

the normal full load current 50µA applied through the R

ISEN

resistor (or at a different full load current if adjusted as under

“Overcurrent, Selecting R ” above).

ISEN

R

= Vdroop/50µA

0

IN

For a Vdroop of 80mV, R = 1.6kΩ

IN

The AC feedback components, R and Cc, are scaled in

FB

relation to R

.

IN

Current Balancing

FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH

CURRENT BALANCING DISABLED

The detected currents are also used to balance the phase

currents.

Each phase’s current is compared to the average of all

phase currents, and the difference is used to create an offset

in that phase’s PWM comparator. The offset is in a direction

to reduce the imbalance.

25

20

15

10

5

The balancing circuit can not make up for a difference in

r

between synchronous rectifiers. If a FET has a

DS(ON)

higher r

, the current through that phase will be

DS(ON)

reduced.

Figures 8 and 9 show the inductor current of a two phase

system without and with current balancing.

0

Inductor Current

The inductor current in each phase of a multi-phase Buck

converter has two components. There is a current equal to

FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH

CURRENT BALANCING ENABLED

the load current divided by the number of phases (I / n),

LT

and a sawtooth current, (i

) resulting from switching.

PK-PK

The sawtooth component is dependent on the size of the

inductors, the switching frequency of each phase, and the

values of the input and output voltage. Ignoring secondary

effects, such as series resistance, the peak to peak value of

the sawtooth current can be described by:

The inductor, or load current, flows alternately from V

IN

through Q1 and from ground through Q2. The HIP6301

samples the on-state voltage drop across each Q2 transistor

to indicate the inductor current in that phase. The voltage

drop is sampled 1/3 of a switching period, i/F , after Q1 is

SW

turned OFF and Q2 is turned on. Because of the sawtooth

current component, the sampled current is different from the

average current per phase. Neglecting secondary effects,

2

V

(V

) – V

CORE

IN CORE

i

= ----------------------------------------------------------------

PK – PK

(L)(F

)(V

)

SW

IN

FN4765.6

13

December 27, 2004

HIP6301

the sampled current (I

) can be related to the load

traces minimize the magnitude of voltage spikes. Contact

SAMPLE

current (I ) by:

LT

Intersil for evaluation board drawings of the component

placement and printed circuit board.

I

LT

n

------- + (V )V

– 3V

IN CORE

2

CORE

There are two sets of critical components in a DC-DC

converter using a HIP6301 controller and a HIP6601B gate

driver. The power components are the most critical because

they switch large amounts of energy. Next are small signal

components that connect to sensitive nodes or supply critical

bypassing current and signal coupling.

I

= -----------------------------------------------------------------------------------

SAMPLE

(6L)(F

)(V

)

SW

IN

Where: I = total load current

LT

n = the number of channels

Example: Using the previously given conditions, and

For I =100A,

LT

n =4

1,000

Then I

SAMPLE

= 25.49A

500

As discussed previously, the voltage drop across each Q2

transistor at the point in time when current is sampled is

200

r

(Q2) x I

. The voltage at Q2’s drain, the

DSON

SAMPLE

PHASE node, is applied through the R resistor to the

HIP6301 ISEN pin. This pin is held at virtual ground, so the

current into ISEN is:

ISEN

100

50

(I

)r

(Q2)

SAMPLE DS(ON)

I

= ------------------------------------------------------------------

SENSE

R

ISEN

20

10

(I

)r

(Q2)

SAMPLE DS(ON)

R

= ------------------------------------------------------------------

ISEN

50µA

Example: From the previous conditions,

5

where I

= 100A,

LT

2

1

I

= 25.49A,

= 4mΩ

SAMPLE

r

(Q2)

DS(ON)

Then: R

= 2.04K and

= 165%

ISEN

10

20

50 100 200

500 1,000 2,000 5,000 10,000

(kHz)

CHANNEL OSCILLATOR FREQUENCY, F

I

SW

CURRENT TRIP

FIGURE 10. RESISTANCE R vs FREQUENCY

Short circuit I

= 165A.

T

LT

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

Channel Frequency Oscillator

The channel oscillator frequency is set by placing a resistor,

length of the connections between the input capacitors, C

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the gate driver close to the MOSFETs.

,

IN

R , to ground from the FS/DIS pin. Figure 10 is a curve

T

showing the relationship between frequency, F

and

SW,

resistor R . To avoid pickup by the FS/DIS pin, it is important

T

to place this resistor next to the pin.

The critical small components include the bypass capacitors

for VCC and PVCC on the gate driver ICs. Locate the bypass

Layout Considerations

capacitor, C , for the HIP6301 controller close to the

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

BP

device. It is especially important to locate the resistors

associated with the input to the amplifiers close to their

respective pins, since they represent the input to feedback

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

amplifiers. Resistor R , that sets the oscillator frequency

T

should also be located next to the associated pin. It is

especially important to place the R

resistor(s) at the

SEN

respective terminals of the HIP6301.

A multi-layer printed circuit board is recommended. Figure 11

shows the connections of the critical components for one output

channel of the converter. Note that capacitors C and C

IN OUT

could each represent numerous physical capacitors. Dedicate

one solid layer, usually the middle layer of the PC board, for a

ground plane and make all critical component ground connections

FN4765.6

14

December 27, 2004

HIP6301

with vias to this layer. Dedicate another solid layer as a power

plane and break this plane into smaller islands of common voltage

levels. Keep the metal runs from the PHASE terminal to inductor

bulk capacitor’s ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient’s edge. In most cases, multiple capacitors of small

case size perform better than a single large case capacitor.

L

short. The power plane should support the input power and

O1

output power nodes. Use copper filled polygons on the top and

bottom circuit layers for the phase nodes. Use the remaining

printed circuit layers for small signal wiring. The wiring traces from

the driver IC to the MOSFET gate and source should be sized to

carry at least one ampere of current.

Bulk capacitor choices include aluminum electrolytic, OS-

Con, Tantalum and even ceramic dielectrics. An aluminum

electrolytic capacitor’s ESR value is related to the case size

with lower ESR available in larger case sizes. However, the

equivalent series inductance (ESL) of these capacitors

increases with case size and can reduce the usefulness of

the capacitor to high slew-rate transient loading.

Component Selection Guidelines

Output Capacitor Selection

Unfortunately, ESL is not a specified parameter. Consult the

capacitor manufacturer and measure the capacitor’s

impedance with frequency to select a suitable component.

The output capacitor is selected to meet both the dynamic

load requirements and the voltage ripple requirements. The

load transient for the microprocessor CORE is characterized

by high slew rate (di/dt) current demands. In general,

multiple high quality capacitors of different size and dielectric

are paralleled to meet the design constraints.

Output Inductor Selection

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Small inductors in a multi-phase converter reduces

the response time without significant increases in total ripple

current.

Modern microprocessors produce severe transient load rates.

High frequency capacitors supply the initially transient current

and slow the load rate-of-change seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

The output inductor of each power channel controls the

ripple current. The control IC is stable for channel ripple

current (peak-to-peak) up to twice the average current. A

single channel’s ripple current is approximately:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

V

– V

V

OUT

V

IN

F

OUT

------------------------------- ---------------

∆I =

×

× L

SW

The current from multiple channels tend to cancel each other

and reduce the total ripple current. Figure 12 gives the total

ripple current as a function of duty cycle, normalized to the

parameter (Vo) ⁄ (LxF ) at zero duty cycle. To determine

the total ripple current from the number of channels and the

SW

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

duty cycle, multiply the y-axis value by (Vo) ⁄ (LxF ) .

SW

+5V

IN

USE INDIVIDUAL METAL RUNS

FOR EACH CHANNEL TO HELP

ISOLATE OUTPUT STAGES

+12V

C

BP

VCC PVCC

LOCATE NEXT TO IC PIN(S)

C

BOOT

C

IN

LOCATE NEAR TRANSISTOR

V

CC

L

C

PWM

O1

BP

V

CORE

HIP6601B

PHASE

FS/DIS

COMP

C

OUT

C

T

HIP6301

R

T

R

FB

LOCATE NEXT

TO FB PIN

FB

LOCATE NEXT TO IC PIN

SEN

R

IN

R

VSEN

ISEN

KEY

ISLAND ON POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

ISLAND ON CIRCUIT PLANE LAYER

FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN4765.6

15

December 27, 2004

HIP6301

Small values of output inductance can cause excessive power

dissipation. The HIP6303 is designed for stable operation for

ripple currents up to twice the load current. However, for this

condition, the RMS current is 115% above the value shown in

the following MOSFET Selection and Considerations section.

With all else fixed, decreasing the inductance could increase

the power dissipated in the MOSFETs by 30%.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance for

the high frequency decoupling and bulk capacitors to supply

the RMS current. Small ceramic capacitors should be placed

very close to the drain of the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

For bulk capacitance, several electrolytic capacitors (Panasonic

HFQ series or Nichicon PL series or Sanyo MV-GX or

equivalent) may be needed. For surface mount designs, solid

tantalum capacitors can be used, but caution must be exercised

with regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge-current at

power-up. The TPS series available from AVX, and the 593D

series from Sprague are both surge current tested.

1.0

SINGLE

0.8

0.6

0.4

0.2

0

CHANNEL

2 CHANNEL

MOSFET Selection and Considerations

3 CHANNEL

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the following

equations). The conduction losses are the main component

of power dissipation for the lower MOSFETs, Q2 and Q4 of

Figure 1. Only the upper MOSFETs, Q1 and Q3 have

significant switching losses, since the lower device turns on

and off into near zero voltage.

4 CHANNEL

0.1

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 12. RIPPLE CURRENT vs DUTY CYCLE

Input Capacitor Selection

The important parameters for the bulk input capacitors are the

voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current required for a multi-phase

converter can be approximated with the aid of Figure 13.

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the Driver IC and don't heat the MOSFETs.

However, large gate-charge increases the switching time,

t

which increases the upper MOSFET switching losses.

SW

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

0.5

SINGLE

CHANNEL

0.4

0.3

0.2

0.1

0

type, ambient temperature and air flow.

2 CHANNEL

2

I

× r

× V

I

× V × t

× F

SW SW

O

DS(ON)

OUT

O

IN

P

= ------------------------------------------------------------ + ---------------------------------------------------------

UPPER

LOWER

V

2

IN

3 CHANNEL

2

I

× r

× (V – V

)

OUT

O

DS(ON)

IN

P

= --------------------------------------------------------------------------------

4 CHANNEL

0.1

V

IN

A diode, anode to ground, may be placed across Q2 and Q4

of Figure 1. These diodes function as a clamp that catches

the negative inductor swing during the dead time between

the turn off of the lower MOSFETs and the turn on of the

upper MOSFETs. The diodes must be a Schottky type to

prevent the lossy parasitic MOSFET body diode from

conducting. It is usually acceptable to omit the diodes and let

the body diodes of the lower MOSFETs clamp the negative

inductor swing, but efficiency could drop one or two percent

as a result. The diode's rated reverse breakdown voltage

must be greater than the maximum input voltage.

0.2

0.3

0.4

0.5

0

DUTY CYCLE (V /V

)

IN

O

FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE

First determine the operating duty ratio as the ratio of the

output voltage divided by the input voltage. Find the Current

Multiplier from the curve with the appropriate power

channels. Multiply the current multiplier by the full load

output current. The resulting value is the RMS current rating

required by the input capacitor.

FN4765.6

16

December 27, 2004

HIP6301

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

AREA

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.35

0.23

MAX

2.65

NOTES

E

A

A1

B

C

D

E

e

0.0926

0.0040

0.014

0.1043

0.0118

0.019

-

-B-

0.30

-

0.49

9

1

2

3

L

0.0091

0.4961

0.2914

0.0125

0.32

-

SEATING PLANE

A

0.5118 12.60

13.00

7.60

3

-A-

0.2992

7.40

4

o

D

h x 45

0.050 BSC

1.27 BSC

-

-C-

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

α

µ

5

e

A1

C

L

6

B

0.10(0.004)

N

α

20

7

M

S

B

0.25(0.010)

C

A

o

0

8

0

8

-

Rev. 1 1/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN4765.6

17

December 27, 2004

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