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HM514260C Series

HM51S4260C Series

262,144-word × 16-bit Dynamic Random Access Memory

ADE-203-260A (Z)

Rev. 1.0

Jun. 12, 1995

Description

The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260C

has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process

technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a

high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard

400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables

HM51S4260C self refresh operation.

Features

•

Single 5 V (±10%) (HM51(S)4260C-6/7/8)

(±5%) (HM51(S)4260C-6R)

High speed

— Access time: 60 ns/70 ns/80 ns (max)

Low power dissipation

— Active mode: 825 mW/788 mW/770 mW/688 mW (max)

— Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8)

10.5 mW (max) (HM51(S)4260C-6R)

1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8)

1.05 mW (max) (L-version) (HM51(S)4260C-6R)

Fast page mode capability

•

512 refresh cycles: 8 ms

128 ms (L-version)

•

2 CAS-byte control

2 variations of refresh

— RAS-only refresh

— CAS-before-RAS refresh

•

Battery backup operation (L-version)

Self refresh operation (HM51S4260C)

HM514260C, HM51S4260C Series

Ordering Information

Type No.

Access Time

Package

HM514260CJ-6

HM514260CJ-6R

HM514260CJ-7

HM514260CJ-8

60 ns

70 ns

80 ns

400-mill 40-pin plastic SOJ (CP-40DA)

HM514260CLJ-6

HM514260CLJ-6R

HM514260CLJ-7

HM514260CLJ-8

60 ns

70 ns

80 ns

HM51S4260CJ-6

HM51S4260CJ-6R

HM51S4260CJ-7

HM51S4260CJ-8

60 ns

70 ns

80 ns

HM51S4260CLJ-6

HM51S4260CLJ-6R

HM51S4260CLJ-7

HM51S4260CLJ-8

60 ns

70 ns

80 ns

HM514260CTT-6

HM514260CTT-6R

HM514260CTT-7

HM514260CTT-8

60 ns

70 ns

80 ns

400-mill 44-pin plastic TSOP II (TTP-44/40DB)

HM514260CLTT-6

HM514260CLTT-6R

HM514260CLTT-7

HM514260CLTT-8

60 ns

70 ns

80 ns

HM51S4260CTT-6

HM51S4260CTT-6R

HM51S4260CTT-7

HM51S4260CTT-8

60 ns

70 ns

80 ns

HM51S4260CLTT-6

HM51S4260CLTT-6R

HM51S4260CLTT-7

HM51S4260CLTT-8

60 ns

70 ns

80 ns

2

HM514260C, HM51S4260C Series

Pin Arrangement

HM514260CTT/CLTT Series

HM51S4260CTT/CLTT Series

HM514260CJ/CLJ Series

HM51S4260CJ/CLJ Series

V_CC

I/O0

I/O1

I/O2

I/O3

V_CC

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

9

10

44

43

42

41

40

39

38

37

36

35

V_SS

V_CC

I/O0

I/O1

I/O2

I/O3

V_CC

I/O4

I/O5

I/O6

I/O7

NC

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

I/O15

I/O14

I/O13

I/O12

V_SS

I/O15

I/O14

I/O13

I/O12

V_SS

2

3

4

5

6

I/O11

I/O10

I/O9

I/O11

I/O10

I/O9

I/O8

NC

7

8

9

I/O8

10

11

12

13

LCAS

UCAS

OE

NC

WE

RAS

NC

A0

13

14

15

16

17

18

19

20

21

22

32

31

30

29

28

27

26

25

24

23

NC

WE

LCAS

UCAS

OE

RAS 14

A8

NC

A0

15

16

17

18

19

20

A7

A8

A6

A1

A7

A5

A2

A1

A6

A4

A3

A2

A5

V_SS

V_CC

A3

A4

V_CC

V

SS

(Top view)

Pin Description

Pin Name

Function

A0 to A8

Address input

–Row address

–Column address

–Refresh address

A0 to A8

I/O0 to I/O15

Data-in/data-out

RAS

Row address strobe

UCAS, LCAS

Column address strobe

Read/write enable

Output enable

Power (+5 V)

WE

OE

V_CC

V_SS

NC

Ground

No connection

3

HM514260C, HM51S4260C Series

Block Diagram

Row

Decoder

Decoder Decoder

Decoder

Selector

I/O4

Buffer

I/O11

Buffer

I/O3

I/O2

I/O1

I/O0

I/O15

I/O14

I/O12

I/O13

I/O4

I/O5

I/O6

I/O7

I/O11

I/O10

I/O9

I/O15 I/O14

Buffer Buffer

I/O5

Buffer

I/O10

Buffer

I/O6

Buffer

I/O9

Buffer

I/O8

Buffer

I/O7

Buffer

I/O8

Peripheral Circuit

LCAS

UCAS

OE

WE

RAS

A6,A7,A8

Selector

Address

A0,A1,A2,A3

Address A4,A5

Selector

Row

Decoder

Row

Decoder Decoder

Row

Decoder

Row

Decoder

Row

Decoder Decoder

Row

Decoder

4

HM514260C, HM51S4260C Series

Operation Mode

The HM51(S)4260C series has the following 11 operation modes.

1. Read cycle

2. Early write cycle

3. Delayed write cycle

4. Read- modify-write cycle

5. RAS-only refresh cycle

6. CAS-before-RAS refresh cycle

7. Self refresh cycle(HM51S4260C)

8. Fast page mode read cycle

9. Fast page mode early write cycle

10. Fast page mode delayed write cycle

11. Fast page mode read- modify-write cycle

Inputs

RAS

LCAS

UCAS

WE

D

OE

Output

Open

Operation

H

D

Standby

H

L

H

L

Valid

Standby

L

H

L

Valid

Read cycle

L

L*²

H to L

D

Open

Early write cycle

L

H

Undefined

Valid

Delayed write cycle

Read-modify-write cycle

RAS-only refresh cycle

CAS-before-RAS refresh cycle

Self refresh cycle (HM51S4260C)

L

L to H

L

H

D

Open

H to L

H

L

D

Open

L

H

L

H to L

L

H to L

L

H

L

Valid

Fast page mode read cycle

L*²

H to L

H

D

Open

Fast page mode early write cycle

Fast page mode delayed write cycle

Fast page mode read-modify-write cycle

Read cycle (Output disabled)

H

Undefined

Valid

L to H

H

Open

Notes: 1. H: High(inactive) L: Low(active) D: H or L

2. t_WCS≥ 0 ns

Early write cycle

t_WCS< 0 ns

Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output HIZ control are done independently by each UCAS, LCAS.

ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.

5

HM514260C, HM51S4260C Series

Absolute Maximum Ratings

Parameter

Symbol

V_T

Value

Unit

V

Voltage on any pin relative to V_SS

Supply voltage relative to V_SS

Short circuit output current

Power dissipation

–1.0 to +7.0

50

V_CC

V

Iout

P_T

mA

W

1.0

Operating temperature

Storage temperature

Topr

Tstg

0 to +70

–55 to +125

°C

Recommended DC Operating Conditions (Ta = 0 to +70°C)^*2

Parameter

Symbol

Min

Typ

0

Max

0

Unit

V

Notes

2

Supply voltage

V_SS

0

V_CC(HM51(S)4260C-6/7/8) 4.5

5.0

—

5.5

5.25

6.5

0.8

V

1, 2

1

V_CC(HM51(S)4260C-6R)

4.75

V

Input high voltage

Input low voltage

V_IH

V_IL

2.4

V

–1.0

—

V

1

Notes: 1. All voltage referred to V_SS.

2. The supply voltage with all V_CCpins must be on the same level.

The supply voltage with all V_SSpins must be on the same level.

6

HM514260C, HM51S4260C Series

DC Characteristics (Ta = 0 to 70°C, V_CC= 5 V ±5%, V_SS= 0 V) (HM51(S)4260C-6R)

(Ta = 0 to 70°C, V_CC= 5 V ±10%, V_SS= 0 V)

(HM51(S)4260C-6/7/8)

HM514260C, HM51S4260C

-6/-6R

-7

-8

Parameter

Symbol Min Max Min Max Min Max Unit Test Conditions

Operating

current^{*1, *2}

I_CC1

I_CC2

—

150

2

—

140

2

—

125 mA RAS, UCAS or LCAS cycling

_RC= min

t

Standby current

2

mA TTL interface

RAS, UCAS, LCAS = V_IH

Dout = High-Z

—

1

—

1

—

1

mA CMOS interface

RAS, UCAS, LCAS, WE,

OE ≥ V_CC– 0.2 V

Dout = High-Z

Standby current

(L-version)

I_CC2

200

200 µA

CMOS interface

RAS, UCAS, LCAS, OE,

WE ≥ V_CC– 0.2 V

Dout = High-Z

RAS-only refresh

I_CC3

I_CC5

I_CC6

I_CC7

I_CC10

—

140

5

—

130

5

—

110 mA t_RC= min

current^*2

Standby current^*1

5

mA RAS = V_IH, UCAS or LCAS = V_IL

Dout = enable

CAS-before-RAS

140

150

300

130

300

110 mA t_RC= min

refresh current^*2

Fast page mode

current^{*1, *3}

120 mA t_PC= min

Battery backup

current^*4(Standby

with CBR refresh)

(L-version)

300 µA

Standby: CMOS interface

Dout = High-Z

CBR refresh: t_RC= 250 µs

t_RAS≤ 1 µs, UCAS, LCAS = V_IL

WE, OE = V_IH

Self-refresh mode I_CC11

current

(HM51S4260C)

—

1

—

1

—

1

mA CMOS interface

RAS, UCAS, LCAS ≤ 0.2 V,

Dout = High-Z

Self-refresh mode I_CC11

current

(HM51S4260CL)

200

200 µA

CMOS interface

RAS, UCAS, LCAS ≤ 0.2 V,

Dout = High-Z

7

HM514260C, HM51S4260C Series

DC Characteristics (Ta = 0 to 70°C, V_CC= 5 V ±5%, V_SS= 0 V) (HM51(S)4260C-6R)

(Ta = 0 to 70°C, V_CC= 5 V ±10%, V_SS= 0 V)

(HM51(S)4260C-6/7/8) (cont)

HM514260C, HM51S4260C

-6/-6R

-7

-8

Parameter

Symbol Min Max Min Max Min Max Unit Test Conditions

Input leakage

current

I_LI

–10 10

µA

0 V ≤ Vin ≤ 6.5 V

Output leakage

current

I_LO

0 V ≤ Vout ≤ 6.5 V, Dout = disable

Output high voltage V_OH

Output low voltage V_OL

2.4 V_CC2.4 V_CC2.4 V_CC

0.4 0.4 0.4

V

High Iout = –5.0 mA

0

Low Iout = 4.2 mA

Notes: 1. I_CCdepends on output load condition when the device is selected. I_CCmax is specified at the output

open condition.

2. Address can be changed once or less while RAS = V_IL.

3. Address can be changed once or less while UCAS and LCAS = V_IH.

4. V_IH≥ V_CC– 0.2 V, 0 ≤ V_IL≤ 0.2 V, Address can be changed once or less while RAS = V_IL

5. All the V_CCpins shall be supplied with the same voltage. And all the V_SSpins shall be supplied with

the same voltage.

Capacitance (Ta = +25°C, V_CC= 5 V ±5%) (HM51(S)4260C-6R)

(Ta = +25°C, V_CC= 5 V ±10%) (HM51(S)4260C-6/7/8)

Parameter

Symbol

C_I1

Typ

—

Max

5

Unit

pF

Notes

Input capacitance (Address)

Input capacitance (Clocks)

Output capacitance (Data-in, Data-out)

1

C_I2

—

7

pF

1

C_I/O

—

10

pF

1, 2

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. UCAS and LCAS = V_IHto disable Dout

8

HM514260C, HM51S4260C Series

AC Characteristics (Ta = 0 to 70°C, V_CC= 5 V ±5%, V_SS= 0 V)

(HM51(S)4260C-6R)^{*1, *14, *15, *17, *18}

(Ta = 0 to 70°C, V_CC= 5 V ±10%, V_SS= 0 V)

(HM51(S)4260C-6/7/8)^{*1, *14, *15, *17, *18}

Test Conditions

•

Input rise and fall time: 5 ns

Input timing reference levels: 0.8 V, 2.4 V

Input levels: 0 V, 3 V

Output load: 2 TTL gate + C_L(50 pF) (HM51(S)4260C-6R) (Including scope and jig)

2 TTL gate + C_L(100 pF) (HM51(S)4260-6/7/8) (Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

HM514260C, HM51S4260C

-6/-6R

-7

-8

Parameter

Symbol Min Max

Min Max

Unit Notes

Random read or write cycle time

RAS precharge time

t_RC

110

40

60

15

0

—

130

50

—

150

60

—

ns

t_RP

RAS pulse width

t_RAS

t_CAS

t_ASR

t_RAH

t_ASC

t_CAH

t_RCD

t_RAD

t_RSH

t_CSH

t_CRP

t_ODD

t_DZO

t_DZC

t_T

10000 70

10000 20

10000 80

10000 20

10000 ns

CAS pulse width

23

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS to CAS delay time

RAS to column address delay time

RAS hold time

—

45

30

—

50

8

0

—

50

35

—

50

8

0

—

60

40

—

50

8

ns

ms

10

0

10

0

10

0

19

8

15

20

15

60

10

15

0

15

20

15

20

70

15

20

0

15

20

15

20

80

15

20

0

9

CAS hold time

CAS to RAS precharge time

OE to Din delay time

OE delay time from Din

CAS setup time from Din

Transition time (rise and fall)

Refresh period

20

7

0

3

t_REF

—

Refresh period (L-version)

128

9

HM514260C, HM51S4260C Series

Read Cycle

HM514260C, HM51S4260C

-6/-6R

Symbol Min Max

-7

-8

Parameter

Min Max

Unit Notes

Access time from RAS

Access time from CAS

t_RAC

t_CAC

—

60

15

—

70

20

—

80

20

ns

2, 3

3, 4,

13

Access time from address

t_AA

—

30

—

35

—

40

ns

3, 5,

13

Access time from OE

t_OAC

t_RCS

t_RCH

t_RRH

t_RAL

—

0

15

—

15

—

0

20

—

15

—

0

20

—

15

—

ns

23

Read command setup time

Read command hold time to CAS

Read command hold time to RAS

Column address to RAS lead time

Output buffer turn-off time

Output buffer turn-off to OE

CAS to Din delay time

19

0

16, 19

16

0

30

0

35

0

40

0

t_OFF1

t_OFF2

t_CDD

6

0

15

Write Cycle

HM514260C, HM51S4260C

-6/-6R

Symbol Min Max

-7

-8

Parameter

Min Max

Unit Notes

Write command setup time

Write command hold time

Write command pulse width

Write command to RAS lead time

Write command to CAS lead time

Data-in setup time

t_WCS

t_WCH

t_WP

0

—

0

—

0

—

0

ns

10, 19

19

15

10

20

0

15

10

20

0

15

10

20

0

t_RWL

t_CWL

t_DS

21

11

23

Data-in hold time

t_DH

15

—

15

—

15

—

CAS to OE delay time

t_COD

10

HM514260C, HM51S4260C Series

Read-Modify-Write Cycle

HM514260C, HM51S4260C

-6/-6R

-7

-8

Parameter

Symbol Min Max

Min Max

Unit Notes

Read-modify-write cycle time

RAS to WE delay time

CAS to WE delay time

Column address to WE delay time

OE hold time from WE

t_RWC

t_RWD

t_CWD

t_AWD

t_OEH

150

80

35

50

15

—

180

95

45

60

20

—

200

105

45

—

ns

10

65

10, 13

20

Refresh Cycle

HM514260C, HM51S4260C

-6/-6R

Symbol Min Max

-7

-8

Parameter

Min Max

Unit Note

CAS setup time (CBR refresh cycle)

CAS hold time (CBR refresh cycle)

RAS precharge to CAS hold time

CAS precharge time in normal mode

t_CSR

t_CHR

t_RPC

t_CPN

10

—

10

—

10

—

ns

19

20

19

22

Fast Page Mode Cycle

HM514260C, HM51S4260C

-6/-6R

Symbol Min Max

-7

-8

Parameter

Min Max

Unit Notes

Fast page mode cycle time

Fast page mode CAS precharge time

Fast page mode RAS pulse width

Access time from CAS precharge

t_PC

40

10

—

45

10

—

50

10

—

ns

t_CP

ns

22

12

t_RASC

t_ACP

100000 —

100000 ns

35

—

40

—

45

ns

3, 13,

20

RAS hold time from CAS precharge

t_RHCP

35

55

—

40

65

—

45

70

—

ns

Fast page mode read-modify-write cycle t_CPW

CAS precharge to WE delay time

Fast page mode read-modify-write cycle t_PCM

time

80

—

95

—

100

—

ns

11

HM514260C, HM51S4260C Series

Self refresh Mode

HM51S4260C

-6/-6R

-7

-8

Parameter

Symbol Min Max

Min Max

Unit Notes

RAS pulse width (self refresh)

t_RASS

100

—

100

—

100

—

µs

24, 25,

26

RAS precharge time (self refresh)

CAS hold time (self refresh)

t_RPS

t_CHS

110

—

130

—

150

—

ns

–50

21

Notes: 1. AC measurements assume t_T= 5 ns.

2. Assumes that t_RCD≤ t_RCD(max) and t_RAD≤ t_RAD(max). If t_RCDor t_RADis greater than the maximum

recommended value shown in this table, t_RACexceeds the value shown.

3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF (HM51(S)4260C-6/7/8), 2 TTL

50 pF (HM51(S)4260C-6R).

4. Assumes that t_RCD≥ t_RCD(max) and t_RAD≤ t_RAD(max).

5. Assumes that t_RCD≤ t_RCD(max) and t_RAD≥ t_RAD(max).

6. t_OFF(max) defines the time at which the output achieves the open circuit condition and is not

referred to output voltage levels.

7. V_IH(min) and V_IL(max) are reference levels for measuring timing of input signals. Also, transition

times are measured between V_IHand V_IL.

8. Operation with the t_RCD(max) limit insures that t_RAC(max) can be met, t_RCD(max) is specified as a

reference point only, if t_RCDis greater than the specified t_RCD(max) limit, then access time is

controlled exclusively by t_CAC

.

9. Operation with the t_RAD(max) limit insures that t_RAC(max) can be met, t_RAD(max) is specified as a

reference point only, if t_RADis greater than the specified t_RAD(max) limit, then access time is

controlled exclusively by t_AA.

10. t_WCS, t_RWD, t_CWDand t_AWDare not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only: if t_WCS≥ t_WCS(min), the cycle is an early write cycle and the data out

pin will remain open circuit (high impedance) throughout the entire cycle; if t_RWD≥ t_RWD(min), t_CWD

≥

t

_CWD(min), t_AWD≥ t_AWD(min) and t_CPW≥ t_CPW(min), the cycle is a read-modify-write and the data output

will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,

the condition of the data out (at access time) is indeterminate.

11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge

in a delayed write or a read-modify-write cycle.

12. t_RASCdefines RAS pulse width in fast page mode cycles.

13. Access time is determined by the longest among t_AA, t_CACand t_ACP

.

14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization

cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is

used, a minimum of eight CAS-before-RAS refresh cycles is required.

15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to

the device.

16. Either t_RCHor t_RRHmust be satisfied for a read cycle.

17. When both UCAS and LCAS go low at the same time, all 16-bits data are written into the device.

UCAS and LCAS cannot be staggered within the same write/read cycles.

18. All the V_CCand V_SSpins shall be supplied with the same voltages.

19. t_ASC, t_CAH, t_RCS, t_WCS, t_WCH, t_CSRand t_RPCare determined by the earlier falling edge of UCAS or LCAS.

20. t_CRP, t_CHR, t_ACP, t_RCHand t_CPWare determined by the later rising edge of UCAS or LCAS.

21. t_CWL,t_DH,t_DSand t_CHSshould be satisfied by both UCAS and LCAS.

12

HM514260C, HM51S4260C Series

22. t_CPNand t_CPare determined by the time that both UCAS and LCAS are high.

23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.

When output buffer is turned on and off within a very short time, generally it causes large V_CC/V_SS

line noise, which causes to degrade V_IHmin/V_ILmax level.

24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR

refresh should be executed within 15.6 µs immediately after exiting from and before entering

into self refresh mode.

25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles

of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately

after exiting from and before entering into the self refresh mode.

26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self

refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode

again.

27.

H or L (H: V (min) ≤ V ≤ V (max), L: V (min) ≤ V ≤ V (max))

IH IN IH IL IN IL

Invalid Dout

13

HM514260C, HM51S4260C Series

Notes concerning 2CAS control

Please do not separate the UCAS/LCAS operation timing intentionally. However skew between

UCAS/LCAS are allowed under the following conditions.

(1) Each of the UCAS/LCAS should satisfy the timing specifications individually.

(2) Different operation mode for upper/lower byte is not allowed; such as following.

RAS

Delayed write

UCAS

Early write

LCAS

WE

(3) Closely separated upper/lower byte control is not allowed. However when the condition (t_CP≤ t_UL) is

satisfied, fast page mode can be performed.

RAS

UCAS

LCAS

t

UL

14

HM514260C, HM51S4260C Series

Timing Waveforms^*27

Read Cycle

t

RC

t

RAS

t

RP

t

T

t

RSH

t

CRP

CAS

t

RCD

t

CSH

UCAS

LCAS

t

RAL

ASR

RAD

t

CAH

t

ASC

RAH

Column

Address

Row

t

RCH

RRH

RCS

WE

t

CAC

t

OFF1

AA

High-Z

Dout

Din

t

RAC

t

OFF2

t

CDD

OAC

DZC

High-Z

t

ODD

t

DZO

OE

15

HM514260C, HM51S4260C Series

Early Write Cycle

t

RC

t

RAS

t

RAS

RP

t

T

t

RSH

t

RCD

CAS

t

CRP

t

CSH

UCAS

LCAS

t

ASR

t

ASC

CAH

RAH

Row

Address

Column

t

WCH

WCS

WE

t

DH

DS

Din

High-Z

Dout

: H or L

*

OE

16

HM514260C, HM51S4260C Series

Delayed Write Cycle

t

RC

t

RAS

RP

RAS

t

CRP

CSH

t

T

t

RCD

RSH

t

UCAS

LCAS

CAS

t

CWL

RWL

ASC

ASR

t

RAH

t

CAH

Column

Address

Row

t

RCS

WP

WE

Din

t

DH

t

DS

Din

t

OEH

DZC

t

ODD

t

DZO

High-Z

Dout

OE

*Invalid Dout

t

COD

t

OFF2

* Do not enable Dout during delayed write cycle.

17

HM514260C, HM51S4260C Series

Read-Modify-Write Cycle

t

RWC

t

T

t

RP

RAS

t

CRP

t

RCD

UCAS

LCAS

t

RAD

t

ASR

ASC

t

RAH

CAH

Column

t

Address

Row

t

CWL

RWL

t

RCS

CWD

t

AWD

t

WP

WE

t

AA

t

RWD

t

CAC

DH

t

RAC

t

DS

t

DZC

High-Z

Din

Dout

OE

High-Z

Dout

t

OEH

t

OAC

t

OFF2

ODD

t

DZO

18

HM514260C, HM51S4260C Series

RAS-Only Refresh Cycle

t

RC

t

RP

RAS

t

CRP

T

t

CRP

t

RPC

UCAS

LCAS

t

RAH

t

ASR

Row

Address

Dout

High-Z

: H or L

* OE, WE

** Refresh address : A0 – A8 (AX0 – AX8)

19

HM514260C, HM51S4260C Series

CAS-Before-RAS Refresh Cycle

t

RC

t

**

RP

RAS

RP

RAS

RP

RAS

t

T

t

RPC

CRP

RPC

CPN

t

CHR

CSR

CHR

CPN

CSR

UCAS

LCAS

Address

t

OFF1

High-Z

Dout

: H or L

* WE

_

Do not extend t

> t

(max).

RAS

**

Untested self refresh mode may be

activated and loss of data may be

resulted (HM514260C).

20

HM514260C, HM51S4260C Series

Fast Page Mode Read Cycle

t

RP

RASC

t

RHCP

RAS

t

T

CRP

t

RSH

t

PC

CSH

t

CAS

t

CP

CAS

RCD

CP

CAS

UCAS

LCAS

t

RAD

t

RAL

CAH

t

CAH

t

CAH

t

ASC

t

RAH

t

ASC

ASR

ASC

Address

Row

Column

t

RRH

RCS

t

RCH

RCS

DZC

RCH

WE

t

CDD

t

DZC

t

CDD

t

DZC

CDD

High-Z

Din

t

ODD

t

CAC

AA

CAC

t

ODD

CAC

t

AA

t

ACP

RAC

t

OFF1

t

OFF1

t

DZO

High-Z

Dout

OE

Dout

t

OAC

t

ODD

t

DZO

t

DZO

t

OAC

t

OFF2

t

OFF2

t

OAC

21

HM514260C, HM51S4260C Series

Fast Page Mode Early Write Cycle

t

RP

RASC

RAS

t

PC

RSH

CAS

CSH

t

T

t

CRP

CAS

RCD

CP

CAS

CAH

CP

UCAS

LCAS

t

ASC

t

CAH

t

CAH

ASC

ASR

RAH

ASC

Address

Row

Column

t

WCS

t

WCS

WCH

WCS

WCH

t

WCH

WE

t

DS

t

DH

t

DH

Din

High-Z

Dout

: H or L

*

OE

22

HM514260C, HM51S4260C Series

Fast Page Mode Delayed Write Cycle

t

RP

RASC

RAS

t

CSH

t

RSH

CAS

t

PC

T

t

CRP

t

CP

t

RCD

CAS

CP

CAS

UCAS

LCAS

t

ASC

ASR

t

CAH

t

ASC

t

CAH

t

RAH

t

CWL

t

CAH

ASC

Address

Column

Row

t

CWL

t

CWL

t

WP

t

RCS

t

RWL

WP

WE

t

RCS

t

DH

t

RCS

DH

t

DS

t

DS

Din

Dout

OE

Din

t

OEH

High-Z

t

ODD

23

HM514260C, HM51S4260C Series

Fast Page Mode Read-Modify-Write Cycle

t

RP

RASC

RAS

t

RCD

PCM

t

T

t

CRP

t

CP

UCAS

LCAS

t

RAD

t

RAH

t

ACP

t

CAH

t

CAH

t

ASR

t

ASC

t

ASC

RCS

ASC

Column

t

CPW

Row

Column

Address

t

CWL

RWL

WP

t

CWL

t

AWD

t

AWD

CWD

t

RCS

DZC

t

RCS

t

WP

t

CWD

t

WP

t

CPW

RWD

WE

t

DS

ACP

DZC

DS

t

DS

t

CAC

t

CAC

DZC

t

DH

t

DH

High-Z

AA

High-Z

AA

High-Z

Din

t

Din

t

CAC

t

DZO

RAC

t

OAC

Dout

OFF2

OEH

Dout

OFF2

Dout

OFF2

Dout

t

DZO

OE

t

ODD

24

HM514260C, HM51S4260C Series

Self Refresh Cycle

t

RASS

RP

RPS

RAS

t

T

t

CRP

RPC

CPN

t

CSR

t

CHS

UCAS

LCAS

Address

t

OFF1

High-Z

Dout

*

WE, OE

: H or L

The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore

some care needs to be taken on the refresh.

1.

Please do not use t_RASStiming, 10 µs ≤ t_RASS≤ 100 µs. During this period, the device is in

transition state from normal operation mode to self refresh mode. If t_RASS≥ 100 µs, then RAS

precharge time should use t_RPSinstead of t_RP

.

2.

If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles

of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately

after exiting from and before entering into the self refresh mode.

If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR

refresh should be executed within 15.6 µs immediately after exiting from and before entering

into self refresh mode.

Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from

self refresh mode, all memory cells need to be refreshed before re-entering the self refresh

mode again.

3.

4.

25

HM514260C, HM51S4260C Series

Package Dimensions

HM51(S)4260CJ/CLJ Series (CP-40DA)

Unit: mm

25.80

26.16 Max

40

21

20

1

0.74

1.30 Max

1.27

9.40 ± 0.25

0.43 ± 0.10

0.10

26

HM514260C, HM51S4260C Series

HM51(S)4260CTT/CLTT Series (TTP44/40DB)

Unit: mm

18.41

18.81 Max

44

35 32

23

22

1

10 13

0.80

M

0.13

0.27 ± 0.07

11.76 ± 0.20

1.005 Max

0 – 5°

0.80

0.10

0.50 ± 0.10

27

型号:	HM514260CJ-6
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	HITACHI LTD
零件包装代码：	SOJ
包装说明：	SOJ, SOJ40,.44
针数：	40
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.39
访问模式：	FAST PAGE
最长访问时间：	60 ns
其他特性：	RAS ONLY/CAS BEFORE RAS REFRESH
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J40
JESD-609代码：	e0
长度：	25.8 mm
内存密度：	4194304 bit
内存集成电路类型：	FAST PAGE DRAM
内存宽度：	16
功能数量：	1
端口数量：	1
端子数量：	40
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	256KX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ
封装等效代码：	SOJ40,.44
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
刷新周期：	512
座面最大高度：	3.76 mm
自我刷新：	NO
最大待机电流：	0.001 A
子类别：	DRAMs
最大压摆率：	0.15 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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