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产品型号HM62256BLFP-7ULT的Datasheet PDF文件预览

HM62256B Series  
256k SRAM (32-kword × 8-bit)  
ADE-203-135F (Z)  
Rev. 6.0  
Nov. 13, 1997  
Description  
The Hitachi HM62256B Series is a CMOS static RAM organized 32,768-word × 8-bit. It realizes higher  
performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The  
device, packaged in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with thickness of 1.2 mm, 450 mil SOP (foot  
print pitch width), 600 mil plastic DIP, or 300 mil plastic DIP, is available for high density mounting. It  
offers low power standby power dissipation; therefore, it is suitable for battery backup systems.  
Features  
Single 5.0 V supply: 5.0 V ± 10%  
Access time: 55 ns/70 ns/85 ns (max)  
Power dissipation:  
Active: 25 mW (typ) (f = 1 MHz)  
Standby: 1.0 µW (typ)  
Completely static memory  
No clock or timing strobe required  
Equal access and cycle times  
Common data input and output  
Three state output  
Directly TTL compatible all inputs and outputs  
Battery backup operation  
HM62256B Series  
Ordering Information  
Type No.  
Access time  
70 ns  
Package  
HM62256BLP-7  
HM62256BLP-7SL  
HM62256BLSP-7  
HM62256BLSP-7SL  
HM62256BLFP-7T  
600-mil 28-pin plastic DIP (DP-28)  
70 ns  
70 ns  
300-mil 28-pin plastic DIP (DP-28NA)  
450-mil 28-pin plastic SOP (FP-28DA)  
70 ns  
70 ns  
HM62256BLFP-5SLT  
HM62256BLFP-7SLT  
55 ns  
70 ns  
HM62256BLFP-7ULT  
HM62256BLT-8  
70 ns  
85 ns  
70 ns  
85 ns  
8 mm × 14 mm 32-pin TSOP (TFP-32DA)  
8 mm × 13.4 mm 28-pin TSOP (TFP-28DA)  
HM62256BLT-7SL  
HM62256BLTM-8  
HM62256BLTM-5SL  
HM62256BLTM-7SL  
55 ns  
70 ns  
HM62256BLTM-7UL  
70 ns  
Pin Arrangement  
HM62256BLP/BLFP/BLSP Series  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
WE  
A13  
A8  
A14  
A12  
A7  
2
3
4
A6  
5
A9  
A5  
6
A11  
OE  
A10  
CS  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A4  
7
A3  
8
A2  
9
A1  
10  
11  
12  
13  
14  
A0  
I/O0  
I/O1  
I/O2  
VSS  
(Top view)  
2
HM62256B Series  
Pin Arrangement (cont.)  
HM62256BLT Series  
OE  
A11  
NC  
A9  
A10  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CS  
2
NC  
3
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
VSS  
I/O2  
I/O1  
I/O0  
A0  
4
A8  
5
A13  
WE  
VCC  
A14  
A12  
A7  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
A6  
A5  
NC  
A4  
NC  
A1  
A3  
A2  
(Top view)  
HM62256BLTM Series  
A10  
CS  
OE  
A11  
A9  
22  
23  
24  
25  
26  
27  
28  
1
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A8  
A13  
WE  
V
CC  
V
A14  
A12  
A7  
SS  
I/O2  
I/O1  
I/O0  
A0  
2
3
A6  
4
A5  
5
A1  
A2  
A4  
6
A3  
7
8
(Top view)  
Pin Description  
Pin Name  
A0 to A14  
I/O0 to I/O7  
CS  
Function  
Address input  
Data input/output  
Chip select  
WE  
Write enable  
Output enable  
Power supply  
Ground  
OE  
VCC  
VSS  
NC  
No connection  
3
HM62256B Series  
Block Diagram  
VCC  
VSS  
(MSB) A12  
A5  
A7  
Memory Matrix  
A6  
Row  
Decoder  
×
512 512  
A8  
A13  
A14  
A4  
(LSB) A3  
I/O0  
Column I/O  
Input  
Data  
Control  
Column Decoder  
I/O7  
A1 A0 A10 A9 A11  
A2  
(LSB)  
(MSB)  
Timing Pulse Generator  
Read/Write Control  
CS  
WE  
OE  
4
HM62256B Series  
Operation Table  
WE  
×
CS  
H
L
OE  
×
Mode  
VCC current  
I/O pin  
High-Z  
High-Z  
Dout  
Ref. cycle  
Standby  
ISB, ISB1  
H
H
L
H
L
Output disable ICC  
L
Read  
Write  
Write  
ICC  
ICC  
ICC  
Read cycle (1)to (3)  
Write cycle (1)  
Write cycle (2)  
L
H
L
Din  
L
L
Din  
Note: ×: H or L  
Absolute Maximum Ratings  
Parameter  
Symbol  
Value  
–0.5 to +7.0  
Unit  
Power supply voltage relative to VSS  
VCC  
V
Terminal voltage on any pin relative to VSS VT  
–0.5*1 to VCC+0.3*2  
V
Power dissipation  
PT  
1.0  
W
°C  
°C  
°C  
Operating temperature range  
Storage temperature range  
Storage temperature range under bias  
Topr  
Tstg  
Tbias  
0 to +70  
–55 to +125  
–10 to +85  
Notes: 1. VT min: –3.0 V for pulse half-width 50 ns  
2. Maximum voltage is 7.0 V  
DC Operating Conditions (Ta = 0 to +70°C)  
Parameter  
Symbol  
VCC  
Min  
4.5  
Typ  
5.0  
0
Max  
5.5  
Unit  
V
Notes  
Supply voltage  
VSS  
0
0
V
Input high voltage  
Input low voltage  
VIH  
2.2  
–0.5*1  
VCC + 0.3  
0.8  
V
VIL  
V
Note: 1. VIL min: –3.0 V for pulse half-width 50 ns  
5
HM62256B Series  
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)  
Parameter  
Symbol Min  
Typ*1  
Max  
1
Unit Test conditions  
Input leakage current  
Output leakage current  
|ILI|  
µA  
µA  
Vin = VSS to VCC  
|ILO|  
1
CS = VIH or OE = VIH or WE = VIL,  
VI/O = VSS to VCC  
Operating current  
ICC  
6
15  
60  
mA  
mA  
CS = VIL, Others = VIH/VIL,  
II/O = 0 mA  
Average HM62256B-5  
operating  
current  
ICC1  
Min cycle, duty = 100%,II/O = 0 mA,  
CS = VIL, Others = VIH/VIL  
HM62256B-7  
HM62256B-8  
ICC1  
ICC1  
ICC2  
33  
29  
5
60  
50  
15  
mA  
mA  
mA  
Cycle time = 1 µs, II/O = 0 mA,  
CS = VIL, VIH = VCC, VIL = 0  
Standby current  
ISB  
2.4  
0.3  
0.2  
0.2*2  
0.2*3  
2
mA  
µA  
µA  
µA  
V
CS = VIH  
ISB1  
ISB1  
ISB1  
VOL  
VOH  
100  
50*2  
10*3  
0.4  
Vin 0 V, CS VCC – 0.2 V  
Output low voltage  
Output high voltage  
IOL = 2.1 mA  
V
IOH = –1.0 mA  
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.  
2. This characteristic is guaranteed only for L-SL version.  
3. This characteristic is guaranteed only for L-UL version.  
Capacitance (Ta = 25°C, f = 1.0 MHz)  
Parameter  
Symbol Min  
Typ  
Max  
8
Unit  
pF  
Test Conditions  
Vin = 0 V  
Input capacitance*1  
Input/output capacitance*1  
Cin  
CI/O  
10  
pF  
VI/O = 0 V  
Note: 1. This parameter is sampled and not 100% tested.  
6
HM62256B Series  
AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10%)  
Test Conditions  
Input pulse levels: 0.8 V to 2.4 V  
Input rise and fall time: 5 ns  
Input and output timing reference levels: 1.5 V  
Output load: 1 TTL Gate + CL (50 pF) (HM62256B-5)  
1 TTL Gate + CL (100 pF) (HM62256B-7/8)  
(Including scope & jig)  
Read Cycle  
HM62256B  
-5  
-7  
-8  
Parameter  
Symbol Min Max Min Max Min  
Max Unit  
Notes  
Read cycle time  
tRC  
55  
5
55  
55  
35  
20  
20  
70  
10  
5
70  
70  
40  
25  
25  
85  
10  
5
85  
85  
45  
30  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
tAA  
Chip select to access time  
Output enable to output valid  
Chip select to output in low-Z  
Output enable to output in low-Z  
Chip deselect to output in high-Z  
Output disable to output in high-Z  
Output hold from address change  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
2
5
2
0
0
0
1, 2  
1, 2  
0
0
0
5
5
5
7
HM62256B Series  
Write Cycle  
HM62256B  
-5  
-7  
-8  
Parameter  
Symbol Min Max Min Max Min  
Max Unit  
Notes  
Write cycle time  
tWC  
tCW  
tAS  
55  
40  
0
20  
20  
70  
60  
0
25  
25  
85  
75  
0
30  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip selection to end of write  
Address setup time  
5
6
Address valid to end of write  
Write pulse width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
40  
35  
0
60  
50  
0
75  
55  
0
4, 13  
7
Write recovery time  
Write to output in high-Z  
Data to write time overlap  
Data hold from write time  
Output active from end of write  
Output disable to output in High-Z  
0
0
0
1, 2, 8  
25  
0
30  
0
35  
0
tOW  
tOHZ  
5
5
5
2
0
0
0
1, 2, 8  
Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions  
and are not referred to output voltage levels.  
2. This parameter is sampled and not 100% tested.  
3. Address must be valid prior to or simultaneously with CS going low.  
4. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest  
transition of CS going low or WE going low. A write ends at the earliest transition of CS going  
high or WE going high. tWP is measured from the beginning of write to the end of write.  
5. tCW is measured from CS going low to the end of write.  
6. tAS is measured from the address valid to the beginning of write.  
7. tWR is measured from the earliest of CS or WE going high to the end of write cycle.  
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite  
phase to the outputs must not be applied.  
9. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in  
the high impedance state.  
10. Dout is the same phase of the latest written data in this write cycle.  
11. Dout is the read data of next address.  
12. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the  
opposite phase to the outputs must not be applied to them.  
13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of  
data bus contention.  
t
WP tDW min + tWHZ max  
8
HM62256B Series  
Timing Waveform  
Read Timing Waveform (1) (WE = VIH)  
tRC  
Address  
Valid address  
tAA  
tACS  
CS  
tOH  
tOE  
tOLZ  
OE  
tOHZ  
tCHZ  
High impedance  
Dout  
Valid data  
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)  
tRC  
Valid address  
Address  
Dout  
tAA  
tOH  
tOH  
Valid data  
9
HM62256B Series  
Read Timing Waveform (3) (WE = VIH, OE = VIL)*3  
tACS  
CS  
tCLZ  
tCHZ  
High impedance  
Dout  
Valid data  
Write Timing Waveform (1) (OE Clock)  
tWC  
Address  
Valid address  
tAW  
tWR  
OE  
CS  
tCW  
*9  
tAS  
tWP  
WE  
Dout  
Din  
tOHZ  
High impedance  
tDW  
tDH  
High impedance  
Valid data  
10  
HM62256B Series  
Write Timing Waveform (2) (OE Low Fixed)  
tWC  
Address  
Valid address  
tCW  
tWR  
CS  
*9  
tAW  
tOH  
tWP  
WE  
tAS  
tWHZ  
tOW  
*11  
*10  
Dout  
tDW  
tDH  
*12  
High impedance  
Din  
Valid data  
11  
HM62256B Series  
Low VCC Data Retention Characteristics (Ta = 0 to 70°C)  
Parameter  
Symbol  
Min  
Typ*1  
Max  
Unit  
Test conditions*6  
VCC for data retention  
VDR  
2.0  
5.5  
V
CS VCC – 0.2 V,  
Vin 0V  
Data retention current  
ICCDR  
0.05  
30*2  
µA  
VCC = 3.0 V, Vin 0V  
CS VCC – 0.2 V  
ICCDR  
ICCDR  
tCDR  
0
0.05  
0.05  
10*3  
3*4  
µA  
µA  
ns  
Chip deselect to data  
retention time  
See retention Waveform  
Operation recovery time  
tR  
tRC*5  
ms  
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.  
2. 10 µA max. at Ta = 0 to +40°C.  
3. This characteristic is guaranteed only for L-SL version, 3 µA max. at Ta = 0 to +40°C.  
4. This characteristic is guaranteed only for L-UL version, 0.6 µA max. at Ta = 0 to +40°C.  
5. tRC = Read cycle time.  
6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention  
mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.  
Low VCC Data Retention Timing Waveform  
Data retention mode  
VCC  
4.5V  
tCDR  
tR  
2.2V  
VDR  
CS  
CS VCC 0.2V  
0V  
12  
HM62256B Series  
Package Dimensions  
HM62256BLP Series (DP-28)  
Unit: mm  
35.6  
36.5 Max  
28  
15  
14  
1
1.2  
1.9 Max  
15.24  
+ 0.11  
– 0.05  
0.25  
2.54 ± 0.25  
0.48 ± 0.10  
0° – 15°  
Hitachi Code  
JEDEC  
EIAJ  
DP-28  
Conforms  
Weight (reference value) 4.6 g  
13  
HM62256B Series  
Package Dimensions (cont.)  
HM62256BLSP Series (DP-28NA)  
Unit: mm  
36.00  
37.32 Max  
28  
15  
14  
1
1.30  
2.20 Max  
7.62  
+ 0.11  
– 0.05  
0.25  
0.48 ± 0.10  
2.54 ± 0.25  
0° – 15°  
Hitachi Code  
JEDEC  
DP-28NA  
EIAJ  
Conforms  
Weight (reference value) 2.2 g  
14  
HM62256B Series  
Package Dimensions (cont.)  
HM62256BLFP Series (FP-28DA)  
Unit: mm  
18.00  
18.75 Max  
15  
28  
1
14  
11.80 ± 0.30  
1.12 Max  
1.70  
0° – 8°  
1.27  
1.00 ± 0.20  
0.15  
0.40 ± 0.08  
0.38 ± 0.06  
M
0.20  
Hitachi Code  
FP-28DA  
JEDEC  
EIAJ  
Conforms  
Conforms  
Dimension including the plating thickness  
Base material dimension  
Weight (reference value) 0.82 g  
15  
HM62256B Series  
Package Dimensions (cont.)  
HM62256BLT Series (TFP-32DA)  
Unit: mm  
8.00  
8.20 Max  
17  
32  
1
16  
0.50  
0.22 ± 0.08  
0.20 ± 0.06  
0.08  
M
0.80  
14.00 ± 0.20  
0.45 Max  
0° – 5°  
0.50 ± 0.10  
0.10  
Hitachi Code  
JEDEC  
EIAJ  
TFP-32DA  
Conforms  
Conforms  
Dimension including the plating thickness  
Base material dimension  
Weight (reference value) 0.26 g  
16  
HM62256B Series  
Package Dimensions (cont.)  
HM62256BLTM Series (TFP-28DA)  
Unit: mm  
8.00  
8.20 Max  
8
21  
22  
7
28  
1
0.55  
0.22 ± 0.05  
0.20 ± 0.04  
0.10 M  
0.80  
13.40 ± 0.30  
0.63 Max  
0° – 5°  
0.50 ± 0.10  
0.10  
Hitachi Code  
TFP-28DA  
JEDEC  
EIAJ  
Dimension including the plating thickness  
Base material dimension  
Weight (reference value) 0.22 g  
17  
HM62256B Series  
When using this document, keep the following in mind:  
1. This document may, wholly or partially, be subject to change without notice.  
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of  
this document without Hitachi’s permission.  
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any  
other reasons during operation of the user’s unit according to this document.  
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and  
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual  
property claims or other problems that may result from applications based on the examples described  
herein.  
5. No license is granted by implication or otherwise under any patents or other rights of any third party or  
Hitachi, Ltd.  
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL  
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.  
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are  
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL  
APPLICATIONS.  
Hitachi, Ltd.  
Semiconductor & IC Div.  
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan  
Tel: Tokyo (03) 3270-2111  
Fax: (03) 3270-5109  
For further information write to:  
Hitachi America, Ltd.  
Semiconductor & IC Div.  
2000 Sierra Point Parkway  
Brisbane, CA. 94005-1835  
U S A  
Hitachi Europe GmbH  
Continental Europe  
Dornacher Straße 3  
D-85622 Feldkirchen  
München  
Hitachi Europe Ltd.  
Electronic Components Div.  
Northern Europe Headquarters  
Whitebrook Park  
Lower Cookham Road  
Maidenhead  
Berkshire SL6 8YA  
United Kingdom  
Tel: 01628-585000  
Fax: 01628-585160  
Hitachi Asia Pte. Ltd.  
16 Collyer Quay #20-00  
Hitachi Tower  
Singapore 049318  
Tel: 535-2100  
Tel: 415-589-8300  
Fax: 415-583-4207  
Tel: 089-9 91 80-0  
Fax: 089-9 29 30-00  
Fax: 535-1533  
Hitachi Asia (Hong Kong) Ltd.  
Unit 706, North Tower,  
World Finance Centre,  
Harbour City, Canton Road  
Tsim Sha Tsui, Kowloon  
Hong Kong  
Tel: 27359218  
Fax: 27306071  
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.  
18  
HM62256B Series  
Revision Record  
Rev. Date  
Contents of Modification  
Initial Issue  
Drawn by Approved by  
0.0  
1.0  
Sep. 10, 1993  
Mar. 23, 1994  
Y. Saito  
Y. Saito  
K. Yoshizaki  
K. Yoshizaki  
DC Characteristics  
I
CC1 Typ: —/—/—/— mA to 33/29/26/24 mA  
2.0  
Oct. 31, 1994  
Deletion of HM62256BLT-7/10SL/12SL  
Addition of HM62256BLTM-8/7SL/8SL(TFP-28DA)  
AC Characteristics  
Y. Saito  
K. Yoshizaki  
Addition of note 12  
Low VCC data retention characteristics  
V
DR max: — to 5.5 V  
Note 2: 20 µA max at Ta = 0 to +40°C  
to 10 µA max at Ta = 0 to +40°C  
Deletion of description; (only for L-version)  
3.0  
Jun. 19, 1995  
Change of format  
M. Higuchi K. Yoshizaki  
Deletion of HM62256BLP-8/10/12/8SL/10SL/12SL  
Deletion of HM62256BLSP-8/10/12/8SL/10SL/12SL  
Deletion of HM62256BLFP-8T/10T/12T  
Deletion of HM62256BLFP-8SLT/10SLT/12SLT  
Deletion of HM62256BLT-10/12/8SL  
Deletion of HM62256BLTM-8SL  
Addition of HM62256BLFP-4SLT/5SLT/7ULT  
Addition of HM62256BLTM-4SLT/5SLT/7ULT  
Features  
Fast access time: 70/85/100/120 ns  
to 45/55/70/85 ns  
DC Characteristics  
I
I
CC1 typ: 33/29/26/24 mA to —/—/33/29 mA  
max: 60/50/50/45 mA to 70/60/60/50 mA  
SB1 typ: 0.3/0.3 µA to 0.2/0.2/0.2 µA  
max: 100/50 µA to 100/50/10 µA  
Addition of note 3  
AC Characteristics  
Change order of notes.  
Test Condition  
Addition of HM62256B-4: 1TTL Gate + CL (100pF)  
(Including scope & jig)  
t
RC min: 70/85/100/120 ns to 45/55/70/85 ns  
tAA max: 70/85/100/120 ns to 45/55/70/85 ns  
t
t
t
ACS max: 70/85/100/120 ns to 45/55/70/85 ns  
OE max: 40/45/50/60 ns to 30/35/40/45 ns  
CLZ min: 10/10/10/10 ns to 5/5/10/10 ns  
tOHZ max: 25/30/35/40 ns to 20/20/25/30 ns  
tOH min: 5/5/10/10 ns 5/5/5/5 ns  
t
t
t
t
t
WC min: 70/85/100/120 ns to 45/55/70/85 ns  
CW min: 60/75/80/85 ns to 35/40/60/75 ns  
AW min: 60/75/80/85 ns to 35/40/60/75 ns  
WP min: 50/55/60/70 ns to 30/35/50/55 ns  
WHZ max: 25/30/35/40 ns to 20/20/25/30 ns  
19  
HM62256B Series  
Revision Record (cont.)  
Rev. Date  
Contents of Modification  
Drawn by Approved by  
3.0  
Jun. 19, 1995  
AC Characteristics  
M. Higuchi K. Yoshizaki  
tPW min: 30/35/40/50 ns to 20/25/30/35 ns  
tOHZ max: 25/30/35/40 ns to 20/20/25/30 ns  
Low VCC Data Retention Characteristics  
Addition of note 4.  
tCCDR typ: 0.2/0.2 µA to 0.05/0.05/0.05 µA  
max: 30/10 µA to 30/10/3 µA  
4.0  
Nov. 29, 1995  
Ordering Information (HM62256BLFP-4 Series)  
Addition of note (Under development)  
AC Characteristics  
M. Higuchi K. Yoshizaki  
Test Conditions  
HM62256-5/7/8:1TTL Gate + CL (100pF) to  
HM62256-5:1TTL Gate + CL (50pF) and  
HM62256-7/8:1TTL Gate + CL (100pF)  
5.0  
6.0  
Jul. 9, 1997  
Change of format  
Deletion of HM62256B-4 Series  
M. Higuchi K. Imato  
Nov. 13,1997  
Operation Table  
Correct Error  
DC Operating Conditions  
Correct Error  
DC Characteristics  
Correct Error  
20  
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