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北京元坤伟业科技有限公司
HM6287HLP-25
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010-62104931、62106431、62104891、62104791

深圳市中利达电子科技有限公司
HM6287HLP-25
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0755-13686833545

深圳市芯福林电子有限公司
HM6287HLP-25
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13418564337

首天国际（深圳）科技有限公司
HM6287HLP-25
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0755-82807802/82807803

柒号芯城电子商务（深圳）有限公司
HM6287HLP-25
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18922803401

深圳市华芯盛世科技有限公司
HM6287HLP-25

数量865000
厂家HIT
封装原厂封装
批号最新批号
一级代理,原装特价现货！
QQ：2881475757 复制
0755-83225692

深圳市毅创腾电子科技有限公司
HM6287HLP-25

数量3000
厂家DIP24
封装1806+
批号22+
★只做原装★正品现货★原盒原标★
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86-755-83616256

上海金庆电子技术有限公司
HM6287HLP-25

数量20
厂家HIT
封装DIP
批号新
全新原装货期两周
QQ：1484215649 复制
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021-51872561

深圳市楷兴电子科技有限公司
HM6287HLP-25

数量10500
厂家DIP24
封装1806+
批号22+
原装现货库存可出样品
QQ：2881475151 复制
0755-83016042

深圳市瑞天芯科技有限公司
HM6287HLP-25

数量20000
厂家DIP24
封装1806+
批号22+
深圳现货库存，保证原装正品
QQ：1940213521 复制
15973558688

深圳市一线半导体有限公司
HM6287HLP-25

数量24500
厂家原厂品牌
封装原厂外观
批号
全新原装部分现货其他订货
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0755-88608801多线

深圳市科雨电子有限公司
HM6287HLP-25

数量9800
厂家HITACHI
封装DIP-22
批号24+
原厂渠道，全新原装现货，欢迎查询！
QQ：97877805 复制
171-4729-0036（微信同号）

产品型号HM6287HLP-25的Datasheet PDF文件预览

HM6287, HM6287H Series

65536-word × 1-bit High Speed CMOS Static RAM

Description

The Hitachi HM6287/HM6287H is a high speed 64 k static RAM organized as 64-kword × 1-bit. It realizes

high speed access time (25/35/45/55/70 ns) and low power consumption, employing CMOS process

technology and high speed circuit design technology. It is most advantageous for high speed and high density

memory, such as cache memory for mainframes or 32-bit MPUs. The HM6287/HM6287H is packaged in a

300-mil plastic DIP and SOJ, and is available for high density mounting. The low power version retains data

with battery backup.

Features

•

Single 5 V supply and high density 22-pin DIP and 24-pin SOJ

High speed: Fast access time 25/35/45/55/70 ns (max)

Low power

Operation: 300 mW (typ)

Standby: 100 µW (typ)/10 µW (typ) (L-version)

Completely static memory

•

No clock or timing strobe required

Equal access and cycle times

Directly TTL compatible: All inputs and outputs

Battery backup capability (L-version)

HM6287, HM6287H Series

Ordering Information

Type No.

Access Time

Package

HM6287P-45

HM6287P-55

HM6287P-70

45 ns

55 ns

70 ns

300-mil, 22-pin plastic DIP (DP-22N)

HM6287LP-45

HM6287LP-55

HM6287LP-70

45 ns

55 ns

70 ns

HM6287HP-25

HM6287HP-35

25 ns

35 ns

300-mil, 22-pin plastic DIP (DP-22NB)

300-mil, 24-pin SOJ (CP-24D)

HM6287HLP-25

HM6287HLP-35

25 ns

35 ns

HM6287HJP-25

HM6287HJP-35

25 ns

35 ns

HM6287HLJP-25

HM6287HLJP-35

25 ns

35 ns

Pin Arrangement

HM6287P/HP Series

HM6287HJP

V_CC

A15

A14

A15

A14

A13

A12

A11

A10

A13

A12

A11

A10

Dout

Din

V_SS

(Top view)

HM6287, HM6287H Series

Pin Description

Pin Name

A0–A15

Din

Function

Address

Input

Dout

Output

Chip select

Write enable

Power supply

Ground

V_CC

V_SS

Block Diagram

V_CC

V_SS

Memory array

128 × 512

Row

decoder

Dout

Column I/O

Din

Column decoder

A15

Truth Table

Mode

Standby

Read

V_CCcurrent

I_SB, I_SB1

I_CC

Dout pin

Ref. Cycle

—

High-Z

Dout

Read cycle 1, 2

Write cycle 1, 2

Write

I_CC

High-Z

Note: ×: Don't care.

HM6287, HM6287H Series

Absolute Maximum Ratings

Parameter

Symbol

V_T

Value

–0.5^*to +7.0

Unit

Voltage any pin relative to V_SS

Power dissipation

P_T

1.0

Operating temperature

Storage temperature

Storage temperature under bias

Topr

Tstg

Tbias

0 to +70

–55 to +125

–10 to +85

°C

Note: V_Tmin: –3.5 V for pulse width ≤ 20 ns (HM6287 Series)

V_Tmin: –2.0 V for pulse width ≤ 10 ns (HM6287H Series)

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

V_CC

Min

4.5

Typ

5.0

Max

5.5

Unit

Supply voltage

V_SS

Input high (logic 1) voltage

Input low (logic 0) voltage

V_IH

2.2

–0.5^*1

—

6.0

0.8

V_IL

—

Note: 1. V_ILmin: –3.0 V for pulse width ≤ 20 ns (HM6287 Series)

V_ILmin: –2.0 V for pulse width ≤ 10 ns (HM6287H Series)

DC Characteristics (Ta = 0 to +70°C, V_CC= 5 V ± 10%, V_SS= 0 V)

HM6287

HM6287H

Typ^*1Max Unit Test Conditions

Parameter

Symbol Min

Typ*¹Max Min

Input leakage current

|I_LI|

—

2.0

—

2.0

µA V_CC= Max

Vin = V_SSto V_CC

Output leakage current |I_LO|

—

2.0

—

2.0

µA CS = V_IH, V_I/O= V_SSto V_CC

Operating V_CCcurrent

I_CC

100

120

mA CS = V_IL, Iout = 0 mA,

min cycle

Standby V_CCcurrent

I_SB

—

mA CS = V_IH, min. cycle

mA CS ≥ V_CC– 0.2 V

Standby V_CCcurrent (1) I_SB1

—

0.02 2.0

—

0.02 2.0

0.02^*20.1^*2

0.02^*20.1^*2mA 0 V ≤ Vin ≤ 0.2 V

or V_CC– 0.2 V≤ V_in

Output low voltage

Output high voltage

V_OL

V_OH

—

0.4

—

0.4

—

I_OL= 8 mA

2.4

I_OH= –4.0 mA

Notes: 1. Typical values are at V_CC= 5.0 V, Ta = +25°C and not guaranteed.

2. These characteristics are guaranteed only for L-version.

HM6287, HM6287H Series

Capacitance (Ta = 25°C, f = 1.0 MHz)^*1

HM6287

HM6287H

Parameter

Symbol

Cin

Min

—

Max

Min

—

Max

Unit Test Conditions

Input capacitance

Output capacitance

Vin = 0 V

Cout

—

7.5

—

Vout = 0 V

Note: 1. These parameters are sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70°C, V_CC= 5 V ± 10%, unless otherwise noted.)

Test Conditions

•

Input pulse levels: V_SSto 3.0 V

Input and output timing reference levels: 1.5 V

Input rise and fall time: 5 ns

Output load: See figure

+ 5 V

480 Ω

Dout

30 pF ^*1

5 pF ^*1

255 Ω

Output load (A)

Output load (B)

(for t_HZ,t_{LZ, WZ}and t_OW)

Note: 1. Including scope and jig

HM6287, HM6287H Series

Read Cycle

HM6287H- HM6287H- HM6287- HM6287- HM6287-

25 35 45 55 70

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Read cycle time

t_RC

t_AA

—

Address access time

Chip select access time

t_ACS

Output hold from address t_OH

change

Chip selection to output in t_LZ

low-Z

—

1, 3, 4

Chip deselection to output t_HZ

in high-Z

1, 3, 4

Chip selection to power- t_PU

up time

Chip deselection to power t_PD

down time

—

Notes: 1. Transistion is measured +200 mV from steady state voltage with load (B).

2. All read cycle timing is referenced from last valid address to the first transitioning address.

3. At any given temperature and voltage condition, t_HZmax, is less the t_LZmin both for a given device

and from device to device.

4. These parameters are sampled and not 100% tested.

Read Timing Waveform (1)

t_RC

Address

Dout

t_AA

t_OH

Previous data valid

Valid Data

Notes: 1. WE is high for read cycle.

2. Device is continously selected, CS = V_IL.

3. All read cycle timing is referred from last valid address to the first transitioning address.

HM6287, HM6287H Series

Read Timing Waveform (2)

t_RC

t_HZ

t_ACS

t_LZ

Valid Data

Dout

V_CC

supply

current

I_SB

High impedance

t_PU

High

impedance

t_PD

I_CC

50%

Notes: 1. WE is high for read cycle.

2. Address valid prior to or coincident with CS transistion low.

Write Cycle

HM6287H- HM6287H- HM6287- HM6287- HM6287-

25 35 45 55 70

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write cycle time

t_WC

t_CW

—

Chip selection to endof

write

Address valid to end of

write

t_AW

—

Address setup time

Write pulse width

Write recovery time

t_AS

—

t_WP

t_WR

Data valid to end of write t_DW

Data hold time t_DH

Write enabled to output in t_WZ

high-Z

Output active from end of t_OW

write

—

Notes: 1. All write cycle timing is referenced from the last valid address to first transitioning address.

2. Transition is measured ±200 mV from steady state voltage with load B. These parameters are

sampled and not 100% tested.

HM6287, HM6287H Series

Write Timing Waveform (1) (WE Controlled)

t_WC

Address

t_CW

t_AW

t_WR

t_AS

t_WP

t_DH

t_DW

Valid Data

Din

t_WZ

t_OW

High impedance

t_OH

Dout

Notes: 1. A write occurs during the overlap of a low CS and a low WE (t_WP).

2. t_WRis measured from the earlier of CS or WE going high to the end of the write cycle.

3. Dout is the same phase of write data of this write cycle, if t_WRis long enough.

HM6287, HM6287H Series

Write Timing Waveform (2) (CS Controlled)

t_WC

Address

t_AW

t_WR

t_AS

t_CW

t_WP

t_DW

t_DH

Din

Valid Data

High impedance ^*3

Dout

Notes: 1. A write occurs during the overlap of a low CS and a low WE (t_WP).

2. t_WRis measured from the earlier of CS or WE going high to the end of the write cycle.

3. If CS low transition occurs simultaneously with the WE low transition or after the WE

transition, the output buffers remain in a high impedance state.

HM6287, HM6287H Series

Low V_CCData Retention Characteristics (Ta = 0 to +70°C)

These specifications are guaranteed only for L-version.

Parameter

Symbol

Min

Typ

Max Unit Test conditions

V_CCfor data retention

V_DR

2.0

—

CS ≥ V_CC– 0.2 V,

0 V ≥ Vin – 0.2 V,

or 0 V ≤ Vin ≤ 0.2V

Data retention current

I_CCDR

—

50^*2

35^*3

—

µA

Chip deselect to data retention time

Operation recovery time

t_CDR

t_R

See retention waveform

t_RC

—

Notes: 1. t_RC= Read cycle time

2. V_CC= 3.0 V

3. V_CC= 2.0 V

Low V_CCData Retention Waveform

Data retention mode

V_CC

4.5 V

t_CDR

t_R

V_DR

2.2 V

CS ≥ V_DR– 0.2 V

0 V

HM6287, HM6287H Series

Package Dimensions

HM6287P/LP Series (DP-22N)

Unit: mm

27.08

27.90 Max

0.88

1.3

1.30 Max

7.62

+ 0.11

– 0.05

0.25

2.54 ± 0.25

0.48 ± 0.10

0° – 15°

HM6287HP/HLP Series (DP-22NB)

Unit: mm

27.08

27.90 Max

0.88

1.3

1.30 Max

7.62

+ 0.11

– 0.05

0.25

2.54 ± 0.25

0.48 ± 0.10

0° – 15°

HM6287, HM6287H Series

HM6287HJP/HLJP Series (CP-24D)

Unit: mm

15.63

16.00 Max

0.74

1.30 Max

+ 0.35

– 0.16

1.27

0.43 ± 0.10

6.76

0.10

HM6287HLP-25相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

HM6287HLP-25产品参数

型号:	HM6287HLP-25
生命周期：	Transferred
IHS 制造商：	RENESAS TECHNOLOGY CORP
零件包装代码：	DIP
包装说明：	DIP,
针数：	22
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.41
风险等级：	5.64
Is Samacsys：	N
最长访问时间：	25 ns
其他特性：	BATTERY BACK-UP OPERATION
JESD-30 代码：	R-PDIP-T22
长度：	27.08 mm
内存密度：	65536 bit
内存集成电路类型：	CACHE SRAM
内存宽度：	1
功能数量：	1
端子数量：	22
字数：	65536 words
字数代码：	64000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	64KX1
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	SERIAL
认证状态：	Not Qualified
座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
宽度：	7.62 mm
Base Number Matches：	1

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