HM9270D现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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产品型号HM9270D的概述

芯片HM9270D的概述 HM9270D是一款专用于数字信号处理（DSP）领域的高性能芯片，广泛应用于音频处理、电视和音频解码器设备中。该芯片由一系列先进的技术构成，旨在提供高效的信号处理能力，使其在处理复杂音频算法时表现出色。通过极低的功耗和高运算速度，HM9270D满足了现代电子产品升级的需求。在音频处理领域，HM9270D的数码转模拟转换质量得到了广泛认可。该芯片利用高级算法处理声音信号，提供高保真的音频输出，并能与多种音频输入源兼容，确保用户在不同设备间的连通性。芯片HM9270D的详细参数 HM9270D的主要技术参数包括： - 工作电压：3.3V至5V - 功耗：一般工作状态下小于100mW - 工作频率：支持48kHz（采样率） - 音频通道：立体声输出 - 解析度：24位音频解析 - 内部存储：支持外部Flash和SRAM - 接口类型：I2S接口和SPI接口 - ...

产品型号HM9270D的Datasheet PDF文件预览

HM 9270C/D

DTMF RECEIVER

General Description

The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder

functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone

rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-

pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input

amplifier, clock-oscillator and latched 3-state bus interface.

Features

• Complete receiver in an 18-pin package.

• Excellent performance.

• CMOS, single 5 volt operation.

• Minimum board area.

• Central office quality.

• Low power consumption.

• Power-Down mode (HM9270D only).

• Inhibit-mode (HM9270D only).

Pin Configurations

HM9270C

HM9270D

IN+

REF

IC*

IN+

REF

INH

St/GT

ESt

StD

ESt

StD

PWDN

OSC1

OSC2

IC*

OSC1

OSC2

TOE

* Connect to V_SS

- 1 -

HM 9270C/D

DTMF RECEIVER

Block Diagram (Figure 1)

INH

DIGITAL

HIGH

GROUP

FILTER

CODE

ZERO

CROSSING

DETECTORS

CONVERTER

AND

DETECTION

ALGORITHM

IN+

DIAL

TONE

FILTER

LOW

GROUP

FILTER

LATCH

CHIP

POWERBIAS REF

CHIP CHIP

CHIP

CLOCKS

OSC2

BIAS

CIRCUIT

STEERING

LOGIC

OSC1

V_REF

TOE

ESt

StD

St/GT

PWDN

Pin Description

Function

Sym.

Non-Inverting input

Invering Input

IN+

IN-

Connections to the front-end differential amplifier.

Gain select. Gives access to output of front-end differential amplifier for connection of

feedback resistor.

Reference voltage output,nominally V_DD/2. May be used to bias the inputs at midrail (see

application diagram).

V_REF

INH

Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor.

(HM9270D only).

Power down (input). Active high power down the device and inhibit the oscillator internal

built-in pull down resistor. (HM9270D only).

PWDN

Clock Input

Output

Clock

3.579545 MHz crystal connected between these pins completes

internal oscillator.

OSC1

OSC2

Negative power supply, normally connected to 0V.

V_SS

3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.

TOE

- 2 -

HM 9270C/D

DTMF RECEIVER

Function

Sym.

3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid

tone-pair received (see code table).

Delayed steering output. Presents a logic high when a received tone-pair has been registered

and the output latch updated; returns to logic low when the voltage on St/GT falls below

V_TSt.

StD

Early steering output. Presents a logic high immediately when the digital algorithm detects a

recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause

ESt to return to a logic low.

ESt

Steering input/guard time output (bi-directional). A voltage greater than V_TStdetected at St

causes the device to register the detected tone-pair and update the output latch. A voltage

less than V_TStfrees the device to accept a new tone-pair. The GT output acts to reset the

external steering time-constant; its state is a function of ESt and the voltage on St (see truth

table).

St/GT

Positive power supply, +5Volts.

V_DD

Absolute Maximum Ratings (Notes 1, 2 and 3)

Parameters

Min.

Max.

Units

Power Supply Voltage, V_DD- V_SS

Voltage on any pin

Current at any pin

Operating temperature

Storage temperature

Package power dissipation

V_SS- 0.3

V_DD+ 0.3

+85

+150

500

-40

-65

^oC

Note 1. Absolute maximum ratings are those values beyond which damage to the device may

occur.

2. Unless otherwise specified, all voltages are referenced to ground.

3. Power dissipation temperature derating: -12 ^mV_oCfrom 65^oC to 85^oC

DC Electrical Characteristics

Parameter Description

Test Conditions

Min. Typ. Max. Units

SUPPLY:

V_DD

I_cc

P_o

Operating Supply Voltage

4.75

5.25

Operating Supply Current

Power Consumption

Standby Current

3.0

µA

f=3.579MHz; V_DD=5V

PWDN pin = V_DD

I_S

100

INPUTS:

V_IL

Low Level Input Voltage

High Level Input Voltage

Input Leakage Current

Pull Up (Source) Current

1.5

MΩ

V_IH

I_IH/I_IL

I_so

3.5

V_IN=V_ssor V_DD

TOE (Pin 10)=OV

@ 1kHz

0.1

7.5

R_IN

Input

Signal

Impedance Inputs 1,2

V_TSt

Steering Threshold Voltage

2.35

- 3 -

HM 9270C/D

DTMF RECEIVER

Parameter

Description

Test Conditions

Min. Typ. Max. Units

OUTPUTS:

No Load

V_OUT=0.4V

V_OUT=4.6V

No Load

0.03

4.97

2.5

KΩ

V_OL

V_OH

I_OL

I_OH

V_REF

R_OR

Low Level Output Voltage

High Level Output Voltage

Output Low (Sink) Current

Output High (Source) Current

1.0

0.4

2.4

0.8

2.7

Output Voltage

V_REF

Output Resistance

Operating Characteristics

Gain Setting Amplifier

Parameter

Description

Test Conditions

Min.

Typ. Max. Units

I_IN

R_IN

Input Leakage Current

Input Resistance

Input Offset Voltage

V_SS< V_IN< V_DD

±100

±25

1.5

4.5

100

MΩ

MHz

V_PP

KΩ

V_PP

V_OS

PSRR

CMRR

A_VOL

f_C

V_O

C_L

R_L

V_CM

Power Supply Rejection

Common Mode Rejection

DC Open Loop Voltage Gain

Open Loop Unity Gain Bandwidth

Output Voltage Swing

Tolerable capacitive load(GS)

Tolerable resistive load(GS)

Common Mode Range

1kHz

-3.0V <V_IN< 3.0V

R_L³100KΩ to V_SS

No Load

3.0

Notes : 1.All voltages referenced to V_DDunless otherwise noted.

2.V_DD= 5.0V, V_SS= 0V, T_A= 25^oC .

AC Characteristics

All voltages referenced to V_SSunless otherwise noted. V_DD=5.0V, V_SS=0V, T_A= 25^OC, F_CLK=3.579545 MNz, using

test circuit of figure 2.

Parameter

SIGNAL COITIONS:

Valid Input Signal level (each

tone signal):MIN

Description

Min. Typ.

Max. Units

Notes

-40

dBm

1,2,3,5,6,9,11

7.75

mV_RMS

dBm

883

MAX

1,2,3,5,6,9,11

mV_RMS

2,3,6,9,11

Twist Accept Limit: Positive

Negative

±1.5%±2 Hz Nom.

2,3,5,9,11

2,3,5,11

2,3,4,5,9,10,11

2,3,4,5,7,9,10,11

2,3,4,5,8,9,10,11

Freq. Deviation Accept Limit

Freq. Deviation Reject Limit

Third Tone Tolerance

Noise Tolerance

±3.5%

Nom.

-16

-12

+18

Dial Tone Tolerance

- 4 -

HM 9270C/D

DTMF RECEIVER

Parameter

Description

Min. Typ. Max. Units

Notes

TIMING:

t_DP

Tone Present Detection Time

Tone Absent Detection Time

Tone Duration Accept

Tone Duration Reject

Interdigit Pause Accept

Interdigit Pause Reject

0.5

8.5

Refer to Fig. 4

t_DA

t_REC

t_ID

(User Adjustable)

Refer to "Guard Time 20

t_DO

Adjustment"

OUTPUTS:

t_PQ

Propagation Delay (St to Q)

Propagation Delay (St to StD)

Output Data Set Up (Q to Std)

µs

TOE= V_DD

t_PSED

t_QSED

t_PTE

4.5

300

Propagation

ENABLE

R_L=10kΩ

C_L=50pf

t_PTD

Delay (TOE to Q) DISABLE

CLOCK:

f_CLK

Crystal/Clock Frequency

Clock Output Capacitive

3.5759 3.5795 3.581 MHz

30 pf

C_LO

(OSC2)

Load

Notes: 1.dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.

2.Digit sequences consists of all 16 DTMF tones.

3.Tone duration = 40mS Tone pause = 40mS.

4.Nominal DTMF frequencies are used.

5.Both tones in the composite signal have an equal amplitude.

6.Tone pair is deviated by ±1.5% ±2Hz.

7.Bandwidth limited (3kHz) Gaussian Noise.

8.The precise dial tone frequencies are (350Hz and 440Hz) ±2%.

9.For an error rate of less than 1 in 10,000.

10.Referenced to the lowest level frequency component in DTMF signal.

11.Added A 0.1µf capacitor between V_DDand V_SS.

Function Description

HM9270C

0.1µf

100NF

IN+

100

St/GT

ESt

300KΩ

100KΩ

StD

100 KΩ

REF

OSC1

3.58

MHz

OSC2

TOE

FIGURE 2. SINGLE ENDED INPUT CONFIGURATION

- 5 -

HM 9270C/D

DTMF RECEIVER

HM9270D

0.1µf

100NF

IN+

100

Vin

St/GT

ESt

300KΩ

100KΩ

StD

100 KΩ

REF

INH

PWDN

OSC1

3.58

MHz

OSC2

TOE

FIGURE 3. SINGLE ENDED INPUT CONFIGURATION

The HM9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its

architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by

a digital counting section which verifies the frequency and duration of the received tones before passing the

corresponding code to the output bus.

FILTER SECTION

Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two

filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond

to the bands enclosing the low-group and high-group tones (see Fig. 4). The filter section also in corporates

notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order

switched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain com-

parators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the

outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.

Flow Fhigh KEY TOE Q4

Q3 Q2 Q1

697 1209

697 1336

697 1477

770 1209

770 1336

770 1477

852 1209

852 1336

852 1477

941 1336

941 1209

941 1477

697 1633

770 1633

852 1633

941 1633

Decoder Section

The decoder used digital counting techniques to

determine the frequencies of the limited tones and to

verify that they correspond to standard DTMF

frequencies. A complex averaging algorithm(protects)

against tone simulation by extraneous signals, such as

voice, while providing tolerance to smalll frequency

deviations and variations. This averaging algorithm has

been developed to ensure an optimum combination of

immunity to "talk-off" and tolerance to the presence of

interfering signals ("third tones") and noise. When the

detector recognizes the simultaneous presence of two

valid tones (referred to as "signal condition" in some

industry specifications), it raises the "early steering"

flag (ESt). Any subsequent loss of signal condition will

cause ESt to fall.

ANY L

L = LOGIC LOW , H = LOGIC HIGH, Z = HIGH

IMPEDANCE

FIGURE 4. LOGIC TABLE

- 6 -

HM 9270C/D

DTMF RECEIVER

FIGURE 5. TIMING DIAGRAM

EVENTS

TONE DROPOUT

TONE#n+1

INTERDIGIT

PAUSE

REC

TONE # n

TONE #n+1

Ts t

ESt

GTP

GTA

St/GT

DATA

OUTPUTS

DECODED

TONE#n

DECODE TONE n-1

DECODED TONE # n + 1

HIGH

IMPEDANCE

Q1-Q4

StD

OUTPUT

PTD

PTE

TOE

A. Short tone bursts: detected. Tone duration is invalid.

B. Tone #n is detected. Tone duration is valid. Decoded

to outputs.

C. End of tone #n is dectected and validated.

D. 3 State outputs disabled (high impedance).

E. Tone #n + 1 is detected. Tone duration is valid. De

coded to outputs.

F. Tristate outputs are enabled. Acceptable drop out of

tone #n + 1 does not negister at outputs.

G. End of tone #n + 1 is detected and validated.

FIGURE 5. TIMING DIAGRAM

STEERING CIRCUIT

Before registration of a decoded tone-pair, the receiver checks

for a valid signal duration (referred to as "character-recogni-

tion-condition"). This check is per-

formed by an external RC time-constant driven by ESt.

A logic high on ESt causes V_C(see Fig. 5) to rise as the

capacitor discharges. Provided signal-condition is main-

tained (ESt remains high) for the validation period (t_GTP), Vc

reaches the threshold (V_TSt) of the steering logic to register the

tone-pair, latching its corresponding 4-bit code (see Fig. 3)

into the output latch. At this point,

FIGURE 6. TYPICAL FILTER

CHARACTERISTIC

the GT output is activated and drives V_Cto V_DD. GT continues to drive high as long as ESt remains high. Finally

after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling

that a recieved tone-pair has been registered. The contents of the output lacth are made available on the 4-bit

output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to

validate the interdigit paues between signals. Thus, as well as rejecting signals too short to be considered valid, the

receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together

with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to

meet a wide variety of system requiremetns.

- 7 -

HM 9270C/D

DTMF RECEIVER

0.1µf

=(RC) ln (

)

GTA

TST

St/GT

)

GTP

TST

ESt

FIGURE 7. BASIC STEERING CIRCUIT

Guard Time Adjustment

In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig. 7 is

applicable. Component values are chosen according to the following formulae:

t_REC= t_DP+ t_GTP

t_ID= t_DA+ t_GTA

The value of t_DPis a parameter of the device (see table) and t_RECis the minimum signal duration to be recognized by

the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the

designer. For example, a suitable value of R for a t_RECof 40mS would be 300k.

Different steering arrangements may be used to select independently the guard-times for tone-present (t_GTP) and

tone-absent (t_GTA). This may be necessary to meet system specifications which place both accept and reject limits on

both tone duration and interdigital pause.

Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.

Increasing t_RECimproves talk-off performance, since it reduces the probability that tones simulated by speech will

maintain signal condition for long enough to be registered. On the other hand, a relatively short t_RECwith a long t_DO

would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs

would be required. Design information for guard-time adjustment is shown in Fig. 8.

/ GT

tGTP=(Rp C) In (

)

tGTP=(Rp C) In (

tGTA=(R1 C) In (

)

DD - V_TST

tGTA=(R1 C) In (

)

V_TST

R1R2

Rp=

R1R2

Rp=

R1+R2

a) Decreasing t_GTP(t_GTP< t_GTA

)

b) Decreasing t_GTP(t_GTP> t_GTA)

FIGURE 8. GUARD TIME ADJUSTMENT

- 8 -

HM 9270C/D

DTMF RECEIVER

Input Configuration

The input arrangement of the HM9270C/D provides a differential-input operational amplifier as well as a

bias source (V_REF) which is used to bias the inputs at mid-rail.

Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain.

In a single-ended configuration, the input pins are connected as shown in Fig. 2 with the op-amp connected

for unity gain and V_REFbiasing the input at 1/2VDD.

Fig. 9 shows the differential configuration, which permits the adjustment of gain with the feedback resistor

R5.

HM9270C/D

REF

FIGURE 9. DIFFERENTIAL INPUT CONFIGURATION

Power - down and inhibit mode

A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby

mode. It stops the oscillator and the functions of the filters.

Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output

code will remain the same as the previous detected code (see table 1).

fLow Fhigh Key

TOE Q4

Q3 Q2 Q1

fLow Fhigh Key

TOE Q4

Q3 Q2 Q1

697 1209

697 1336

697 1477

770 1209

770 1336

770 1477

852 1209

852 1336

852 1477

941 1336

941 1209

941 1477

697 1209

697 1336

697 1477

770 1209

770 1336

770 1477

852 1209

852 1336

852 1477

941 1336

941 1209

941 1477

697

1633

770 1633

852 1633

941 1633

ANY

697

1633

770 1633

852 1633

941 1633

ANY

PREVIOUS DATA

Table 1: Truth table

INH =V_SS

(Z: high impedance)

INH=V_DD

- 9 -

HM 9270C/D

DTMF RECEIVER

SPECIAL PACKAGE PIN CONFIGURATIONS

HM9270DM

IN+

IN-

VREF

INH

PWDN

OSC1

OSC2

VDD

St/GT

EST

StD

TOE

- 10 -

HM9270D相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

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深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

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深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

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首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

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HM92M产品参数

型号:	HM92M
生命周期：	Obsolete
IHS 制造商：	HSMC CORP
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.84
最大集电极电流 (IC)：	0.8 A
配置：	Single
最小直流电流增益 (hFE)：	40
最高工作温度：	150 °C
极性/信道类型：	PNP
最大功率耗散 (Abs)：	1 W
子类别：	Other Transistors
表面贴装：	YES
标称过渡频率 (fT)：	50 MHz

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产品型号HM9270D的概述

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