HMC832
Data Sheet
Registers Required for Frequency Changes in Integer
Mode
VCO Built-In Test (BIST) with Autocalibration
The frequency limits of the VCO can be measured using the
BIST features of the autocalibration machine by setting Regis-
ter 0x0A[10] = 1, which freezes the VCO switches in one position.
VCO switches may then be written manually with the varactor
biased at the nominal midrail voltage used for autocalibration.
For example, to measure the VCO maximum frequency use
Switch 0, written to the VCO subsystem via Register 0x05 =
000000001 0000 VCO_ID, where VCO_ID = 000b.
In integer mode (Register 0x06[11] = 0), a change of frequency
requires main serial port writes to the following registers:
•
VCO SPI register, Register 0x05. This is required for
manual control only of the VCO when Register 0x0A[11] =
1 (autocalibration disabled) or when the VCO output
divider value must change (VCO_REG 0x02).
•
Integer register, Register 0x03. In integer mode, an
integer register write triggers autocalibration when
Register 0x0A[11] = 0 and it is loaded into the prescaler
automatically after autocalibration runs. If autocalibration
is disabled, Register 0x0A[11] = 1, the integer frequency
change is loaded into the prescaler immediately when
written with no adjustment to the VCO. Normally, changes
to the integer register cause large steps in the VCO
frequency; therefore, the VCO switch settings must be
adjusted. Autocalibration enabled is the recommended
method for integer mode frequency changes. If auto-
calibration is disabled (Register 0x0A[11] = 1), a priori
knowledge of the correct VCO switch setting and the
corresponding adjustment to the VCO is required before
executing the integer frequency change.
When autocalibration is enabled (Register 0x0A[11] = 0), and a
new frequency is written, autocalibration runs. The VCO
frequency error relative to the command frequency is measured
and the results are written to Register 0x11[19:0], where
Register 0x11[19] is the sign bit. The result is written in terms of
VCO count error (see Equation 4).
For example, if the expected VCO is 2 GHz, the reference is
50 MHz, and n is 6, expect to measure 2000/(50/26) = 2560
counts. If a difference of −5 counts is measured in Register 0x11,
then it means 2555 counts were actually measured. Hence, the
actual frequency of the VCO is 5/2560 low, or 1.99609375 GHz,
1 count ~ 781 kHz.
PLL SUBSYSTEM
Charge Pump (CP) and Phase Detector (PD)
VCO Output Mute Function
The phase detector (PD) has two inputs, one from the reference
path divider and one from the RF path divider. When in lock,
these two inputs are at the same average frequency and are fixed
at a constant average phase offset with respect to each other.
The frequency of operation of the PD is fPD. Most formulae
related to step size, Δ-Σ modulation, timers, and so forth are
functions of the operating frequency of the PD, fPD. fPD is also
referred to as the comparison frequency of the PD.
The HMC832 features an intelligent output mute function with
the capability to disable the VCO output while maintaining
fully functional PLL and VCO subsystems. The mute function is
automatically controlled by the HMC832 and provides a
number of mute control options including
•
Automatic mute. This option automatically mutes the
outputs during VCO calibration during output frequency
changes. This mode can be useful in eliminating any out of
band emissions during frequency changes, and ensuring
that the system emits only the desired frequencies. It is
enabled by writing VCO_REG 0x03[8:7] = 1d.
The PD compares the phase of the RF path signal with that of
the reference path signal and controls the charge pump output
current as a linear function of the phase difference between the
two signals. The output current varies linearly over a full 2π
radians ( 360°) of input phase difference.
•
Always mute (VCO_REG 0x03[8:7] = 3d). This mode is
used for manual mute control.
Charge Pump
Typical isolation when the HMC832 is muted is always better
than 50 dB, and is ~40 dB better than disabling the individual
outputs of the HMC832 via VCO_REG 0x03[3:2], as shown in
Figure 35.
A simplified diagram of the charge pump is shown in Figure 43.
The CP consists of four programmable current sources, two con-
trolling the CP gain (Up Gain Register 0x09[13:7], and Down
Gain Register 0x09[6:0]) and two controlling the CP offset,
where the magnitude of the offset is set by Register 0x09[20:14],
and the direction is selected by Register 0x09[21] = 1 for up and
Register 0x09[22] = 1 for down offset.
Also note that the VCO subsystem registers are not directly
accessible. They are written to the VCO subsystem via PLL
Register 0x05. See Figure 39 and the VCO Serial Port Interface
(VSPI) section for more information about the VCO subsystem
SPI.
CP gain is used at all times, whereas CP offset is recommended
for fractional mode of operation only. Typically, the CP up and
down gain settings are set to the same value (Register 0x09[13:7] =
Register 0x09[6:0]).
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