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  • 北京元坤伟业科技有限公司

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  • 深圳市西源信息科技有限公司

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  • 数量5000 
  • 厂家Analog Devices Inc. 
  • 封装40-SMT(6x6) 
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  • 千层芯半导体(深圳)有限公司

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  • 数量12800 
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  • 深圳市宏世佳电子科技有限公司

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  • 数量5378 
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  • 北京齐天芯科技有限公司

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  • 数量5000 
  • 厂家Analog Devices Inc. 
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  • 深圳市华芯盛世科技有限公司

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  • 数量865000 
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  • 封装QFN-40 
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  • 数量5000 
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  • 数量11494 
  • 厂家Analog Devices Inc. 
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  • 数量15300 
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  • 深圳市一呈科技有限公司

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  • 北京顺科电子科技有限公司

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     该会员已使用本站13年以上
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  • 数量5000 
  • 厂家Analog Devices Inc. 
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  • HMC832LP6GETR
  • 数量3219 
  • 厂家Analog Devices Inc. 
  • 封装40-VFQFN 
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产品型号HMC832LP6GETR的概述

HMC832LP6GETR芯片概述 HMC832LP6GETR是由Analog Devices(亚德诺半导体)生产的一款高性能宽频宽合成器。此芯片主要用于无线通信、卫星通信、微波系统以及测试和测量设备等领域。其主要特点是具备优秀的相位噪声性能和灵活的频率调谐能力,因此受到不少高频应用工程师的青睐。 详细参数 HMC832LP6GETR的主要参数包括: - 频率范围: 该合成器可以生成从 0.1 GHz 到 2.0 GHz 的输出频率,适应于多种不同的通信标准。 - 相位噪声: HMC832LP6GETR在1 GHz时,相位噪声优于 -120 dBc/Hz @ 10 kHz偏移,非常适合需要低相位噪声的应用场合。 - 输出功率: 该芯片可以提供高达 +5 dBm 的输出功率,这使得其能够直接驱动下游的射频放大器或混频器。 - 调制类型: 支持多种调制类型,包括频率调制和相位调制,便于用户...

产品型号HMC832LP6GETR的Datasheet PDF文件预览

Fractional-N PLL with Integrated VCO  
25 MHz to 3000 MHz  
HMC832  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
LD/SDO SCK SDI  
RF bandwidth:  
25 MHz to 3000 MHz  
3.3 V supply  
HMC832  
LOCK  
DETECT  
Maximum phase detector rate: 100 MHz  
Ultralow phase noise  
SPI  
SEN  
PROGRAMMING  
INTERFACE  
CONTROL  
CAL  
−110 dBc/Hz in band, typical  
Fractional figure of merit (FOM): −226 dBc/Hz  
24-bit step size, resolution 3 Hz typical  
Exact frequency mode with 0 Hz frequency error  
Fast frequency hopping  
EN  
MODULATOR  
RF_P  
RF_N  
EN  
÷1, 2, 4, 6, ...62  
40-lead 6 mm × 6 mm SMT package: 36 mm2  
APPLICATIONS  
÷N  
VCO  
Cellular infrastructure  
Microwave radio  
CP  
CP  
PFD  
VTUNE  
÷R  
WiMax, WiFi  
Communications test equipment  
CATV equipment  
XREFP  
DDS replacement  
Military  
Figure 1.  
Tunable reference source for spurious-free performance  
GENERAL DESCRIPTION  
The HMC832 is a 3.3 V, high performance, wideband, frac-  
tional-N, phase-locked loop (PLL) that features an integrated  
voltage controlled oscillator (VCO) with a fundamental  
frequency of 1500 MHz to 3000 MHz, and an integrated VCO  
output divider (divide by 1/2/4/6/…60/62), that enables the  
HMC832 to generate continuous frequencies from 25 MHz to  
3000 MHz. The integrated phase detector (PD) and delta-sigma  
(Δ-Σ) modulator, capable of operating at up to 100 MHz, permit  
wider loop bandwidths and faster frequency tuning with  
excellent spectral performance.  
The HMC832 is footprint-compatible to the market leading  
HMC830 PLL with integrated VCO. It features 3.3 V supply and  
an innovative programmable performance technology that enables  
the HMC832 to tailor current consumption and corresponding  
noise floor performance to individual applications by selecting  
either a low current consumption mode or a high performance  
mode for an improved noise floor performance.  
Additional features of the HMC832 include 12 dB of RF output  
gain control in 1 dB steps; output mute function to automatically  
mute the output during frequency changes when the device is  
not locked; selectable output return loss; programmable  
differential or single-ended outputs, with the ability to select  
either output in single-ended mode; and a Δ-Σ modulator exact  
frequency mode that enables users to generate output frequencies  
with 0 Hz frequency error.  
Industry leading phase noise and spurious performance, across  
all frequencies, enable the HMC832 to minimize blocker effects,  
and to improve receiver sensitivity and transmitter spectral  
purity. A low noise floor (−160 dBc/Hz) eliminates any contri-  
bution to modulator/mixer noise floor in transmitter applications.  
Rev. A  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
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COMPARABLE PARTS  
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REFERENCE MATERIALS  
Quality Documentation  
HMC Legacy PCN: LP6CE and LP6GE QFN - Alternate  
assembly source  
EVALUATION KITS  
Package/Assembly Qualification Test Report: LP6, LP6C,  
LP6G (QTR: 2014-00368)  
HMC832LP6GE Evaluation Board  
Semiconductor Qualification Test Report: BiCMOS-A (QTR:  
2013-00235)  
DOCUMENTATION  
Application Notes  
Technical Articles  
Frequency Hopping with Hittite PLLVCOs Application  
Note  
Hittite Introduces New 3.3V Wideband PLL with  
Integrated VCO  
PLL & PLLVCO Serial Programming Interface Mode  
Selection Application Note  
Low Cost PLL with Integrated VCO Enables Compact LO  
Solutions  
Power-Up & Brown-Out Design Considerations for RF PLL  
+VCO Products Application Note  
DESIGN RESOURCES  
HMC832 Material Declaration  
PCN-PDN Information  
Quality And Reliability  
Symbols and Footprints  
Wideband RF PLL+VCO and Clock Generation Products  
FAQs  
Data Sheet  
HMC832 Data Sheet  
TOOLS AND SIMULATIONS  
ADIsimFrequency Planner Tool  
• ADIsimPLL™  
DISCUSSIONS  
View all HMC832 EngineerZone Discussions.  
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HMC832  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
PLL Register Map ........................................................................... 36  
ID, Read Address, and RST Registers...................................... 36  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
General Description......................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Specifications .................................................................. 5  
Absolute Maximum Ratings............................................................ 6  
Recommended Operating Conditions ...................................... 6  
ESD Caution.................................................................................. 6  
Pin Configuration and Function Descriptions............................. 7  
Typical Performance Characteristics ............................................. 8  
Theory of Operation ...................................................................... 14  
PLL Subsystem Overview.......................................................... 14  
VCO Subsystem Overview........................................................ 14  
Reference Divider, Integer, and Fractional Frequency  
Registers....................................................................................... 36  
VCO SPI Register....................................................................... 37  
Delta-Sigma Configuration....................................................... 37  
Lock Detect Register.................................................................. 38  
Analog Enable (EN) Register.................................................... 38  
Charge Pump Register............................................................... 39  
Autocalibration Register............................................................ 39  
Phase Detector (PD) Register................................................... 40  
Exact Frequency Mode Register............................................... 40  
General-Purpose, Serial Port Interface, and Reference  
Divider (GPO_SPI_RDIV) Register........................................ 41  
VCO Tune Register .................................................................... 42  
SAR Register ............................................................................... 42  
General-Purpose 2 Register...................................................... 42  
Built-In Self Test Register.......................................................... 42  
VCO Subsystem Register Map...................................................... 43  
VCO Enable Register ................................................................. 43  
VCO Output Divider Register.................................................. 44  
VCO Configuration Register.................................................... 44  
SPI (Serial Port Interface) Configuration of PLL and VCO  
Subsystems................................................................................... 14  
VCO Subsystem.......................................................................... 16  
PLL Subsystem............................................................................ 20  
Soft Reset and Power-On Reset................................................ 28  
Power-Down Mode.................................................................... 29  
General-Purpose Output (GPO) Pin....................................... 29  
Chip Identification ..................................................................... 29  
Serial Port .................................................................................... 29  
Applications Information .............................................................. 33  
Power Supply............................................................................... 34  
Programmable Performance Technology................................ 34  
Loop Filter and Frequency Changes........................................ 34  
RF Programmable Output Return Loss................................... 35  
Mute Mode .................................................................................. 35  
VCO Calibration/Bias, CF Calibration, and MSB Calibration  
Registers....................................................................................... 45  
VCO Output Power Control..................................................... 45  
Evaluation Printed Circuit Board (PCB)..................................... 46  
Changing Evaluation Board Reference Frequency and CP  
Current Configuration .............................................................. 46  
Evaluation Kit Contents ............................................................ 46  
Outline Dimensions....................................................................... 47  
Ordering Guide .......................................................................... 48  
REVISION HISTORY  
11/14—Rev. 0 to Rev. A  
This Hittite Microwave Products data sheet has been reformatted  
to meet the styles and standards of Analog Devices, Inc.  
Updated Format..................................................................Universal  
Moved Endnotes from Typical Performance Characteristics  
Section to the Applications Information Section....................... 34  
Changes to Ordering Guide .......................................................... 48  
Rev. A | Page 2 of 48  
 
Data Sheet  
HMC832  
SPECIFICATIONS  
VPPCP, VDDLS, VCC1, VCC2 = 3.3 V; RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V minimum and maximum specified  
across the temperature range of −40°C to +85°C.  
Table 1.  
Parameter  
Test Conditions/Comments  
Min  
Typ  
Max  
Unit  
RF OUTPUT CHARACTERISTICS  
Output Frequency  
VCO Frequency at PLL Input  
RF Output Frequency at fVCO  
OUTPUT POWER  
25  
1500  
1500  
3000  
3000  
3000  
MHz  
MHz  
MHz  
RF Output Power at Fundmental  
Frequency  
2000 MHz across all frequencies (see Figure 25)  
Maximum gain setting: VCO_REG 0x07[3:0] = 11d  
single-ended  
7
dBm  
Gain Setting 6: VCO_REG 0x07[3:0] = 6d differential  
1 dB steps  
2
12  
dBm  
dB  
Output Power Control Range  
HARMONICS FOR FUNDAMENTAL  
MODE  
fo Mode at 2 GHz  
fo/2 Mode at 2 GHz/2 = 1 GHz  
fo/30 Mode at 3 GHz/30 = 100 MHz  
fo/62 Mode at 1550 MHz/62 = 25 MHz  
VCO OUTPUT DIVIDER  
2nd/3rd/4th  
2nd/3rd/4th  
2nd/3rd/4th  
2nd/3rd/4th  
−20/−29/−45  
−26/−10/−34  
−33/−10/−40  
−40/−6/−43  
dBc  
dBc  
dBc  
dBc  
VCO RF Divider Range  
1, 2, 4, 6, 8, … 62  
1
62  
PLL RF DIVIDER CHARACTERISTICS  
19-Bit N-Divider Range (Integer)  
19-Bit N-Divider Range (Fractional)  
Maximum = 219 − 1  
Fractional nominal divide ratio varies ( 4) dynamically  
maximum  
16  
20  
524,287  
524,283  
REFERENCE (XREFP PIN) INPUT  
CHARACTERISTICS  
350  
+12  
5
MHz  
dBm  
pF  
Maximum XREFP Input Frequency  
XREFP Input Level  
AC-coupled1  
−6  
1
XREFP Input Capacitance  
14-Bit R-Divider Range  
PHASE DETECTOR (PD)2  
PD Frequency Fractional Mode3  
PD Frequency Integer Mode  
CHARGE PUMP  
16,383  
DC  
DC  
100  
100  
MHz  
MHz  
Output Current  
0.02  
2.54  
mA  
µA  
Charge Pump Gain Step Size  
PD/Charge Pump SSB Phase Noise  
1 kHz  
10 kHz  
100 kHz  
20  
50 MHz reference, input referred  
−143  
−150  
−152  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Add 2 dB for fractional mode  
Add 3 dB for fractional mode  
LOGIC INPUTS  
VSW  
40  
50  
60  
% DVDD  
LOGIC OUTPUTS  
Output High Voltage (VOH )  
Output Low Voltage (VOL )  
Output Impedance  
Maximum Load Current  
POWER SUPPLY VOLTAGES  
3.3 V Supplies  
DVDD  
0
V
V
Ω
mA  
100  
3.1  
200  
1.5  
AVDD, VCCHF, VCCPS, VCCPD, RVDD, DVDD, VPPCP,  
VDDLS, VCC1, VCC2  
3.3  
3.5  
V
Rev. A | Page 3 of 48  
 
HMC832  
Data Sheet  
Parameter  
Test Conditions/Comments  
Min  
Typ  
Max  
Unit  
POWER SUPPLY CURRENTS  
High Performance Mode  
2500 MHz, Gain 11  
VCO_REG 0x03[1:0] = 3d4  
Gain 11 (VCO_REG 0x07[3:0] = 11d) single-ended  
output (VCO_REG 0x03[3:2] = 2d)  
Single-ended output  
Gain 6 (VCO_REG 0x07[3:0] = 6d) differential output  
(VCO_REG 0x03[3:2] = 3d)  
219  
mA  
800 MHz, Gain 11  
2500 MHz, Gain 6  
230  
226  
mA  
mA  
800 MHz, Gain 6  
2500 MHz, Gain 1  
237  
210  
mA  
mA  
Differential output  
Gain 1 (VCO_REG 0x07[3:0] = 1d) differential output  
(VCO_REG 0x03[3:2] = 3d)  
800 MHz, Gain 1  
Low Current Mode  
2500 MHz, Gain 6  
221  
195  
mA  
mA  
Differential output  
VCO_REG 0x03[1:0] = 1d4  
Gain 6 (VCO_REG 0x07[3:0] = 6d), differential output  
(VCO_REG 0x03[3:2] = 3d)  
800 MHz, Gain 6  
2500 MHz, Gain 1  
Differential output  
Gain 1 (VCO_REG 0x07[3:0] = 1d), differential output  
(VCO_REG 0x03[3:2] = 3d)  
205  
180  
mA  
mA  
800 MHz, Gain 1  
Power-Down  
Differential output  
192  
mA  
Crystal Off  
Register 0x01 = 0, crystal not clocked  
Register 0x01 = 0, crystal clocked 100 MHz  
10  
5
µA  
mA  
Crystal On, 100 MHz  
POWER-ON RESET  
Typical Reset Voltage on DVDD  
Minimum DVDD Voltage for No Reset  
Power-On Reset Delay  
VCO OPEN-LOOP PHASE NOISE  
fo @ 2 GHz5  
700  
250  
mV  
V
µs  
1.5  
10 kHz Offset  
100 kHz Offset  
1 MHz Offset  
10 MHz Offset  
100 MHz Offset  
fo @ 2 GHz/2 = 1 GHz5  
−88  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
−116  
−139  
−157  
−162  
10 kHz Offset  
100 kHz Offset  
1 MHz Offset  
10 MHz Offset  
−93  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
−122  
−145  
−159  
−162  
100 MHz Offset  
fo @ 3 GHz/30 = 100 MHz5  
10 kHz Offset  
100 kHz Offset  
1 MHz Offset  
10 MHz Offset  
100 MHz Offset  
−110  
−139  
−160  
−163  
−163  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
FIGURE OF MERIT (FOM)  
Floor Integer Mode (Figure 24)  
Floor Fractional Mode (Figure 24)  
Flicker (Both Modes) (Figure 24)  
Normalized to 1 Hz  
Normalized to 1 Hz  
Normalized to 1 Hz  
−229  
−226  
−268  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Rev. A | Page 4 of 48  
Data Sheet  
HMC832  
Parameter  
Test Conditions/Comments  
Min  
Typ  
Max  
Unit  
VCO CHARACTERISTICS  
VCO Tuning Sensitivity  
2800 MHz  
2400 MHz  
2000 MHz  
1600 MHz  
VCO Supply Pushing  
Measured with 1.5 V on VTUNE; see Figure 29  
Measured with 1.5 V on VTUNE; see Figure 29  
Measured with 1.5 V on VTUNE; see Figure 29  
Measured with 1.5 V on VTUNE; see Figure 29  
Measured with 1.5 V on VTUNE  
24.6  
25.8  
25.2  
24.3  
2.8  
MHz/V  
MHz/V  
MHz/V  
MHz/V  
MHz/V  
1 Measured with 100 Ω external termination. See Reference Input Stage section for more details.  
2 Slew rate of ≥0.5 ns/V is recommended, see Reference Input Stage section for more details. Frequency is guaranteed across process voltage and temperature from  
−40°C to +85°C.  
3 This maximum PD frequency can only be achieved if the minimum N value is respected. For example, in the case of fractional mode, the maximum PD frequency =  
f
VCO/20 or 100 MHz, whichever is less.  
4 For detailed current consumption information, refer to Figure 33 and Figure 36.  
5 Gain setting = 6 (VCO_REG 0x07[3:0] = 6d) in high performance mode (VCO_REG 0x03[1:0] = 3d).  
TIMING SPECIFICATIONS  
SPI Write Timing Characteristics  
AVDD = DVDD = 3 V, AGND = DGND = 0 V.  
Table 2. SPI Write Timing Characteristics, See Figure 47  
Parameter  
Test Conditions/Comments  
SDI setup time to SCLK rising edge  
SCLK rising edge to SDI hold time  
SEN low duration  
SEN high duration  
SCLK 32nd rising edge to SEN rising edge  
Min  
3
3
10  
10  
10  
20  
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
t1  
t2  
t3  
t4  
t5  
t6  
ns  
ns  
Recovery time  
Maximum serial port clock speed  
50  
MHz  
Table 3. SPI Read Timing Characteristics, See Figure 48  
Parameter  
Test Conditions/Comments  
SDI setup time to SCK rising edge  
SCK rising edge to SDI hold time  
SEN low duration  
Min  
3
3
10  
10  
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
SEN high duration  
SCK rising edge to SDO time  
Recovery time  
SCK 32nd rising edge to SEN rising edge  
8.2 ns + 0.2 ns/pF  
10  
10  
Rev. A | Page 5 of 48  
 
 
 
 
 
 
 
 
HMC832  
Data Sheet  
ABSOLUTE MAXIMUM RATINGS  
Table 4. Absolute Maximum Ratings  
Parameter  
AVDD, RVDD, DVDD, VCCPD, VCCHF, VCCPS  
VPPCP, VDDLS, VCC1  
RECOMMENDED OPERATING CONDITIONS  
Rating  
Table 5. Recommended Operating Conditions  
−0.3 V to +3.6 V  
−0.3 V to +3.6 V  
−0.3 V to +3.6 V  
−40°C to +85°C  
−65°C to +150°C  
150°C  
Parameter  
Min  
Typ  
Max  
Units  
Temperature  
Junction Temperature1  
Ambient Temperature  
Supply Voltage  
125  
+85  
°C  
°C  
VCC2  
Operating Temperature  
Storage Temperature  
−40  
3.1  
Maximum Junction Temperature  
AVDD, RVDD, DVDD, VCCPD, VCCHF,  
VCCPS, VPPCP, VDDLS, VCC1, VCC2  
3.3  
3.5  
V
9°C/W  
Thermal Resistance (θJC) (Junction to Case (Ground  
Paddle))  
1 Layout design guidelines set out in Qualification Test Report are strongly  
recommended.  
Reflow Soldering  
Peak Temperature  
260°C  
Time at Peak Temperature  
ESD Sensitivity (HBM)  
40 sec  
Class 1B  
ESD CAUTION  
Stresses at or above those listed under Absolute Maximum  
Ratings may cause permanent damage to the product. This is a  
stress rating only; functional operation of the product at these  
or any other conditions above those indicated in the operational  
section of this specification is not implied. Operation beyond  
the maximum operating conditions for extended periods may  
affect product reliability.  
Rev. A | Page 6 of 48  
 
 
 
 
Data Sheet  
HMC832  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
AVDD  
NC  
1
2
3
4
5
6
7
8
9
30 SEN  
29 RF_P  
28 RF_N  
27 VCC1  
26 NC  
VPPCP  
CP  
HMC832  
TOP VIEW  
(Not to Scale)  
NC  
NC  
25 VCC2  
24 NC  
VDDLS  
NC  
23 VTUNE  
22 NC  
21 NC  
NC  
RVDD 10  
NOTES  
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.  
2. THE EXPOSED GROUND PAD MUST BE  
CONNECTED TO RF/DC GROUND.  
Figure 2. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
AVDD  
NC  
DC Power Supply for Analog Circuitry.  
No Connect. These pins are not connected internally; however, it is recommended to connect these  
pins to RF/dc ground externally.  
2, 5, 6, 8, 9, 11 to  
14, 18 to 22, 24, 26,  
34, 37, 38  
3
4
VPPCP  
CP  
Power Supply for Charge Pump Analog Section.  
Charge Pump Output.  
7
VDDLS  
RVDD  
XREFP  
DVDD  
CEN  
Power Supply for the Charge Pump Digital Section.  
Reference Supply.  
Reference Oscillator Input.  
DC Power Supply for Digital (CMOS) Circuitry.  
PLL Subsystem Enable. Note that there is no effect on the VCO subsystem. Connect to logic high for  
normal operation.  
10  
15  
16  
17  
23  
25  
27  
28  
29  
30  
31  
32  
33  
35  
36  
39  
40  
VTUNE  
VCC2  
VCC1  
RF_N  
RF_P  
SEN  
SDI  
SCK  
LD/SDO  
VCCHF  
VCCPS  
VCCPD  
BIAS  
VCO Varactor. Tuning port input.  
VCO Analog Supply 2.  
VCO Analog Supply 1.  
RF Negative Output.  
RF Positive Output.  
PLL Serial Port Enable (CMOS) Logic Input.  
PLL Serial Port Data (CMOS) Logic Input.  
PLL Serial Port Clock (CMOS) Logic Input.  
Lock Detect, or Serial Data, or General-Purpose (CMOS) Logic Output (GPO).  
DC Power Supply for Analog Circuitry.  
DC Power Supply for Analog Prescaler.  
DC Power Supply for Phase Detector.  
External Bypass Decoupling for Precision Bias Circuits. Note: 1.920 V 20 mV reference voltage (BIAS) is  
generated internally and cannot drive an external load. It must be measured with a 10 GΩ meter, such  
as the Agilent 34410A; a normal 10 MΩ DVM reads erroneously.  
EP  
Exposed Pad. The exposed pad must be connected to RF/dc ground.  
Rev. A | Page 7 of 48  
 
HMC832  
Data Sheet  
TYPICAL PERFORMANCE CHARACTERISTICS  
–100  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–110  
LOOP BW = 75kHz  
–120  
LOOP BW = 127kHz  
LOOP BW = 75kHz  
–130  
LOOP BW = 127kHz  
–140  
–150  
750MHz, EVM = –62.5dB, OR 0.075%  
1600MHz, EVM = –57dB OR 0.141%  
880MHz, EVM = –61.3dB OR 0.086%  
1605MHz, EVM = –57.5dB OR 0.133%  
2505MHz, EVM = –52dB OR 0.251%  
880MHz, EVM = –61.8dB OR 0.081%  
1605MHz, EVM = –57.2dB OR 0.138%  
2505MHz, EVM = –53.9dB OR 0.204%  
2500MHz, EVM = –53.3dB OR 0.216%  
–160  
875MHz, EVM = –64.8dB OR 0.058%  
1600MHz, EVM = –59.8dB OR 0.102%  
2500MHz, EVM = –55.8dB OR 0.168%  
–170  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 6. Typical Closed-Loop Fractional Phase Noise, 50 MHz PD Frequency,  
Output Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode (VCO_REG  
0x03[1:0] = 3d), Phase Noise Integrated from 1 kHz to 100 MHz, See Table 12  
Figure 3. Typical Closed-Loop Integer Phase Noise, 50 MHz PD Frequency, Output  
Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode (VCO_REG 0x03[1:0]  
= 3d), Phase Noise Integrated from 1 kHz to 100 MHz, See Table 12  
–100  
–60  
÷1  
÷2  
÷4  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–80  
–100  
÷8  
÷16  
÷32  
÷62  
LOW CURRENT MODE  
(VCO_REG0x03[10] = 1d)  
–120  
–140  
–160  
–180  
HIGH PERFORMANCE MODE  
(VCO_REG0x03[10] = 3d)  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 7. Closed-Loop Phase Noise at 1800 MHz, Divided by 1 to 62, PD  
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 12), High Perfor-  
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios  
is Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62  
Figure 4. Open-Loop VCO Phase Noise at 1800 MHz  
–40  
–60  
–100  
÷1  
–110  
÷2  
÷4  
–80  
–120  
÷8  
÷16  
–100  
–120  
–140  
–160  
–180  
–130  
÷32  
LOW CURRENT MODE  
(VCO_REG0x03[10] = 1d)  
–140  
–150  
–160  
–170  
÷62  
HIGH PERFORMANCE MODE  
(VCO_REG0x03[10] = 3d)  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 5. Free Running VCO Phase Noise at 3000 MHz  
Figure 8. Closed-Loop Phase Noise at 3000 MHz, Divided by 1 to 62, PD  
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 12), High Perfor-  
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios  
is Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62  
Rev. A | Page 8 of 48  
 
Data Sheet  
HMC832  
–60  
–60  
–80  
–80  
LOW CURRENT MODE (VCO_REG0x03 [10] = 1d)  
SSB INTEGRATED PHASE NOISE = –58.7dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 55.7dB, EVM = 0.164%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
LOW CURRENT MODE (VCO_REG0x03[10] = 1d)  
SSB INTEGRATED PHASE NOISE = –64.3dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 61.3dB, EVM = 0.086%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–100  
–120  
–140  
–100  
–120  
–140  
–160  
–180  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
SSB INTEGRATED PHASE NOISE = –59dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 56dB, EVM = 0.158%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
SSB INTEGRATED PHASE NOISE = –65.5dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 62.5dB, EVM = 0.075% PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–160  
–180  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 9. Fractional Spurious Performance at 904 MHz, Exact Frequency  
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz,  
Loop Filter Type 2 (See Table 12)  
Figure 12. Fractional Spurious Performance at 1804 MHz, Exact Frequency  
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz,  
Loop Filter Type 2 (See Table 12)  
–60  
–60  
LOW CURRENT MODE (VCO_REG0x03[10] = 1d)  
SSB INTEGRATED PHASE NOISE = –57dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 54dB, EVM = 0.199%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
LOW CURRENT MODE (VCO_REG0x03[10] = 1d)  
–80  
–80  
SSB INTEGRATED PHASE NOISE = –57dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 54, EVM = 0.199%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–100  
–100  
–120  
–120  
–140  
–140  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
SSB INTEGRATED PHASE NOISE = –57.45dBc  
–160  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
–160  
SSB INTEGRATED PHASE NOISE = –57.45dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 54.45dB, EVM = 0.189%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–180  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 54.45dB, EVM = 0.189%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–180  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 10. Fractional Spurious Performance at 2118.24 MHz,  
Exact Frequency Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel  
Spacing = 240 kHz, Loop Filter Type 2 (See Table 12)  
Figure 13. Fractional Spurious Performance at 2118.24 MHz, Identical  
Configuration to Figure 10 with Exact Frequency Mode Off  
–60  
–60  
LOW CURRENT MODE (VCO_REG0x03[10] = 1d)  
SSB INTEGRATED PHASE NOISE = –55.6dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
–80  
–80  
LOW CURRENT MODE (VCO_REG0x03[10] = 1d)  
SSB INTEGRATED PHASE NOISE = –55.6dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 52.6dB, EVM = 0.234%, PHASE NOISE  
SNR = 52.6dB, EVM = 0.234%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–100  
–120  
–100  
–120  
–140  
–160  
–180  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–140  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
HIGH PERFORMANCE MODE (VCO_REG0x03[10] = 3d)  
SSB INTEGRATED PHASE NOISE = –56dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 53dB, EVM = 0.224%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
–160  
–180  
SSB INTEGRATED PHASE NOISE = –56dBc  
INTEGRATION BANDWIDTH = 1kHz TO 100MHz  
SNR = 53dB, EVM = 0.224%, PHASE NOISE  
INTEGRATION BANDWIDTH 1kHz TO 100MHz  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET (Hz)  
OFFSET (Hz)  
Figure 11. Fractional Spurious Performance at 2646.96 MHz, Exact Frequency  
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 240 kHz,  
Loop Filter Type 2 (See Table 12)  
Figure 14. Fractional Spurious Performance at 2646.96 MHz, Identical  
Configuration to Figure 11 with Exact Frequency Mode Off  
Rev. A | Page 9 of 48  
 
 
HMC832  
Data Sheet  
–60  
–80  
–120  
–130  
–140  
–150  
–160  
–100  
–120  
–140  
–160  
–180  
100MHz OUTPUT  
55.55MHz OUTPUT  
25MHz OUTPUT  
–170  
100  
1k  
10k  
100k  
1M  
10M  
100M  
1k  
10k  
100k  
OFFSET (Hz)  
1M  
10M  
100M  
OFFSET (Hz)  
Figure 15. Low Frequency Performance, 100 MHz XTAL, PD Frequency =  
50 MHz, Loop Filter Type 3 (See Table 12), Integer Mode, 50 MHz Low-Pass  
Filter at the Output of HMC832 for the 25 MHz Curve Only, Charge Pump Set to  
Maximum Value  
Figure 18. Typical Spurious Emissions at 2000.1 MHz, 50 MHz Fixed  
Reference, 50 MHz PD Frequency, Integer Boundary Spur Inside the Loop  
Filter Bandwidth (See the Loop Filter and Frequency Changes Section)  
–60  
–60  
TYPICAL SPURIOUS VS. OFFSET FROM 2GHz,  
FIXED REFERENCE = 50MHz  
–70  
–80  
–80  
–100  
–120  
–140  
–160  
–180  
–90  
–100  
TYPICAL SPURIOUS VS. OFFSET FROM 2GHz,  
TUNABLE REFERENCE ~47.5MHz  
–110  
–120  
2000.01  
2000.1  
2001  
1k  
10k  
100k  
1M  
10M  
100M  
OUTPUT FREQUENCY (kHz)  
OFFSET (Hz)  
Figure 16. Typical Spurious Emissions at 2000.1 MHz, Tunable Reference,  
Loop Filter Type 2 (see Table 12 and the Loop Filter and Frequency Changes  
Section)  
Figure 19. Typical Spurious vs. Offset from 2 GHz, Fixed 50 MHz Reference vs.  
Tunable 47.5 MHz Reference (See the Loop Filter and Frequency Changes  
Section)  
–40  
–100  
–40°C  
HIGH PERFORMANCE MODE ON  
(VCO_REG0x03[1:0] = 3d)  
+27°C  
100kHz OFFSET  
ALL MODES  
+85°C  
–60  
–80  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
1MHz OFFSET  
ALL MODES  
100MHz OFFSET  
LOW CURRENT MODE  
100MHz OFFSET  
HIGH PERFORMANCE  
MODE  
–100  
–120  
–140  
2854MHz  
–160  
2453MHz  
2013MHz  
1587MHz  
–180  
1k  
10k  
100k  
1M  
10M  
100M  
30  
100  
300  
1000  
3000  
OFFSET (Hz)  
FREQUENCY (MHz)  
Figure 17. Open-Loop Phase Noise  
Figure 20. Open-Loop Phase Noise vs. Frequency at Various Temperatures  
Rev. A | Page 10 of 48  
 
 
 
Data Sheet  
HMC832  
–200  
–210  
–220  
–230  
–240  
–50  
0.4460  
0.1410  
0.0447  
0.0141  
0.0045  
–40°C  
+27°C  
+85°C  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
TYP FOM VS OFFSET  
FOM FLOOR  
FOM 1/f NOISE  
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz  
–90  
100  
100  
1k  
10k  
100k  
1M  
1000  
OFFSET (Hz)  
OUTPUT FREQUENCY (MHz)  
Figure 21. Single Sideband Integrated Phase Noise, High Performance Mode,  
Loop Filter Type 2 (See Table 12)  
Figure 24. Figure of Merit  
20  
15  
15  
RETURN LOSS (VCO_REG0x03[5] = 0)  
RETURN LOSS (VCO_REG0x03[5] = 1)  
10  
GAIN SETTING = 11  
(VCO_REG0x07[3:0] = 11d)  
HIGH PERFORMANCE MODE  
(VCO_REG0x03[1:0] = 3d)  
10  
5
0
GAIN SETTING = 5  
5
(VCO_REG0x07[3:0] = 5d)  
0
GAIN SETTING = 0  
(VCO_REG0x07[3:0] = 0d)  
–5  
–5  
LOW CURRENT MODE  
(VCO_REG0x03[1:0] = 1d)  
–10  
–15  
–20  
–10  
HIGH PERFORMANCE MODE  
LOW CURRENT MODE  
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz  
–15  
25  
100  
1000  
3000  
25  
100  
1000  
3000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 22. Typical Single-Ended Output Power vs. Frequency (Mid Gain  
Setting 6)  
Figure 25. Typical Output Power vs. Frequency and Gain (Single-Ended)  
10  
0
–40°C  
+27°C  
+85°C  
8
RETURN LOSS 0 (VCO_REG0x03[5] = 0)  
–5  
6
4
RETURN LOSS 1 (VCO_REG0x03[5] = 1)  
–10  
2
–15  
–20  
–25  
–30  
0
–2  
–4  
–6  
0
2
4
6
8
10  
25  
100  
1000  
8000  
GAIN SETTING  
OUTPUT FREQUENCY (MHz)  
Figure 23. Typical RF Output Power at 2 GHz (Single-Ended) vs. Temperature  
Figure 26. RF Output Return Loss  
Rev. A | Page 11 of 48  
 
 
 
 
HMC832  
Data Sheet  
3.2  
200  
150  
100  
50  
SETTLING TIME TO < 10 DEGREES  
PHASE ERROR  
SETTLING TIME TO < 10 DEGREES  
PHASE ERROR  
3.0  
2.8  
2.6  
2.4  
2.2  
0
–50  
–100  
–150  
–200  
0
20  
40  
60  
80  
TIME (µs)  
100  
120  
140  
160  
0
20  
40  
60  
80  
100  
120  
140  
160  
TIME (µs)  
Figure 30. Phase Settling After Frequency Change, Autocalibration Enabled,  
Loop Filter BW = 127 kHz (Type 1, See Table 12)  
Figure 27. Frequency Settling After Frequency Change, Autocalibration  
Enabled, Loop Filter BW = 127 kHz (Type 1, See Table 12)  
200  
2.510  
SETTLING TIME TO < 10 DEGREES  
PHASE ERROR  
150  
100  
50  
SETTLING TIME TO < 10 DEGREES  
PHASE ERROR  
2.505  
0
–50  
–100  
–150  
–200  
2.500  
NOTE: LOOP FILTER BANDWIDTH = 127kHz,  
NOTE: LOOP FILTER BANDWIDTH = 127kHz, LOOP  
FILTER PHASE MARGIN = 61 DEGREES. THIS RESULT IS  
DIRECTLY AFFECTED BY LOOP FILTER DESIGN. FASTER  
SETTLING TIME IS POSSIBLE WITH WIDER LOOP FILTER  
BANDWIDTH AND LOWER PHASE MARGIN.  
2.495  
LOOP FILTER PHASE MARGIN = 61 DEGREES.  
THIS RESULT IS DIRECTLY AFFECTED BY LOOP  
FILTER DESIGN. FASTER SETTLING TIME IS  
POSSIBLE WITH WIDER LOOP FILTER  
BANDWIDTH AND LOWER PHASE MARGIN.  
0
20  
40  
60  
80  
100  
120  
140  
160  
0
20  
40  
60  
80  
100  
120  
140  
160  
TIME (µs)  
TIME (µs)  
Figure 31. Phase Settling After Frequency Change, Manual Calibration  
Figure 28. Frequency Settling After Frequency Change, Manual Calibration,  
Loop Filter BW = 127 kHz (Type 1 in Table 12)  
4.0  
90  
2854MHz  
2453MHz  
2013MHz  
1587MHz  
TUNING CAP 15  
3.5  
80  
70  
60  
50  
40  
30  
20  
10  
CALIBRATED AT +85°C, MEASURED AT +85°C  
CALIBRATED AT +85°C, MEASURED AT –40°C  
CALIBRATED AT –40°C, MEASURED AT –40°C  
CALIBRATED AT –40°C, MEASURED AT +85°C  
CALIBRATED AT +27°C, MEASURED AT +27°C  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
fMIN  
fMAX  
1330 1520 1710 1900 2090 2280 2470 2660 2850 3040  
0
0.66  
1.30  
2.00  
2.60  
3.30  
VCO FREQUENCY (MHz)  
TUNING VOLTAGE (V)  
Figure 29. Typical VCO Sensitivity  
Figure 32. Typical Tuning Voltage After Calibration (See the Loop Filter and  
Frequency Changes Section)  
Rev. A | Page 12 of 48  
 
 
 
 
 
 
Data Sheet  
HMC832  
260  
240  
220  
200  
180  
240  
fO/62  
fO/4  
OUTPUT GAIN 0dB  
OUTPUT GAIN 6dB  
OUTPUT GAIN 0dB  
OUTPUT GAIN 6dB  
fO/62  
fO/4  
230  
220  
210  
200  
190  
180  
170  
160  
fO/2  
fO/2  
HIGH PERFORMANCE MODE  
(VCO_REG0x03[1:0] = 3d)  
fO  
fO  
HIGH PERFORMANCE MODE  
(VCO_REG0x03[1:0] = 3d)  
LOW CURRENT  
CONSUMPTION MODE  
(VCO_REG0x03[1:0] = 1d)  
LOW CURRENT  
CONSUMPTION MODE  
(VCO_REG0x03[1:0] = 1d)  
0
500  
1000  
1500  
2000  
2500  
3000  
0
500  
1000  
1500  
2000  
2500  
3000  
OUTPUT FREQUENCY (MHz)  
OUTPUT FREQUENCY (MHz)  
Figure 36. Current Consumption in Differential Output Configuration,  
Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended  
Mode Programmed in VCO_REG 0x03[3:2]  
Figure 33. Current Consumption in Single-Ended Output Configuration,  
Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended  
Mode Programmed in VCO_REG 0x03[3:2]  
235  
232  
230  
228  
226  
224  
14MHz SINUSOIDAL  
25MHz SINUSOIDAL  
50MHz SQUARE  
230  
100MHz SQUARE  
225  
220  
215  
210  
205  
200  
222  
14MHz SQUARE WAVE  
25MHz SQUARE WAVE  
50MHz SQUARE WAVE  
100MHz SQUARE WAVE  
220  
–15  
–20  
–15  
–10  
–5  
0
5
–12  
–9  
–6  
–3  
0
3
REFERENCE POWER (dBm)  
REFERENCE POWER (dBm)  
Figure 34. Reference Input Sensitivity, Square Wave, Measured from a 50 Ω  
Source with a 100 Ω External Resistor Termination  
Figure 37. Reference Input Sensitivity, Sinusoidal Wave, Measured from a  
50 Ω Source with a 100 Ω External Resistor Termination  
–10  
SIGNAL ON RF_N PIN WHEN RF_N PIN OFF,  
RF_P PIN ON (VCO_REG0x03[3:2] = 1d),  
MUTE OFF (ON ONLY DURING VCO  
CALIBRATION VCO_REG0x03[8:7] = 1d)  
–30  
–50  
BOTH RF_N AND RF_P PINS OFF,  
(VCO_REG0x03[3:2] = 0d),  
MUTE OFF (ON ONLY DURING VCO  
CALIBRATION VCO_REG0x03[8:7] = 1d)  
–70  
–90  
MUTE ON (VCO_REG0x03[8:7] = 3d)  
–110  
100  
1000  
3000  
FRQUENCY (MHz)  
Figure 35. Mute Mode Isolation, Measured at Output  
Rev. A | Page 13 of 48  
 
 
 
HMC832  
Data Sheet  
THEORY OF OPERATION  
SEN  
SDI  
4
REF BUFF  
CONTROL  
RF BUFFER EN  
SCK  
RF_N  
RF_P  
LD_SDO  
3
VSPI  
CNTRL  
MODULATOR  
CAL  
VSPI  
CHARGE  
PUMP  
CP  
fO OR ÷N OR ×2  
CAL  
VCO EN  
N
PHASE  
FREQUENCY  
DETECTOP  
DIVIDER  
R
PLL BUFF  
XREFP  
DIVIDER  
VTUNE  
PLL ONLY  
CEN  
Figure 38. PLL and VCO Subsystems  
The HMC832 PLL with integrated VCO is comprised of two  
subsystems; PLL subsystem and VCO subsystem, as shown in  
Figure 38.  
VCO SUBSYSTEM OVERVIEW  
The VCO subsystem consists of a capacitor switched step tuned  
VCO and an output stage. In typical operation, the VCO  
subsystem is programmed with the appropriate capacitor switch  
setting that is executed automatically by the PLL subsystem  
autocalibration state machine when autocalibration is enabled  
(Register 0x0A[11] = 0, see the VCO Calibration section for  
more information). The VCO tunes to the fundamental  
frequency (1500 MHz to 3000 MHz), and is locked by the CP  
output from the PLL subsystem. The VCO subsystem controls  
the output stage of the HMC832 enabling configuration of  
PLL SUBSYSTEM OVERVIEW  
The PLL subsystem divides down the VCO output to the  
desired comparison frequency via the N-divider (integer value  
set in Register 0x03, fractional value set in Register 0x04),  
compares the divided VCO signal to the divided reference  
signal (reference divider set in Register 0x02) in the phase  
detector (PD), and drives the VCO tuning voltage via the charge  
pump (CP) (configured in Register 0x09) to the VCO  
subsystem. Some of the additional PLL subsystem functions  
include  
User defined performance settings (see the Programmable  
Performance Technology section) that are configured via  
VCO_REG 0x03[1:0].  
Delta-sigma configuration (Register 0x06).  
Exact frequency mode (configured in Register 0x0C,  
Register 0x03, and Register 0x04).  
VCO output divider settings that are configured in the  
VCO_REG 0x02 (divide by 2/4/6 … 60/62 to generate  
frequencies from 25 MHz to 1500 MHz, or divide by 1 to  
generate fundamental frequencies between 1500 MHz and  
3000 MHz).  
Lock detect (LD) configuration (use Register 0x07 to  
configure LD and Register 0x0F to configure the LD_SDO  
output pin).  
External CEN pin used for the hardware PLL enable pin.  
CEN pin does not affect the VCO subsystem.  
Output gain settings (VCO_REG 0x07[3:0]).  
Output return loss setting (VCO_REG 0x03[5]). See  
Figure 26 for more information.  
Single-ended or differential output operation  
(VCO_REG 0x03[3:2]).  
Mute (VCO_REG 0x03[8:7]).  
Typically, only writes to the divider registers (integer part uses  
Register 0x03, fractional part uses Register 0x04) of the PLL  
subsystem are required for HMC832 output frequency changes.  
Divider registers of the PLL subsystem (Register 0x03 and  
Register 0x04), set the fundamental frequency (1500 MHz to  
3000 MHz) of the VCO subsystem. Output frequencies ranging  
from 25 MHz to 1500 MHz are generated by tuning to the  
appropriate fundamental VCO frequency (1500 MHz to  
3000 MHz) by programming the N divider (Register 0x03 and  
Register 0x04) and programming the output divider (divide by  
1/2/4/6 … /60/62, in VCO_REG 0x02) in the VCO subsystem.  
SPI (SERIAL PORT INTERFACE) CONFIGURATION  
OF PLL AND VCO SUBSYSTEMS  
The two subsystems (PLL subsystem and VCO subsystem) have  
their own register maps as shown in the PLL Register Map and  
VCO Subsystem Register Map sections. Typically, writes to both  
register maps are required for initialization and frequency  
tuning operations.  
As shown in Figure 38, the PLL subsystem is connected directly  
to the SPI of the HMC832, whereas the VCO subsystem is  
connected indirectly through the PLL subsystem to the  
For detailed frequency tuning information and example, see the  
Frequency Tuning section.  
Rev. A | Page 14 of 48  
 
 
 
 
 
Data Sheet  
HMC832  
HMC832 SPI. As a result, writes to the PLL Register Map are  
written directly and immediately, whereas the writes to the  
VCO Subsystem Register Map are written to the PLL subsystem  
Register 0x05 and forwarded via the internal VCO SPI (VSPI)  
to the VCO subsystem. This is a form of indirect addressing.  
they are not zero (Register 0x05[6:0] ≠ 0), autocalibration does  
not function.  
To ensure that the autocalibration functions, it is critical to  
write Register 0x05[6:0] = 0 after the last VCO subsystem write  
prior to an output frequency change triggered by a write to  
either Register 0x03 or Register 0x04.  
Note that VCO subsystem registers are write only and cannot be  
read. More information is available in the VCO Serial Port  
Interface (VSPI) section.  
However, it is impossible to write only Register 0x05[6:0] = 0  
(VCO_REGADDR) without writing Register 0x05[15:7]  
(VCO_DATA). Therefore, to ensure that the VCO_DATA  
(Register 0x05[15:7]) in VCO_REGADDR 0x00 is not changed,  
it is required to read the switch settings provided in Regis-  
ter 0x10[7:0], and then rewrite them to Register 0x05[15:7], as  
shown in the following example:  
VCO Serial Port Interface (VSPI)  
The HMC832 communicates with the internal VCO subsystem  
via an internal 16-bit VCO SPI. The internal serial port controls  
the step tuned VCO and other VCO subsystem functions.  
Note that the internal VCO subsystem SPI (VSPI) runs at  
the rate of the autocalibration FSM clock, tFSM, (see the VCO  
Autocalibration section) where the FSM clock frequency  
cannot be greater than 50 MHz. The VSPI clock rate is set  
by Register 0x0A[14:13].  
1. Read Register 0x10  
2. Write to Register 0x05 the following:  
a. Register 0x05[15:14] = Register 0x10[7:6]  
b. Register 0x05[13] = 1, reserved bit  
c. Register 0x05[12:8] = Register 0x10[4:0]  
d. Register 0x05[7:0] = 0  
Writes to the control registers of the VCO are handled indirectly  
via writes to Register 0x05 of the HMC832. A write to HMC832  
Register 0x05 causes the internal PLL subsystem to forward the  
packet, MSB first, across its internal serial link to the VCO  
subsystem, where it is interpreted.  
Changing the VCO subsystem configuration (VCO Subsystem  
Register Map section) without following this procedure results  
in a failure to lock to the desired frequency.  
VSPI Use of Register 0x05  
The packet data written into Register 0x05 is subparsed by logic  
at the VCO subsystem into the following three fields:  
For applications not using the read functionality of the  
HMC832 SPI, in which Register 0x10 cannot be read, it is  
possible to write Register 0x05 = 0x0 to set Register 0x05[6:0] =  
0, which also sets the VCO subband setting equal to zero  
(Register 0x05[15:7] = 0), effectively programming incorrect  
VCO subband settings and causing the HMC832 to lose lock.  
This procedure is then immediately followed by a write to:  
Field 1—Bits[2:0]: 3-bit VCO_ID, target subsystem address =  
000b.  
Field 2—Bits[6:3]: 4-bit VCO_REGADDR, the internal register  
address inside the VCO subsystem.  
Field 3—Bits[15:7]: 9-bit VCO_DATA, data field to write to the  
VCO register.  
Register 0x03, if in integer mode.  
Register 0x04, if in fractional mode.  
For example, to write 0_1111_1110 into Register 2 of the VCO  
subsystem (VCO_ID = 000b), and set the VCO output divider  
to divide by 62, the following needs to be written to  
Register 0x05 = 0_1111_1110b, 0010b, 000b or equivalently,  
Register 0x05 = 7F10.  
This write effectively retriggers the autocalibration state  
machine, forcing the HMC832 to relock whether in integer or  
fractional mode.  
This procedure causes the HMC832 to lose lock and relock after  
every VCO subsystem change. Typical output frequency and  
lock time is shown in Figure 27 and Figure 30, and is typically  
in the order of 100 μs for a phase settling of 10°, and is also  
dependent on loop filter design (loop filter bandwidth and loop  
filter phase margin).  
During autocalibration, the autocalibration controller writes  
into the VCO register address specified by the VCO_ID  
and VCO_REGADDR, as stored in Register 0x05[2:0] and  
Register 0x05[6:3], respectively. Autocalibration requires that  
these values be zero (Register 0x05[6:0] = 0); otherwise, when  
Rev. A | Page 15 of 48  
 
HMC832  
Data Sheet  
VCO SUBSYSTEM  
SPI  
LD_SDO  
VCO_REG0x03[1:0]  
VCO SUBSYSTEM  
VCO_REG0x01[0]  
PERFORMANCE  
TUNING  
VDD  
MASTER ENABLE  
VCO SUBSYSTEM  
VCO_REG0x01[5]  
VCO_REG0x03[3]  
EN  
VSPI  
VCO  
CONTROL  
RF_P  
÷1, ÷2, ÷4, ÷6, ... ÷62  
VCO_REG0x02[5:0]  
VCO_REG0x01[3]  
EN  
RF_N  
VCO_REG0x03[2]  
CONTROL CAL  
VCO_REG0x07[3:0]  
VCO_REG0x01[2]  
EN  
MODULATOR  
VCO  
VTUNE  
N
DIVIDER  
VCO_REG0x01[1], EN  
VCO_REG0x00[8:1]  
VCO CAL  
VOLTAGE  
VCO_REG0x00[0]  
CP  
PHASE  
FREQUENCY  
DETECTOR  
LOOP  
FILTER  
CHARGE  
PUMP  
XREFP  
R
DIVIDER  
Figure 39. PLL and VCO Subsystems  
The HMC832 contains a VCO subsystem that can be  
configured to operate in:  
feature is implemented in the internal state machine. It manages  
the selection of the VCO subband (capacitor selection) when a  
new frequency is programmed. The VCO switches may also be  
controlled directly via Register 0x05 for testing or for other  
special purpose operations. Other control bits specific to the  
VCO are also sent via Register 0x05.  
Fundamental frequency (fo) mode (1500 MHz to  
3000 MHz).  
Divide by N mode, where N = 2, 4, 6, 8 … 58, 60, 62  
(25 MHz to 1500 MHz).  
To use a step tuned VCO in a closed loop, the VCO must be  
calibrated such that the HMC832 knows which switch position  
on the VCO is optimum for the desired output frequency. The  
HMC832 supports autocalibration of the step tuned VCO. The  
autocalibration fixes the VCO tuning voltage at the optimum  
midpoint of the charge pump output, then measures the free  
running VCO frequency while searching for the setting which  
results in the free running output frequency that is closest to the  
desired phase-locked frequency. This procedure results in a  
phase-locked oscillator that locks over a narrow voltage range  
on the varactor. A typical tuning curve for a step tuned VCO is  
shown in Figure 40. Note that the tuning voltage stays in a  
narrow range over a wide range of output frequencies.  
All modes are VCO register programmable, as shown in  
Figure 39. One loop filter design can be used for the entire  
frequency of operation of the HMC832.  
VCO Calibration  
VCO Autocalibration  
The HMC832 uses a step tuned type VCO. A simplified step  
tuned VCO is shown in Figure 41. A step tuned VCO is a VCO  
with a digitally selectable capacitor bank allowing the nominal  
center frequency of the VCO to be adjusted or stepped by  
switching in and out of the VCO tank capacitors. Note that  
more than one capacitor can be switched in at a time.  
A step tuned VCO allows the user to center the VCO on the  
required output frequency while keeping the varactor tuning  
voltage optimized near the mid voltage tuning point of the  
HMC832 charge pump. This enables the PLL charge pump to  
tune the VCO over the full range of operation with both a low  
tuning voltage and a low tuning sensitivity (kVCO).  
The VCO switches are normally controlled automatically by the  
HMC832 using the autocalibration feature. The autocalibration  
Rev. A | Page 16 of 48  
 
 
 
 
Data Sheet  
HMC832  
4.0  
switch settings vs. time and temperature. The user does not  
CALIBRATED AT +85°C, MEASURED AT +85°C  
normally need to be concerned about which switch setting is  
used for a given frequency because this is handled by the  
autocalibration routine.  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
CALIBRATED AT +85°C, MEASURED AT –40°C  
CALIBRATED AT –40°C, MEASURED AT –40°C  
CALIBRATED AT –40°C, MEASURED AT +85°C  
CALIBRATED AT +27°C, MEASURED AT +27°C  
The accuracy required in the calibration affects the amount of  
time required to tune the VCO. The calibration routine searches  
for the best step setting that locks the VCO at the current  
programmed frequency and ensures that the VCO stays locked  
and performs well over its full temperature range without  
additional calibration, regardless of the temperature at which  
the VCO was calibrated.  
fMAX  
fMIN  
Autocalibration can also be disabled, thereby allowing manual  
VCO tuning. Refer to the Manual VCO Calibration for Fast  
Frequency Hopping section for a description of manual tuning.  
1330 1520 1710 1900 2090 2280 2470 2660 2850 3040  
VCO FREQUENCY (MHz)  
Figure 40. Typical VCO Tuning Voltage After Calibration  
The calibration is normally run automatically, once for every  
change of frequency. This ensures optimum selection of VCO  
SCK  
VSCK  
DTUNE  
VCO  
SUB-BAND  
SELECT  
SDI  
VSDO  
VSLE  
VCO  
VSPI  
HOST  
SEN  
SYNTHESIZER  
VTUNE  
CP  
LOOP  
FILTER  
VCOIP  
RF  
OUT  
VCO  
Figure 41. Simplified Step Tuned VCO  
Rev. A | Page 17 of 48  
 
 
HMC832  
Data Sheet  
N is the ratio of the target VCO frequency, fVCO, to the  
Autocalibration Using Register 0x05  
frequency of the PD, fPD, where N can be any rational number  
supported by the N divider.  
Autocalibration transfers switch control data to the VCO  
subsystem via Register 0x05. The address of the VCO subsystem  
in Register 0x05 is not altered by the autocalibration routine.  
The address and ID of the VCO subsystem in Register 0x05  
must be set to the correct value before autocalibration is  
executed. For more information see the VCO Serial Port  
Interface (VSPI) section.  
N is set by the integer (NINT = Register 0x03) and fractional  
(NFRAC = Register 0x04) register contents by Equation 2.  
N = NINT + NFRAC/224  
(2)  
The autocalibration state machine and the data transfers to the  
internal VCO subsystem SPI (VSPI) run at the rate of the FSM  
clock, tFSM, where the FSM clock frequency cannot be greater  
than 50 MHz.  
Automatic Relock on Lock Detect Failure  
It is possible by setting Register 0x07[13] to have the VCO  
subsystem automatically rerun the calibration routine and  
relock itself if lock detect indicates an unlocked condition for  
any reason. With this option the system attempts to relock only  
once.  
t
FSM = tXTAL × 2m  
(3)  
where m is 0, 2, 4, or 5 as determined by Register 0x0A[14:13].  
The expected number of VCO counts, V, is given by  
V = floor (N × 2n)  
(4)  
VCO Autocalibration on Frequency Change  
The nominal VCO frequency measured, fVCOM, is given by  
Assuming Register 0x0A[11] = 0, the VCO calibration starts  
automatically whenever a frequency change is requested. If it is  
desired to rerun the autocalibration routine for any reason at  
the same frequency, rewrite the frequency change with the same  
value and the autocalibration routine executes again without  
changing the final frequency.  
f
VCOM = V × fXTAL/(2n × R)  
where the worst case measurement error, fERR , is  
ERR fPD/2n + 1  
(5)  
(6)  
f
A 5-bit step tuned VCO, for example, nominally requires five  
measurements for calibration or in the worst case, six  
VCO Autocalibration Time and Accuracy  
measurements, and hence, seven VSPI data transfers of 20 clock  
cycles each. The measurement has a programmable number of  
wait states, k, of 128 FSM cycles defined by Register 0x0A[7:6] =  
k. Total calibration time, worst case, is given by  
The VCO frequency is counted for tMMT, the period of a single  
autocalibration measurement cycle.  
t
MMT = tXTAL × R × 2n  
(1)  
CAL = k128 tFSM + 6tPD 2n + 7 × 20 tFSM  
or equivalently  
CAL = tXTAL (6R × 2n + (140+(k × 128)) × 2m)  
(7)  
where:  
t
n is set by Register 0x0A[2:0] and results in measurement  
periods which are multiples of the PD period, tXTALR.  
R is the reference path division ratio currently in use,  
Register 0x02.  
t
(8)  
For guaranteed hold of lock, across temperature extremes, the  
resolution should be better than 1/8th the frequency step caused  
by a VCO subband switch change. Better resolution settings  
show no improvement.  
tXTAL is the period of the external reference (crystal) oscillator.  
The VCO autocalibration counter, on average, expects to  
register N counts, rounded down (floor) to the nearest integer,  
for every PD cycle.  
tPD  
CALIBRATION WINDOW  
REG0x02  
n
× 2  
tMMT = RT  
STOP  
XREF  
XTAL  
n
÷ 2  
÷ R  
START  
REGA[14:13]  
m = [0, 2, 4, 5]  
m
REGA[2:0]  
n = [0, 1, 2, 3, 5, 6, 7, 8]  
÷ 2  
50MHz MAX FOR  
FSM + VSPI CLOCKS  
V
CTR  
VCO  
FSM  
Figure 42. VCO Calibration  
Table 7. Autocalibration Example with fXTAL = 50 MHz, R = 1, m = 0  
Control Value Register 0x0A[2:0]  
n
0
1
2
3
5
2n  
1
2
4
8
32  
tMMT (µs)  
tCAL (µs)  
4.92  
5.04  
5.28  
5.76  
fERR Maximum  
25 MHz  
12.5 MHz  
6.25 MHz  
3.125 MHz  
781 kHz  
0
1
2
3
4
0.02  
0.04  
0.08  
0.16  
0.64  
8.64  
Rev. A | Page 18 of 48  
 
 
 
 
 
 
Data Sheet  
HMC832  
Control Value Register 0x0A[2:0]  
n
6
7
8
2n  
tMMT (µs)  
1.28  
2.56  
tCAL (µs)  
12.48  
20.16  
fERR Maximum  
5
6
7
64  
128  
256  
390 kHz  
95 kHz  
98 kHz  
5.12  
35.52  
Manual writes to the VCO switches are executed immediately as  
are writes to the integer and fractional registers when  
autocalibration is disabled. Therefore, frequency changes with  
manual control and autocalibration disabled requires a  
minimum of two serial port transfers to the PLL, once to set the  
VCO switches and once to set the PLL frequency.  
VCO Autocalibration Example  
The VCO subsystem must satisfy the maximum fPD limited by  
the two following conditions:  
N ≥ 16 (fINT), N ≥ 20.0 (fFRAC  
)
where N = fVCO/ fPD.  
When autocalibration is disabled, Register 0x0A[11] = 1, the  
VCO updates its registers immediately with the value written  
via Register 0x05. The VCO internal transfer requires 16 VSCK  
clock cycles after the completion of a write to Register 0x05.  
VSCK and the autocalibration controller clock are equal to the  
input reference divided by 0, 4, 16, or 32 as controlled by  
Register 0x0A[14:13].  
f
PD ≤ 100 MHz  
For example, if the VCO subsystem output frequency is to  
operate at 2.01 GHz and the crystal frequency is fXTAL = 50 MHz,  
R = 1, and m = 0 (see Figure 42), then tFSM = 20 ns (50 MHz).  
Note that when using autocalibration, the maximum autocali-  
bration finite state machine (FSM) clock cannot exceed 50 MHz  
(see Register 0x0A[14:13]). The FSM clock does not affect the  
accuracy of the measurement, it only affects the time to produce  
the result. This same clock is used to clock the 16-bit VCO  
serial port.  
Registers Required for Frequency Changes in Fractional  
Mode  
In fractional mode (Register 0x06[11] = 1), a large change of  
frequency may require main serial port writes to one of the  
three following registers  
If time to change frequencies is not a concern, then the  
calibration time for maximum accuracy can be set, and  
therefore, the measurement resolution is of no concern.  
The integer register, INTG, Register 0x03. This is required  
only if the integer part changes.  
Using an input crystal of 50 MHz (R = 1 and fPD = 50 MHz) the  
times and accuracies for calibration using Equation 6 and  
Equation 8 are listed in Table 7, where minimal tuning time is  
1/8th of the VCO band spacing.  
The VCO SPI register, Register 0x05. This is required only  
for manual control of VCO if Register 0x0A[11] = 1,  
autocalibration is disabled, or to change the VCO output  
divider value (VCO_REG 0x02), see Figure 39 for more  
information.  
Across all VCOs, a measurement resolution better than 800 kHz  
produces correct results. Setting m = 0 and n = 5, provides  
781 kHz of resolution and adds 8.6 μs of autocalibration time to  
a normal frequency hop. After the autocalibration sets the final  
switch value, 8.64 μs after the frequency change command, the  
fractional register is loaded, and the loop locks with a normal  
transient predicted by the loop dynamics. Therefore, as shown  
in this example, autocalibration typically adds about 8.6 μs to  
the normal time to achieve frequency lock. Use autocalibration  
for all but the most extreme frequency hopping requirements.  
The fractional register, Register 0x04. The fractional register  
write triggers autocalibration when Register 0x0A[11] = 0,  
and it is loaded into the modulator automatically after the  
autocalibration runs. If autocalibration is disabled, Regis-  
ter 0x0A[11] = 1, the fractional frequency change is loaded  
immediately into the modulator when the register is  
written with no adjustment to the VCO.  
Small steps in frequency in fractional mode, with autocalibration  
enabled (Register 0x0A[11] = 0), usually require only a single  
write to the fractional register. In a worst-case scenario, three  
main serial port transfers to the HMC832 could be required to  
change frequencies in fractional mode. If the frequency step is  
small and the integer part of the frequency does not change,  
then the integer register is not changed. In all cases, in frac-  
tional mode, it is necessary to write to the fractional register,  
Register 0x04, for frequency changes.  
Manual VCO Calibration for Fast Frequency Hopping  
When switching frequencies quickly is needed, it is possible to  
eliminate the autocalibration time by calibrating the VCO in  
advance and storing the switch number vs. frequency infor-  
mation in the host. This is accomplished by initially locking the  
HMC832 on each desired frequency using autocalibration, then  
reading and storing the selected VCO switch settings. The VCO  
switch settings are available in Register 0x10[7:0] after every  
autocalibration operation. The host must then program the  
VCO switch settings directly when changing frequencies.  
Rev. A | Page 19 of 48  
 
HMC832  
Data Sheet  
Registers Required for Frequency Changes in Integer  
Mode  
VCO Built-In Test (BIST) with Autocalibration  
The frequency limits of the VCO can be measured using the  
BIST features of the autocalibration machine by setting Regis-  
ter 0x0A[10] = 1, which freezes the VCO switches in one position.  
VCO switches may then be written manually with the varactor  
biased at the nominal midrail voltage used for autocalibration.  
For example, to measure the VCO maximum frequency use  
Switch 0, written to the VCO subsystem via Register 0x05 =  
000000001 0000 VCO_ID, where VCO_ID = 000b.  
In integer mode (Register 0x06[11] = 0), a change of frequency  
requires main serial port writes to the following registers:  
VCO SPI register, Register 0x05. This is required for  
manual control only of the VCO when Register 0x0A[11] =  
1 (autocalibration disabled) or when the VCO output  
divider value must change (VCO_REG 0x02).  
Integer register, Register 0x03. In integer mode, an  
integer register write triggers autocalibration when  
Register 0x0A[11] = 0 and it is loaded into the prescaler  
automatically after autocalibration runs. If autocalibration  
is disabled, Register 0x0A[11] = 1, the integer frequency  
change is loaded into the prescaler immediately when  
written with no adjustment to the VCO. Normally, changes  
to the integer register cause large steps in the VCO  
frequency; therefore, the VCO switch settings must be  
adjusted. Autocalibration enabled is the recommended  
method for integer mode frequency changes. If auto-  
calibration is disabled (Register 0x0A[11] = 1), a priori  
knowledge of the correct VCO switch setting and the  
corresponding adjustment to the VCO is required before  
executing the integer frequency change.  
When autocalibration is enabled (Register 0x0A[11] = 0), and a  
new frequency is written, autocalibration runs. The VCO  
frequency error relative to the command frequency is measured  
and the results are written to Register 0x11[19:0], where  
Register 0x11[19] is the sign bit. The result is written in terms of  
VCO count error (see Equation 4).  
For example, if the expected VCO is 2 GHz, the reference is  
50 MHz, and n is 6, expect to measure 2000/(50/26) = 2560  
counts. If a difference of −5 counts is measured in Register 0x11,  
then it means 2555 counts were actually measured. Hence, the  
actual frequency of the VCO is 5/2560 low, or 1.99609375 GHz,  
1 count ~ 781 kHz.  
PLL SUBSYSTEM  
Charge Pump (CP) and Phase Detector (PD)  
VCO Output Mute Function  
The phase detector (PD) has two inputs, one from the reference  
path divider and one from the RF path divider. When in lock,  
these two inputs are at the same average frequency and are fixed  
at a constant average phase offset with respect to each other.  
The frequency of operation of the PD is fPD. Most formulae  
related to step size, Δ-Σ modulation, timers, and so forth are  
functions of the operating frequency of the PD, fPD. fPD is also  
referred to as the comparison frequency of the PD.  
The HMC832 features an intelligent output mute function with  
the capability to disable the VCO output while maintaining  
fully functional PLL and VCO subsystems. The mute function is  
automatically controlled by the HMC832 and provides a  
number of mute control options including  
Automatic mute. This option automatically mutes the  
outputs during VCO calibration during output frequency  
changes. This mode can be useful in eliminating any out of  
band emissions during frequency changes, and ensuring  
that the system emits only the desired frequencies. It is  
enabled by writing VCO_REG 0x03[8:7] = 1d.  
The PD compares the phase of the RF path signal with that of  
the reference path signal and controls the charge pump output  
current as a linear function of the phase difference between the  
two signals. The output current varies linearly over a full 2π  
radians ( 360°) of input phase difference.  
Always mute (VCO_REG 0x03[8:7] = 3d). This mode is  
used for manual mute control.  
Charge Pump  
Typical isolation when the HMC832 is muted is always better  
than 50 dB, and is ~40 dB better than disabling the individual  
outputs of the HMC832 via VCO_REG 0x03[3:2], as shown in  
Figure 35.  
A simplified diagram of the charge pump is shown in Figure 43.  
The CP consists of four programmable current sources, two con-  
trolling the CP gain (Up Gain Register 0x09[13:7], and Down  
Gain Register 0x09[6:0]) and two controlling the CP offset,  
where the magnitude of the offset is set by Register 0x09[20:14],  
and the direction is selected by Register 0x09[21] = 1 for up and  
Register 0x09[22] = 1 for down offset.  
Also note that the VCO subsystem registers are not directly  
accessible. They are written to the VCO subsystem via PLL  
Register 0x05. See Figure 39 and the VCO Serial Port Interface  
(VSPI) section for more information about the VCO subsystem  
SPI.  
CP gain is used at all times, whereas CP offset is recommended  
for fractional mode of operation only. Typically, the CP up and  
down gain settings are set to the same value (Register 0x09[13:7] =  
Register 0x09[6:0]).  
Rev. A | Page 20 of 48  
 
 
 
Data Sheet  
HMC832  
For example, if both Register 0x09[13:7] and Register 0x09[6:0]  
are set to 50 decimal, the output current of each pump is 1 mA,  
and the phase frequency detector gain is kP = 1 mA/2π radians,  
or 159 μA/rad. See the Charge Pump (CP) and Phase Detector  
(PD) section for more information.  
Charge Pump Gain  
Charge pump up and down gains are set by Register 0x09[6:0]  
and Register 0x09[13:7], respectively. The current gain of the  
pump in amps/radian is equal to the gain setting of this register  
(Register 0x09) divided by 2π.  
Typical CP gain setting is set to 2 mA to 2.5 mA; however, lower  
values can also be used. Note that values less than 1 mA may  
result in degraded phase noise performance.  
UP OFFSET REG0x09[21]  
0µA TO 635µA  
UP GAIN  
REG0x09[13:7]  
5µA STEP  
REG0x09[20:14]  
0mA TO 2.54mA  
20µA STEP  
UP  
DN  
PD  
REF PATH  
VCO PATH  
LOOP  
FILTER  
DN OFFSET REG0x09[22]  
0µA TO 635µA  
DN GAIN  
REG0x09[6:0]  
5µA STEP  
REG0x09[20:14]  
0mA TO 2.54mA  
20µA STEP  
Figure 43. Charge Pump Gain and Offset Control  
Rev. A | Page 21 of 48  
 
HMC832  
Data Sheet  
Operation with CP offset influences the required configuration  
of the lock detect function. See the description of the lock  
detect function in the Lock Detect section.  
Charge Pump Phase Offset  
In integer mode, the phase detector operates with zero offset.  
The divided reference signal and the divided VCO signal arrive  
at the phase detector inputs at the same time. Integer mode  
does not require any CP offset current. When operating in  
integer mode, disable CP offset in both directions (up and  
down) by writing Register 0x09[22:21] = 00b, and set the CP  
offset magnitude to zero by writing Register 0x09[20:14] = 0.  
Phase Detector Functions  
Register 0x0B, the phase detector register, allows manual access  
to control special phase detector features.  
Setting Register 0x0B[5] = 0 masks the PD up output, which  
prevents the charge pump from pumping up.  
In fractional mode, CP linearity is of paramount importance.  
Any nonlinearity degrades phase noise and spurious perfor-  
mance. These nonlinearities are eliminated by operating the PD  
with an average phase offset, either positive or negative (either  
the reference or the VCO edge always arrives first at the PD,  
that is, leads).  
Setting Register 0x0B[6] = 0, masks the PD down output, which  
prevents the charge pump from pumping down.  
Clearing both Register 0x0B[5] and Register 0x0B[6] tristates  
the charge pump while leaving all other functions operating  
internally.  
PD force up (Register 0x0B[9] = 1) and PD force down  
(Register 0x0B[10] = 1) allows the charge pump to be forced up  
or down, respectively. This forces the VCO to the ends of the  
tuning range, which is useful in testing the VCO.  
A programmable CP offset current source is used to add dc  
current to the loop filter and to create the desired phase offset.  
Positive current causes the VCO to lead, negative current causes  
the reference to lead.  
The CP offset is controlled via Register 0x09. The phase offset is  
scaled from 0° to 360°, where they arrive a full cycle late.  
Reference Input Stage  
RVDD  
The specific level of charge pump offset current (Register 0x09,  
Bits[20:14]) is provided in Equation 9 and plotted in Figure 44.  
AC COUPLE  
XREFP  
20Ω  
80Ω  
Required CP Offset =  
100Ω  
min [(4.3 × 10−9 × fPD × ICP), 0.25 × ICP]  
(9)  
V
b
where:  
PD is the comparison frequency of the phase detector (Hz).  
CP is the full-scale current setting (A) of the switching charge  
Figure 45. Reference Path Input Stage  
f
I
The reference buffer provides the path from an external  
reference source (generally crystal-based) to the R divider, and  
eventually to the phase detector. The buffer has two modes of  
operation controlled by Register 0x08[21]. High gain (Regis-  
ter 0x08[21] = 0) is recommended below 200 MHz, and high  
frequency (Register 0x08[21] = 1) for 200 MHz to 350 MHz  
operation. The buffer is internally dc biased with 100 Ω internal  
termination. For a 50 Ω match, add an external 100 Ω resistor  
to ground followed by an ac coupling capacitor (impedance less  
than 1 Ω).  
pump (set in Register 0x09[6:0] and Register 0x09[13:7]).  
700  
CP CURRENT = 2.5mA  
600  
CP CURRENT = 2mA  
500  
400  
300  
CP CURRENT = 1mA  
At low frequencies, a relatively square reference is recommended to  
maintain a high input slew rate. At higher frequencies, use a  
square or sinusoid.  
200  
100  
0
Table 8 shows the recommended operating regions for different  
reference frequencies. If operating outside these regions, the  
device usually still operates, but with degraded reference path  
phase noise performance.  
0
20  
40  
60  
80  
100  
PHASE DETECTOR FREQUENCY (MHz)  
Figure 44. Recommended CP Offset Current vs. PD Frequency for Typical CP  
Gain Currents, Calculated Using Equation 9  
When operating at 50 MHz, the input referred phase noise of  
the PLL is between −148 dBc/Hz and −150 dBc/Hz at a 10 kHz  
offset, depending upon the mode of operation. To avoid degra-  
dation of the PLL noise contribution, the input reference signal  
should be 10 dB better than this floor. Note that such low levels  
are only necessary if the PLL is the dominant noise contributor  
and these levels are required for the system goals.  
Do not allow the required CP offset current to exceed 25% of  
the programmed CP current. It is recommended to enable the  
up offset and disable the down offset by writing Register 0x09,  
Bits[22:21] = 01b.  
Rev. A | Page 22 of 48  
 
 
 
 
Data Sheet  
HMC832  
Table 8. Reference Sensitivity  
Square Input  
Sinusoidal Input  
Recommended Power Range (dBm)  
Slew > 0.5 V/ns  
Recommended Swing (V p-p)  
Reference Input  
Frequency (MHz)  
Recommended  
Minimum  
0.6  
0.6  
0.6  
0.6  
0.6  
0.9  
1.2  
Maximum  
Recommended  
Minimum  
Maximum  
<10  
10  
25  
Yes  
Yes  
Yes  
Yes  
Yes  
Okay  
Okay  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
No  
No  
No  
No  
8
6
5
No  
No  
15  
15  
15  
12  
8
Okay  
Yes  
Yes  
Yes  
Yes  
50  
100  
150  
200  
4
3
Reference Path, R Divider  
The HMC832 supports two lock detect modes:  
The reference path, R divider is based on a 14-bit counter and  
can divide input signals by values from 1 to 16,383 and is  
controlled via Register 0x02.  
Analog LD, that only supports a fixed window size of 10 ns.  
Analog LD mode is selected by writing Register 0x07[6] = 0.  
Digital LD, that supports a user configurable window size,  
programmed in Register 0x07[11:7]. Digital LD is selected  
by writing Register 0x07[6] = 1.  
RF Path, N Divider  
The main RF path divider is capable of average divide ratios  
between 219 − 5 (524,283) and 20 in fractional mode, and 219 − 1  
(524,287) to 16 in integer mode. The VCO frequency range  
divided by the minimum N divider value places practical  
restrictions on the maximum usable PD frequency. For  
example, a VCO operating at 1.5 GHz in fractional mode with a  
minimum N divider value of 20 has a maximum PD frequency  
of 75 MHz.  
Lock Detect Configuration  
Optimal spectral performance in fractional mode requires CP  
current and CP offset current configuration discussed in detail  
in the Charge Pump (CP) and Phase Detector (PD) section.  
These settings in Register 0x09 impact the required LD window  
size in fractional mode of operation. To function, the required  
lock detect window size is provided by Equation 10 in fractional  
mode and Equation 11 in integer mode.  
Lock Detect  
The lock detect (LD) function verifies that the HMC832 is  
generating the desired frequency. It is enabled by writing  
Register 0x07[3] = 1. The HMC832 provides an LD indicator in  
one of two ways  
LD Window (sec) =  
I
CPOffset (A)  
1
+ 2.66×109(sec) +  
fPD(Hz)× ICP (A)  
f
PD (Hz)  
(10)  
(11)  
2
As an output available on the LD_SDO pin of the  
HMC832, (configuration is required to use the LD_SDO  
pin for LD purposes, for more information, see the Serial  
Port and Configuring the LD_SDO Pin for LD Output  
sections).  
1
LD Window (sec) =  
2× fPD  
where:  
fPD is the comparison frequency of the phase detector.  
Or reading from Register 0x12[1], where Bit 1 = 1 indicates  
a locked condition and Bit 1 = 0 indicates an unlocked  
condition.  
I
I
CP Offset is the charge pump offset current (Register 0x09[20:14]).  
CP is the full-scale current setting of the switching charge pump  
(Register 0x09[6:0] or Register 0x09[13:7]).  
The LD circuit expects the divided VCO edge and the divided  
reference edge to appear at the PD within a user specified time  
period (window), repeatedly. Either signal may arrive first, only  
the difference in arrival times is significant. The arrival of the  
two edges within the designated window increments an internal  
counter. When the count reaches and exceeds a user specified  
value (Register 0x07[2:0]) the HMC832 declares lock.  
If the result provided by Equation 10 is equal to 10 ns, analog  
LD can be used (Register 0x07[6] = 0); otherwise, digital LD is  
necessary (Register 0x07[6] = 1).  
Table 9 lists the required Register 0x07 settings to appropriately  
program the digital LD window size. From Table 9, select the  
closest value in the digital LD window size columns to the ones  
calculated in Equation 10 and Equation 11, and program  
Register 0x07[11:10] and Register 0x07[9:7] accordingly.  
Failure in registering the two edges in any one window resets  
the counter and immediately declares an unlocked condition.  
Lock is deemed to be reestablished when the counter reaches  
the user specified value (Register 0x07[2:0]) again.  
Rev. A | Page 23 of 48  
 
 
 
HMC832  
Data Sheet  
Table 9. Typical Digital Lock Detect Window  
LD Timer Speed  
Register 0x07  
inputs are different, and the phase difference of the two inputs  
at the PD varies rapidly over a range much greater than 2π  
radians. Because the gain of the PD varies linearly with phase  
up to 2π, the gain of a conventional PD cycles from high gain,  
when the phase difference approaches a multiple of 2π, to low  
gain, when the phase difference is slightly larger than a multiple  
of 0 radians. The output current from the charge pump cycles  
from maximum to minimum, even though the VCO has not yet  
reached its final frequency.  
Bits[11:10]  
Fastest 00  
01  
Digital Lock Detect Window Size Nominal Value (ns)  
6.5  
7
8
8.9  
9.2  
11  
17  
29  
36  
38  
47  
53  
68  
72  
88  
100 195  
130 255  
138 272  
172 338  
12.8 21  
13.3 22  
10  
7.1  
7.6  
Slowest 11  
LD Timer Divide  
Setting  
10.2 15.4 26  
010  
000 001  
011 100 101 110 111  
Register 0x07,  
Bits[9:7]  
The charge on the loop filter small capacitor may actually  
discharge slightly during the low gain portion of the cycle. This  
can make the VCO frequency reverse temporarily during  
locking. This phenomenon is known as cycle slipping. Cycle  
slipping causes the pull-in rate during the locking phase to vary  
cyclically. Cycle slipping increases the time to lock to a value  
greater than that predicted by normal small signal Laplace  
transform analysis.  
Digital Window Configuration Example  
Assuming, fractional mode, with a 50 MHz PD and a  
Charge pump gain of 2 mA (Register 0x09[13:7] = 0x64,  
Register 0x09[6:0] = 0x64),  
Up offset (Register 0x09[22:21] = 01b)  
Offset current magnitude of +400 μA (Register 0x09[20:14]  
= 0x50)  
The HMC832 PD features an ability to reduce cycle slipping  
during acquisition. The cycle slip prevention (CSP) feature  
increases the PD gain during large phase errors. The specific  
phase error that triggers the momentary increase in PD gain is  
set via Register 0x0B[8:7].  
Applying Equation 10, the required LD window size is:  
LD Window (sec) =  
0.4×103 (A)  
1
+ 2.66×109 (sec)+  
6
3  
6
50×10 (Hz)×2×10 (A)  
50×10 (Hz)  
Frequency Tuning  
2
The HMC832 VCO subsystem always operates in fundamental  
frequency of operation (1500 MHz to 3000 MHz). The HMC832  
generates frequencies below its fundamental frequency (25 MHz to  
1500 MHz) by tuning to the appropriate fundamental frequency  
and selecting the appropriate output divider setting (divide by  
2/4/6/ … 60/62) in VCO_REG 0x02[5:0].  
=13.33 ns  
Locating the Table 9 value that is closest to this result is, in this  
case, 13.3 ≈ 13.33. To set the digital LD window size, program  
Register 0x07[11:10] = 10b and Register 0x07[9:7] = 010b,  
according to Table 9.  
The HMC832 automatically controls frequency tuning in the  
fundamental band of operation, for more information see the  
VCO Autocalibration section.  
There is always a good solution for the lock detect window for a  
given operating point. The user should understand, however,  
that one solution does not fit all operating points. As observed  
from Equation 10 and Equation 11, if the charge pump offset or  
PD frequency is changed significantly, then the lock detect  
window may need to be adjusted.  
To tune to frequencies below the fundamental frequency range  
(<1500 MHz) it is required to tune the HMC832 to the appropriate  
fundamental frequency, then select the appropriate output divider  
setting (divide by 2/4/6/ … 60/62) in VCO_REG 0x02[5:0].  
Configuring the LD_SDO Pin for LD Output  
Integer Mode  
Setting Register 0x0F[7] = 1 and Register 0x0F[4:0] = 1 displays  
the lock detect flag on the LD_SDO pin of the HMC832. When  
locked, LD_SDO is high. As the name suggests, LD_SDO pin is  
multiplexed between the LD and the serial data output (SDO)  
signals. Therefore, LD is available on the LD_SDO pin at all  
times except when a serial port read is requested, in which case  
the pin reverts temporarily to the serial data output pin, and  
returns to the lock detect flag after the read is completed.  
The HMC832 is capable of operating in integer mode. For  
integer mode, set the following registers:  
Disable the fractional modulator, Register 0x06[11] = 0  
Bypass the modulator circuit, Register 0x06[7] = 1  
In integer mode, the VCO step size is fixed to that of the PD  
frequency. Integer mode typically has a 3 dB lower phase noise  
than fractional mode for a given PD operating frequency.  
Integer mode, however, often requires a lower PD frequency to  
meet step size requirements. The fractional mode advantage is  
that higher PD frequencies can be used; therefore, lower phase  
noise can often be realized in fractional mode. Disable charge  
pump offset when in integer mode.  
LD can be made available on LD_SDO pin at all times by  
writing Register 0x0F[6] = 1. In that case, the HMC832 does  
not provide any readback functionality because the SDO signal  
is not available.  
Cycle Slip Prevention (CSP)  
When changing VCO frequency and the VCO is not yet locked  
to the reference, the instantaneous frequencies of the two PD  
Rev. A | Page 24 of 48  
 
 
 
 
Data Sheet  
HMC832  
For example:  
OUT = 1402.5 MHz  
k = 2  
vco = 2,805 MHz  
Integer Frequency Tuning  
f
In integer mode the digital Δ-Σ modulator is shut off and the N  
divider (Register 0x03) may be programmed to any integer  
value in the range of 16 to 219 − 1. To run in integer mode,  
configure Register 0x06 (as described in the Integer Mode  
section), then program the integer portion of the frequency as  
explained by Equation 12, ignoring the fractional part.  
f
fXTAL = 50 MHz  
R = 1  
1. Disable the fractional modulator, Register 0x06[11] = 0  
2. Bypass the Δ-Σ modulator Register 0x06[7] = 1  
3. To tune to frequencies (<1500 MHz), select the appropriate  
output divider value VCO_REG 0x02[5:0].  
f
PD = 50 MHz  
NINT = 56  
FRAC = 0.1  
N
Register 0x04 = round(0.1 × 224) = round(1,677,721.6) =  
1,677,722.  
Writing to VCO subsystem registers (VCO_REG 0x02[5:0] and  
VCO_REG 0x03[0] in this case) is accomplished indirectly through  
PLL Register 5 (Register 0x05). More information on communi-  
cating with the VCO subsystem through PLL Register 0x05 is  
available in the VCO Serial Port Interface (VSPI) section.  
50×106  
1677722  
224  
fVCO  
56 +  
= 2805 MHz +1.192 Hz error  
1
(14)  
Fractional Mode  
fVCO  
2
fOUT  
=
=1402.5 MHz + 0.596 Hz error  
(15)  
The HMC832 is placed in fractional mode by setting the  
following registers:  
In this example, the output frequency of 1402.5 MHz is achieved by  
programming the 19-bit binary value of 56d = 0x38 into the  
INTG_REG bit in Register 0x03, and the 24-bit binary value of  
1677722d = 0x19999A into the FRAC bit in Register 0x04. The  
0.596 Hz quantization error can be eliminated using the exact  
frequency mode, if required. In this example, the output  
fundamental is divided by 2. Specific control of the output  
divider is required. See the VCO Subsystem Register Map  
section and description for details.  
Enable the fractional modulator, Register 0x06[11] = 1.  
Connect the Δ-Σ modulator in circuit, Register 0x06[7] = 0.  
Fractional Frequency Tuning  
This is a generic example, with the goal of explaining how to  
program the output frequency. Actual variables are dependant  
upon the reference in use.  
The HMC832 in fractional mode can achieve frequencies at  
fractional multiples of the reference. The frequency of the  
HMC832, fVCO, is given by  
Exact Frequency Tuning  
Due to quantization effects, the absolute frequency precision of  
a fractional PLL is normally limited by the number of bits in the  
fractional modulator. For example, a 24-bit fractional modulator  
has frequency resolution set by the phase detector (PD) compari-  
son rate divided by 224. The value 224 in the denominator is  
sometimes referred to as the modulus. Analog Devices PLLs use  
a fixed modulus, which is a binary number. In some types of  
fractional PLLs the modulus is variable, allowing exact frequency  
steps to be achieved with decimal step sizes. Unfortunately,  
small steps using small modulus values result in large spurious  
outputs at multiples of the modulus period (channel step size).  
For this reason, Analog Devices PLLs use a large fixed modulus.  
Normally, the step size is set by the size of the fixed modulus. In  
the case of a 50 MHz PD rate, a modulus of 224 would result in a  
2.98 Hz step resolution, or 0.0596 ppm. In some applications it is  
necessary to have exact frequency steps, and even an error of  
3 Hz cannot be tolerated.  
fXTAL  
R
fVCO  
=
(NINT + NFRAC ) = fINT + fFRAC  
(12)  
(13)  
f
OUT = fVCO/k  
where:  
OUT is the output frequency after any potential dividers.  
k is 1 for fundamental, or k = 2, 4, 6, … 58, 60, 62 depending on  
the selected output divider value (Register 0x05[5:0] indirectly  
to VCO_REG 0x02[5:0]).  
f
N
INT is the integer division ratio, Register 0x03, an integer  
number between 20 and 524,284.  
N
FRAC is the fractional part, from 0.0 to 0.99999..., NFRAC =  
Register 0x04/224.  
R is the reference path division ratio, Register 0x02.  
XTAL is the frequency of the reference oscillator input.  
PD is the PD operating frequency, fXTAL/R.  
f
f
Fractional PLLs are able to generate exact frequencies (with  
zero frequency error) if N can be exactly represented in binary  
(for example, N = 50.0, 50.5, 50.25, 50.75, and so forth). Note  
that, some common frequencies cannot be exactly represented.  
For example, NFRAC = 0.1 = 1/10 must be approximated as  
round((0.1 x 224)/224 ) ≈ 0.100000024. At fPD = 50 MHz, this  
Rev. A | Page 25 of 48  
 
 
 
HMC832  
Data Sheet  
translates to a 1.2 Hz error. The exact frequency mode of the  
HMC832 addresses this issue and can eliminate quantization  
error by programming the channel step size to fPD/10 in  
Register 0x0C to 10 (in this example). More generally, this  
feature can be used whenever the desired frequency, fVCO, can be  
exactly represented on a step plan where there are an integer  
number of steps (<214) across integer-N boundaries.  
Mathematically, this situation is satisfied if  
(the denominator or the modulus of the Δ-Σ modulator) so that  
the Δ-Σ modulator phase accumulator repeats at an exact  
period related to the interval frequency (fVCOk − fVCO(k−1)) in  
Figure 46. Consequently, the shortened accumulator results in  
more frequent repeating patterns and as a result often leads to  
spurious emissions at multiples of the repeating pattern period,  
or at harmonic frequencies of fVCOk − fVCO(k−1). For example, in  
some applications, these intervals might represent the spacing  
between radio channels, with the spurious occurring at  
multiples of the channel spacing.  
fVCOk mod( fGCD ) = 0  
(16)  
f
PD  
214  
where fGCD = GCD( fVCO1, fPD ) and fGCD  
In comparison, the Analog Devices method is able to generate  
exact frequencies between adjacent integer-N boundaries while  
still using the full 24-bit phase accumulator modulus, thus  
achieving exact frequency steps with a high phase detector  
comparison rate, which allows Analog Devices PLLs to maintain  
excellent phase noise and spurious performance in the exact  
frequency mode.  
where:  
GCD means greatest common divisor.  
f
f
PD = frequency of the phase detector.  
VCOk is the channel step frequency where 0 < k < 224−1, as shown  
in Figure 46.  
Some fractional PLLs are able to achieve these exact frequencies  
by adjusting (shortening) the length of the phase accumulator  
fVCO = fVCO2  
INTEGER  
BOUNDARY  
INTEGER  
BOUNDARY  
14  
14  
14  
fN + 1  
fN  
fVCO1  
fVCO2  
fVCO3  
fVCO4  
fVCO  
fVCO  
fVCO  
– 2  
– 1  
fN + 1 fN = fPD  
Figure 46. Exact Frequency Tuning  
Rev. A | Page 26 of 48  
 
 
 
Data Sheet  
HMC832  
Register 0x0C =  
fPD  
GCD(( fVCOk+1 fVCOk ), fPD  
Using Exact Frequency Mode  
If the constraint in Equation 16 is satisfied, the HMC832 is able  
to generate signals with zero frequency error at the desired  
VCO frequency. Exact frequency mode can be reconfigured for  
each target frequency, or be setup for a fixed fGCD that applies to  
all channels.  
=
=
)
61.44×106  
GCD(100×103 , 61.44×106 )  
61.44×106  
= 3072d = 0xC00  
Configuring Exact Frequency Mode for a Particular  
Frequency  
20000  
4. To program Register 0x04, the closest integer-N boundary  
frequency (fN) that is less than the desired VCO frequency  
(fVCO) must be calculated: fN = fPD × NINT. Using the current  
example  
1. Calculate and program the integer register setting  
Register 0x03 = NINT = floor(fVCO/fPD)  
where the floor function is the rounding down to the  
nearest integer.  
fN = fPD × NINT = 45 × 61.44 × 106 = 2764.8 MHz, then  
2. Then calculate the integer boundary frequency  
Register 0x04 =  
24  
2 ( fVCO fN )  
fN = NINT × fPD.  
ceil  
ceil  
=
fPD  
3. Calculate and program the exact frequency register value  
24  
6
6
2 (2800.2×10 2764.8×10 )  
61.44×106  
Register 0x0C = fPD/fGCD  
=
where fGCD = GCD(fVCO,fPD).  
4. Calculate and program the fractional register setting  
9666560d = 0x938000  
24  
Exact Frequency Channel Mode  
2 ( fVCOk fN )  
NFRAC = ceil  
Register 0x04  
When multiple, equally spaced, exact frequency channels are  
needed that fall within the same interval (that is, fN ≤ fVCOk  
N + 1) where fVCOk is shown in Figure 46 and 1 ≤ k ≤ 214, it is  
possible to maintain the same integer-N (Register 0x03) and  
exact frequency register (Register 0x0C) settings and only  
update the fractional register (Register 0x04) setting. The exact  
frequency channel mode is possible when Equation 16 is  
satisfied for at least two equally spaced adjacent frequency  
channels, that is, the channel step size.  
fPD  
<
where ceil is the ceiling function meaning round up to the  
nearest integer.  
f
Example: to configure the HMC832 for exact frequency mode  
at fVCO = 2800.2 MHz, where the PD rate (fPD) = 61.44 MHz,  
proceed as follows:  
1. Check Equation 16 to confirm that the exact frequency  
mode for this fVCO is possible.  
To configure the HMC832 for exact frequency channel mode,  
initially and only at the beginning, the integer (Register 0x03)  
and exact frequency (Register 0x0C) registers need to be  
programmed for the smallest fVCO frequency (fVCO1 in Figure 46),  
as follows:  
f
PD  
fGCD = GCD( fVCO , fPD ) and fGCD  
214  
f
GCD = GCD(2800.2 × 106, 61.44 × 106) =  
61.44×106  
120 × 103 >  
= 3750  
214  
1. Calculate and program the integer register setting Regis-  
ter 0x03 = NINT = floor(fVCO1/fPD), where fVCO1 is shown in  
Figure 46 and corresponds to the minimum channel VCO  
frequency. Then, the lower integer boundary frequency is  
Because Equation 16 is satisfied, the HMC832 can be  
configured for exact frequency mode at fVCO = 2800.2 MHz by  
continuing with the remaining steps.  
given by fN = NINT × fPD  
.
2. Calculate NINT  
2. Calculate and program the exact frequency register value  
Register 0x0C = fPD/fGCD, where fGCD = GCD((fVCOk + 1 − fVCOk),  
N
INT = Register 0x03 =  
6
fPD) = greatest common divisor of the desired equidistant  
f
2800.2×10  
VCO1   
floor  
= floor  
= 45d = 0x2D  
61.44×106  
fPD  
channel spacing and the PD frequency ((fVCOk + 1 − fVCOk  
and fPD).  
)
3. Calculate the value for Register 0x0C  
Rev. A | Page 27 of 48  
HMC832  
Data Sheet  
To switch between various equally spaced intervals (channels)  
only the fractional register (Register 0x04) needs to be  
programmed to the desired VCO channel frequency (fVCOk) in  
the following manner:  
3. To program Register 0x04, the closest integer-N boundary  
frequency, fN, that is less than the smallest channel VCO  
frequency, fVCO1, must be calculated (fN = floor(fVCO1/fPD)).  
Using the current example:  
24  
6   
2800.2×10  
2 ( fVCOk fN )  
fN = fPD × floor  
=
N
= ceil  
Register 0x04 =  
61.44×106  
FRAC  
fPD  
45×61.44×106 = 2764.8MHz  
where fN = floor(fVCO1/fPD), and fVCO1, as shown in Figure 46,  
represents the smallest channel VCO frequency that is greater  
than fN.  
Then, for Channel 1,  
24  
2 ( fVCO1 fN )  
Register 0x04 = ceil  
,
Example: to configure the HMC832 for the exact frequency  
mode for equally spaced intervals of 100 kHz, where the first  
channel (Channel 1) = fVCO1 = 2800.200 MHz and the PD rate  
(fPD) = 61.44 MHz, proceed as follows:  
fPD  
where fVCO1 = 2800.2 MHz.  
24  
6
6
2 (2800.2×10 2764.8×10 )  
61.44×106  
= ceil  
= 9666560d = 0x938000  
1. Check that the exact frequency mode for this fVCO1  
=
2800.2 MHz (Channel 1) and fVCO2 = 2800.2 MHz +  
100 kHz = 2800.3 MHz (Channel 2) is possible.  
4. To change from Channel 1 (fVCO1 = 2800.2 MHz) to  
Channel 2 (fVCO2 = 2800.3 MHz), only Register 0x04 needs  
to be programmed, as long as all of the desired exact  
frequencies, fVCOk (Figure 46), fall between the same  
integer-N boundaries (fN < fVCOk < fN + 1). In that case,  
fGCD1 = GCD( fVCO1, fPD ) and  
f
PD  
fGCD1  
and f  
= GCD( fVCO2 , fPD  
)
(17)  
GCD2  
214  
Register 0x04 =  
f
PD  
and fGCD2  
24  
6
6
214  
2 (2800.3×10 2764.8×10 )  
61.44×106  
ceil  
=
9693867d = 0x93EAAB,and so on.  
f
GCD1 = GCD(2800.2×106,61.44×106) =  
61.44×106  
Seed Register  
120×103 >  
= 3750  
The start phase of the fractional modulator digital phase  
accumulator (DPA) can be set to one of four possible default  
values via the seed register, Register 0x06[1:0]. The HMC832  
automatically reloads the start phase (seed value) into the DPA  
every time a new fractional frequency is selected. Certain zero  
or binary seed values may cause spurious energy correlation at  
specific frequencies. For most cases a random (not zero and not  
binary) start seed is recommended (Register 0x06[1:0] = 2).  
214  
fGCD2 = GCD(2800.3×106 ,61.44×106 ) =  
61.44×106  
20×103 >  
= 3750  
214  
2. If Equation 16 is satisfied for at least two of the equally  
spaced interval (channel) frequencies fVCO1, fVCO2, fVCO3, ...  
VCON, as it is in Equation 17, HMC832 exact frequency  
SOFT RESET AND POWER-ON RESET  
f
The HMC832 features a hardware power-on reset (POR). All  
chip registers are reset to default states approximately 250 μs  
after power up.  
channel mode is possible for all desired channel  
frequencies, and can be configured as follows:  
Register 0x03 =  
The PLL subsystem SPI registers can also be soft reset by an SPI  
write to Register 0x00. Note that the soft reset does not clear the  
SPI mode of operation referred to in the Serial Port section.  
Note that the VCO subsystem is not affected by the PLL soft  
reset; the VCO subsystem registers can only be reset by  
removing the power supply.  
6
f
2800.2×10  
61.44×106  
VCO1   
floor  
= floor  
= 45d = 0x2D  
61.44×106  
fPD  
Register 0x0C =  
fPD  
=
=
GCD(( fVCOk+1 fVCOk ), fPD  
61.44×106  
)
GCD(100×103 ,61.44×106 )  
If external power supplies or regulators have rise times slower  
than 250 μs, then it is advised to write to the SPI reset register  
(Register 0x00[5] = 1) immediately after power up, before any  
other SPI activity. This write procedure ensures starting from a  
known state.  
= 3072d = 0xC00  
20000  
where (fVCOk+1 fVCOk) is the desired channel spacing  
(100 kHz in this example).  
Rev. A | Page 28 of 48  
 
 
Data Sheet  
HMC832  
Register 0x0F to 1 to prevent automux of the SDO. The phase  
noise performance at this output is poor and uncharacterized.  
Also, the GPO output should not be toggling during normal  
operation because it may degrade the spectral performance.  
POWER-DOWN MODE  
Note that the VCO subsystem is not affected by the CEN or soft  
reset. Therefore, device power-down is a two step process.  
1. Power down the VCO by writing 0 to VCO Register 1 via  
Register 0x05 .  
Note that there are additional controls available, which may be  
helpful when sharing the bus with other devices.  
2. Power-down the PLL by pulling the CEN pin (Pin 17) low  
(assuming there are no SPI overrides (Register 0x01[0] = 1)).  
Pulling the CEN pin low disables all analog functions and  
internal clocks. Current consumption typically drops below  
10 μA in the power-down state. The serial port still  
To disable the driver completely, set Register 0x08[5] = 0 (it  
takes precedence over all else).  
To disable either the pull-up or pull-down sections of the  
driver, Register 0x0F[8] = 1 or Register 0x0F[9] = 1,  
respectively.  
responds to normal communication in power-down mode.  
Example scenarios are listed in Table 11. The signals that are  
available on the GPO are selected by changing the GPO Select  
Register 0x0F[4:0].  
It is possible to ignore the CEN pin by setting Register 0x01[0]  
= 0. Control of the power-down mode then comes from the  
serial port register, Register 0x01[1].  
It is also possible to leave various blocks turned on when in  
power-down (see Register 0x01), as listed in Table 10.  
Table 11. Driver Scenarios  
Scenario  
Action  
Drive SDO During Reads, Tristate None required  
Otherwise (Allow Bus Sharing)  
Table 10. Bit and Block Assignments for Register 0x01  
Bit Assignment  
Block Assignment  
Internal bias reference sources  
PD block  
CP block  
Reference path buffer  
VCO path buffer  
Drive SDO During Reads, Lock  
Detect Otherwise  
Set GPO Select Register 0x0F[4:0]  
= 00001b (default)  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Set Register 0x0F[7] = 1, prevent  
GPO driver disable  
Always Drive Lock Detect  
Set Register 0x0F[6] = 1, prevent  
automux of SDO  
Set the GPO Select  
Register 0x0F[4:0] = 00001  
(default)  
Set Register 0x0F[7] = 1, prevent  
GPO driver disable  
Digital I/O test pads  
To mute the output but leave the PLL and VCO locked, see the  
VCO Output Mute Function section.  
GENERAL-PURPOSE OUTPUT (GPO) PIN  
CHIP IDENTIFICATION  
The PLL shares the LD_SDO (lock detect/serial data output)  
pin to perform various functions. Although the pin is most  
commonly used to read back registers from the chip via the SPI,  
it is also capable of exporting a variety of signals and real-time  
test waveforms (including lock detect). It is driven by a tristate  
CMOS driver with ~200 Ω ROUT. It has logic associated with it  
to dynamically select whether the driver is enabled, and to  
decide which data to export from the chip.  
PLL subsystem version information may be read by reading the  
content of read only register, chip_ID in Register 0x00. It is not  
possible to read the VCO subsystem version.  
SERIAL PORT  
The SPI protocol has the following general features:  
3-bit chip address, can address up to eight devices  
connected to the serial bus.  
In its default configuration, after power-on reset, the output  
driver is disabled, and only drives during appropriately  
addressed SPI reads. This allows it to share the output with  
other devices on the same bus.  
Wide compatibility with multiple protocols from multiple  
vendors.  
Simultaneous write/read during the SPI cycle.  
5-bit address space.  
3-wire for write only capability, 4-wire for read/write  
capability.  
The pin driver is enabled if the chip is addressed; that is, the last  
three bits of SPI cycle = 000b before the rising edge of SEN. If  
SEN rises before SCK has clocked in an invalid (non zero) chip  
address, the HMC832 starts to drive the bus.  
Typical serial port operation can be run with SCLK at speeds up  
to 50 MHz.  
To monitor any of the GPO signals, including lock detect, set  
Register 0x0F[7] = 1 to keep the SDO driver always on. This  
stops the LDO driver from tristating and means that the SDO  
line cannot be shared with other devices.  
Serial Port Initialization at Power-Up  
At power-up, it is required that both SEN and SCK lines are  
initially held low, and that the first rising edge occurs on the  
SCK line before any rising edges occur on the SEN line.  
The HMC832 naturally switches away from the GPO data and  
exports the SDO during an SPI read. To prevent this automatic  
data selection, and always select the GPO signal, set Bit 6 of  
Rev. A | Page 29 of 48  
 
 
 
 
 
 
HMC832  
Data Sheet  
If the first rising edge occurs on the SEN line before it does on  
the SCK line the HMC832LP6GE SPI interface does not  
function. In that case, it is necessary to cycle the power to the  
off and on, and repeat the previous recommended sequence  
(hold both signals low at power-up and ensure that the first  
rising edge occurs on the SCK line).  
3. The master places a 5-bit register address to be written to,  
R4:R0, MSB first, on the next five falling edges of SCLK  
(25th to 29th falling edges).  
4. The slave shifts the register bits on the next five rising  
edges of SCLK (25th to 29th rising edges).  
5. The master places 3-bit chip address, A2:A0, MSB first, on  
the next three falling edges of SCLK (30th to 32nd falling  
edges). Analog Devices reserves Chip Address A2 to Chip  
Address A0 = 000 for all RF PLLs with integrated VCOs.  
6. The slave shifts the chip address bits on the next three  
rising edges of SCLK (30th to 32nd rising edges).  
Serial Port Write Operation  
SPI write specifications are listed in the Table 2 in the SPI Write  
Timing Characteristics section and a typical write cycle is  
shown in Figure 47. The SPI write operation is as follows:  
7. The master asserts SEN after the 32nd rising edge of SCLK.  
8. The slave registers the SDI data on the rising edge of SEN.  
1. The master (host) places 24-bit data, D23:D0, MSB first, on  
SDI on the first 24 falling edges of SCLK.  
2. The slave (HMC832) shifts in data on SDI on the first 24  
rising edges of SCLK.  
t5  
1
2
3
22  
23  
24  
25  
26  
30  
31  
32  
SCK  
t1  
t2  
t6  
SDI  
x
D23  
D22  
D2  
D1  
D0  
R4  
R3  
R0  
A2  
A1  
A0  
x
SEN  
t3  
t4  
Figure 47. Serial Port Timing Diagram, Write  
Rev. A | Page 30 of 48  
 
Data Sheet  
HMC832  
Serial Port Read Operation  
5. The master places the 3-bit chip address, A2:A0, MSB first,  
on the next three falling edges of SCK (30th to 32nd falling  
edges). The chip address is always 000b.  
In general, the LD_SDO line is always active during the  
write cycle. During any SPI cycle, LD_SDO contains the  
data from the current address written in Register 0x0[4:0].  
If Register 0x0[4:0] is not changed, the same data is always  
present on LD_SDO during a SPI cycle.  
6. The slave shifts the chip address bits on the next three  
rising edges of SCK (30th to 32nd rising edges).  
7. The master asserts SEN after the 32nd rising edge of SCK.  
8. The slave registers the SDI data on the rising edge of SEN.  
9. The master clears SEN to complete the the address transfer  
of the two part read cycle.  
If a read is required from a specific address, it is necessary to  
write the required address to Register 0x0[4:0] in the first SPI  
cycle, then in the next SPI cycle, the desired data becomes  
available on LD_SDO. A typical read cycle is shown in Figure 48.  
10. If a write data to the chip is not needed at the same time as  
the second cycle occurs, then it is recommended to simply  
rewrite the same contents on SDI to Register 0x00 on the  
readback portion of the cycle.  
An example of the two cycle procedure to read from any  
random address is as follows:  
11. The master places the same SDI data as the previous cycle  
on the next 32 falling edges of SCK.  
12. The slave (HMC832) shifts the SDI data on the next 32  
rising edges of SCK.  
1. The master (host), on the first 24 falling edges of SCLK  
places 24-bit data, D23:D0, MSB first, on SDI as shown in  
Figure 48. Set D23:D5 to zero. D4:D0 = address of the  
register to be read on the next cycle.  
13. The slave places the desired read data (that is, data from  
the address specified in Register 0x00[4:0] of the first  
cycle) on LD_SDO, which automatically switches to SDO  
mode from LD mode, disabling the LD output.  
14. The master asserts SEN after the 32nd rising edge of SCK to  
complete the cycle and revert back to lock detect on  
LD_SDO.  
2. The slave (HMC832) shifts in data on SDI on the first 24  
rising edges of SCK.  
3. The master places the 5-bit register address , R4:R0, (the  
read address register), MSB first, on the next five falling  
edges of SCK (25th to 29th falling edges). R4:R0 = 00000.  
4. The slave shifts the register bits on the next five rising  
edges of SCK (25th to 29th rising edges).  
Rev. A | Page 31 of 48  
HMC832  
Data Sheet  
FIRST CYCLE  
1
18  
19  
20  
24  
25  
29  
30  
31  
32  
SCK  
SDI  
t7  
t1  
t2  
t6  
x
D5  
D4  
D0  
R4  
R3  
R0  
A2  
A1  
A0  
x
READ ADDRESS  
x
REGISTER ADDRESS = 00000  
CHIP ADDRESS = 000  
t5  
LD_SDO  
OR  
TRISTATE  
LD/GPO  
x
x
x
x
x
x
x
x
x
x
LD/GPO  
SEN  
t3  
t4  
SECOND CYCLE  
1
18  
19  
20  
24  
25  
29  
30  
31  
32  
SCK  
SDI  
t7  
t1  
t6  
x
D23  
D5  
D4  
D0  
R4  
R3  
R0  
A2  
A1  
A0  
x
1
LD/GPO  
D23  
D22  
D2  
D1  
D0  
R4  
R0  
A2  
A1  
A0  
LD/GPO  
LD_SDO  
SEN  
t3  
1
FOR MORE INFORMATION ON USING THE GPO PIN WHILE IN SPI OPEN MODE PLEASE SEE SERIAL PORT SECTION.  
Figure 48. Serial Port Timing Diagram, Read  
Rev. A | Page 32 of 48  
 
Data Sheet  
HMC832  
APPLICATIONS INFORMATION  
Using the HMC832 with a tunable reference, as shown in Figure 51,  
it is possible to drastically improve spurious emissions performance  
across all frequencies.  
Large bandwidth (25 MHz to 3000 MHz), industry leading  
phase noise and spurious performance, excellent noise floor  
(−160 dBc/Hz), coupled with a high level of integration make  
the HMC832 ideal for a variety of applications; as an RF or IF  
stage local oscillator (LO).  
PLL  
HMC832  
DAC  
PLL  
÷2  
HMC1044LP3E  
HMC832  
DAC  
HMC795LP5E  
HMC900LP5E  
Figure 49. HMC832 in a Typical Transmit Chain  
PLL  
HMC832  
HMCAD1520  
ADC  
CMIO  
CMQO  
0
PLL  
90  
HMC1044LP3E  
HMC832  
HMCAD1520  
ADC  
HMC597LP4E  
HMC960LP4E  
HMC900LP5E  
Figure 50. HMC832 in a Typical Receive Chain  
TUNABLE REFERENCE  
25MHz TO 100MHz  
PLL  
PLL  
HMC832  
HMC832  
CRYSTAL  
OSCILLATOR  
Figure 51. HMC832 Used as a Tunable Reference for HMC832  
Rev. A | Page 33 of 48  
 
 
HMC832  
Data Sheet  
it is filtered by the loop filter. The internal HMC832 setup and  
divide ratios are changed in the opposite direction accordingly  
so that the HMC832 generates identical output frequency as  
shown in Figure 18, without the spurious emissions inside the  
loop bandwidth. Using these same procedures, in Figure 19, the  
graph is generated by observing and plotting the magnitude of  
the largest spur only, at any offset, at each output frequency,  
while using a fixed 50 MHz reference and a tunable 47.5 MHz  
reference.  
POWER SUPPLY  
The HMC832 is a high performance, low noise device. In some  
cases, phase noise and spurious performance may be degraded  
by noisy power supplies. To achieve maximum performance  
and ensure that power supply noise does not degrade the per-  
formance of the HMC832 it is recommended to use the Analog  
Devices low noise, high power supply rejection ratio (PSRR)  
regulator, the HMC1060LP3E. Using the HMC1060LP3E lowers  
the design risk and cost, and ensures that the performance shown  
in the Typical Performance Characteristics section can be achieved.  
The HMC832 features an internal autocalibration process that  
seamlessly calibrates the HMC832 when a frequency change  
is executed (see Figure 27 and Figure 30). Typical frequency  
settling time that can be expected after any frequency change  
(writes to Register 0x03 or Register 0x04 ) is shown in Figure 27  
with autocalibration enabled (Register 0x0A[11] = 0). A fre-  
quency hop of 5 MHz is shown in Figure 27; however the settling  
time is independent of the size of the frequency change. Any size  
frequency hop has a similar settling time with autocalibration  
enabled. Figure 32 shows the typical tuning voltage after calibration  
where once the HMC832 is calibrated at any temperature, the  
calibration setting holds across the entire operating range of the  
HMC832 (−40°C to +85°C). Figure 32 shows that the tuning  
voltage is maintained within a narrow operating range for worst  
case scenarios where calibration was executed at one temperature  
extreme and the device is operating at the other extreme.  
PROGRAMMABLE PERFORMANCE TECHNOLOGY  
For low power applications that do not require maximum noise  
floor performance, the HMC832 features the ability to reduce  
current consumption by 50 mA (power consumption by 165 mW)  
at the cost of decreasing phase noise floor performance by ~5 dB.  
High performance is enabled by writing VCO_REG 0x03[1:0] =  
3d, and it is disabled (low current consumption mode enabled)  
by writing VCO_REG 0x03[1:0] = 1d. High performance mode  
improves noise floor performance at the cost of increased current  
consumption. Resulting current consumption and phase noise  
floor performance are shown in Figure 33 and Figure 36.  
LOOP FILTER AND FREQUENCY CHANGES  
R3  
R4  
CP  
VTUNE  
C4  
C1  
C3  
R2  
C2  
For applications that require fast frequency changes, the HMC832  
supports manual calibration that enables faster settling times  
(see Figure 28 and Figure 31). Manual calibration needs to be  
executed only once for each individual HMC832, at any tempera-  
ture, and is valid across all temperature operating ranges of the  
HMC832. More information about manual calibration is available  
in the Manual VCO Calibration for Fast Frequency Hopping  
section. A Frequency hop of 5 MHz is shown in Figure 28 and  
Figure 31; however, the settling time is independent of the size  
of the frequency change. Any size frequency hop has a similar  
settling time with autocalibration disabled (Register 0x0A[11] = 1).  
Figure 52. Loop Filter Design  
All PLLs with integrated VCOs exhibit integer boundary spurs  
at harmonics of the reference frequency. As seen in Figure 18,  
the plot shows the worst case spurious scenario where the  
harmonic of the reference frequency (50 MHz) is within the  
loop filter bandwidth of the fundamental frequency of the  
HMC832.  
The tunable reference changes the reference frequency from  
50 MHz in Figure 18 to 47.5 MHz in Figure 16 to distance the  
harmonic of the reference frequency (spurious emissions) away  
from the fundamental output frequency of the HMC832 so that  
Table 12. Loop Filter Designs Used in Typical Performance Characteristics Graphs  
Loop Filter  
Type  
Loop Filter BW  
(kHz)  
Loop Filter Phase  
Margin  
C1  
(pF)  
C2  
(nF)  
C3  
(pF)  </