HT1621芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

HT1621

RAM Mapping 32´4 LCD Controller for I/O mC

Features

·

Operating voltage : 2.4V~5.2V

·

8 kinds of time base/WDT clock sources

32´4 LCD driver

Built-in 32´4 bit display RAM

3-wire serial interface

Built-in 256kHz RC oscillator

External 32.768kHz crystal or 256kHz

frequency source input

·

Selection of 1/2 or 1/3 bias, and selection of

1/2 or 1/3 or 1/4 duty LCD applications

Internal time base frequency sources

Two selectable buzzer frequencies

(2kHz/4kHz)

Internal LCD driving frequency source

Software configuration feature

Data mode and command mode

instructions

·

R/W address auto increment

Three data accessing modes

VLCD pin for adjusting LCD operating

voltage

·

Power down command reduces power

consumption

·

Built-in time base generator and WDT

Time base or WDT overflow output

General Description

systems. Only three or four lines are required

for the interface between the host controller

and the HT1621. The HT1621 contains a power

down command to reduce power consumption.

The HT1621 is a 128 pattern (32´4), memory

mapping, and multi-function LCD driver. The

S/W configuration feature of the HT1621

makes it suitable for multiple LCD applica-

tions including LCD modules and display sub-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM

4

32

Ö

8

32

Ö

8

48

Ö

8

64

Ö

16

48

Ö

16

64

Ö

16

64

SEG

32

Built-in Osc.

Crystal Osc.

Ö

1

April 21, 2000

HT1621

Block Diagram

D

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p

l

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R

A

M

O

S

C

O

S

C

I

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o

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r

o

l

C

O

M

0

3

C

S

a

n

d

T

i

m

i

n

g

R

D

R

C

S

C

i

r

c

u

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L

B

C

D

r

i

v

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/

W

i

a

s

C

i

r

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u

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E

G

0

3

D

A

T

A

S

V

1

V

D

L

C

D

V

S

W

a

t

c

h

d

y

o

g

T

i

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B

Z

T

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F

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q

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c

a

n

d

I

R

Q

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e

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a

t

o

r

T

i

m

e

B

a

s

e

G

e

n

e

r

a

t

o

r

B

Z

Note: CS: Chip selection

BZ, BZ: Tone outputs

WR, RD, DATA: Serial interface

COM0~COM3, SEG0~SEG31: LCD outputs

IRQ: Time base or WDT overflow output

2

April 21, 2000

HT1621

Pin Assignment

S

E

G

7

6

5

4

3

2

1

0

S

E

G

7

6

5

4

3

2

1

0

4

3

2

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

S

E

G

8

9

1

2

3

4

3

2

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

S

E

G

8

9

1

2

3

1

2

3

4

5

6

7

8

9

1

2

1

2

3

4

5

6

7

8

9

1

2

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

C

S

C

S

R

N

D

R

D

R

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

W

S

E

G

5

3

1

2

1

8

7

6

5

4

3

2

1

0

9

8

7

6

5

S

C

E

G

7

9

1

2

3

1

2

3

4

5

6

7

8

9

1

D

A

T

A

D

V

A

T

A

V

S

V

S

1

3

5

7

9

1

3

5

7

9

1

O

S

C

O

S

C

O

C

S

C

O

S

C

I

R

D

R

O

S

C

I

L

C

D

W

V

D

/

V

L

C

D

V

D

V

A

T

A

I

R

Q

I

R

Q

V

S

B

Z

B

Z

L

C

D

V

D

0

1

2

3

4

C

O

M

0

1

2

3

C

O

M

0

1

2

3

I

R

Q

B

Z

C

O

M

0

1

O

M

2

H

T

1

6

2

1

H

T

1

6

2

1

B

H

T

1

6

2

1

D

-

P

4

8

S

O

P

4

8

S

O

P

/

D

I

2

8

S

k

i

n

y

3

April 21, 2000

HT1621

Pad Assignment

4

1

4

1

4

8

4

7

4

6

4

5

4

3

4

2

0

3

9

3

8

3

7

3

6

3

5

3

4

3

2

4

R

D

R

3

2

S

E

G

1

6

7

3

W

3

1

3

2

0

9

8

S

E

G

1

2

8

9

0

1

D

A

T

A

(

0

,

0

)

V

S

5

6

O

S

C

O

2

7

6

S

E

G

2

5

4

S

E

G

2

3

4

O

S

C

7

8

I

2

3

S

E

G

2

5

V

L

C

D

2

1

6

9

D

V

D

S

E

G

2

7

2

0

S

E

G

2

8

1

0

1

2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

Chip size: 127 ´ 129 (mil)²

* The IC substrate should be connected to VDD in the PCB layout artwork.

4

April 21, 2000

HT1621

Pad Coordinates

Unit:mil

Pad No.

X

Y

Pad No.

X

Y

1

2

59.46

22.18

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

58.14

55.55

48.92

42.29

35.66

29.03

22.40

15.77

9.14

-55.04

-58.52

-44.07

-31.58

-20.70

-13.98

-7.05

-25.29

-18.66

-11.94

-5.31

1.32

3

15.56

4

5.36

5

-4.51

6

7.95

-11.14

-34.76

-41.90

-49.13

-59.08

-58.44

-51.81

-45.18

-38.55

-31.92

7

14.58

21.21

59.46

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

-0.34

6.33

2.42

12.96

-4.21

-10.84

-17.47

-24.10

-30.73

-38.17

-45.39

19.59

58.14

5

April 21, 2000

HT1621

Pad Description

Pad No.

Pad Name

I/O

Function

Chip selection input with pull-high resistor

When the CS is logic high, the data and command read from or

written to the HT1621 are disabled. The serial interface circuit

is also reset. But if CS is at logic low level and is input to the CS

pad, the data and command transmission between the host con-

troller and the HT1621 are all enabled.

1

CS

I

READ clock input with pull-high resistor

Data in the RAM of the HT1621 are clocked out on the falling

edge of the RD signal. The clocked out data will appear on the

DATA line. The host controller can use the next rising edge to

latch the clocked out data.

2

3

RD

I

WRITE clock input with pull-high resistor

Data on the DATA line are latched into the HT1621 on the ris-

ing edge of the WR signal.

WR

4

5

7

DATA

VSS

I/O Serial data input/output with pull-high resistor

Negative power supply, ground

¾

OSCI

I

The OSCI and OSCO pads are connected to a 32.768kHz crystal

in order to generate a system clock. If the system clock comes

from an external clock source, the external clock source should

be connected to the OSCI pad. But if an on-chip RC oscillator is

selected instead, the OSCI and OSCO pads can be left open.

6

OSCO

O

8

VLCD

I

LCD power input

9

VDD

Positive power supply

¾

O

10

IRQ

Time base or WDT overflow flag, NMOS open drain output

2kHz or 4kHz tone frequency output pair

LCD common outputs

11, 12

13~16

48~17

BZ, BZ

COM0~COM3

SEG0~SEG31

LCD segment outputs

Absolute Maximum Ratings

Storage Temperature....................-50^oC~125^oC

Operating Temperature..................-25^oC~75^oC

Supply Voltage.................................-0.3V~5.5V

Input Voltage....................V_SS-0.3V~V_DD+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-

mum Ratings may cause substantial damage to the device. Functional operation of this de-

vice at other conditions beyond those listed in the specification is not implied and prolonged

exposure to extreme conditions may affect device reliability.

6

April 21, 2000

HT1621

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

¾

Symbol

V_DD

Parameter

Min. Typ. Max. Unit

V_DD

¾

Operating Voltage

Operating Current

2.4

¾

5.2

300

600

120

240

200

400

5

V

mA

V

¾

150

300

60

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

No load/LCD ON

On-chip RC oscillator

I_DD1

¾

No load/LCD ON

Crystal oscillator

I_DD2

I_DD3

I_STB

V_IL

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

DATA, BZ, BZ, IRQ

DATA, BZ, BZ

120

100

200

0.1

0.3

¾

No load/LCD ON

External clock source

¾

No load

Power down mode

10

¾

0

0.6

1.0

3.0

5.0

¾

DATA, WR, CS, RD

0

V

¾

2.4

4.0

0.5

1.3

-0.4

-0.9

80

V

¾

V_IH

V

¾

V_OL=0.3V

V_OL=0.5V

V_OH=2.7V

V_OH=4.5V

V_OL=0.3V

V_OL=0.5V

V_OH=2.7V

V_OH=4.5V

V_OL=0.3V

V_OL=0.5V

V_OH=2.7V

V_OH=4.5V

1.2

2.6

-0.8

-1.8

150

250

-120

mA

kW

I_OL1

I_OH1

I_OL2

I_OH2

I_OL3

I_OH3

R_PH

¾

LCD Common Sink

Current

150

-80

¾

LCD Common Source

Current

-120 -200

¾

60

120

-40

-70

40

120

200

-70

-100

80

¾

LCD Segment Sink

Current

¾

LCD Segment Source

Current

¾

150

100

Pull-high Resistor

DATA, WR, CS, RD

30

60

7

April 21, 2000

HT1621

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max. Unit

V_DD

f_SYS1

System Clock

3V On-chip RC oscillator

5V

256

kHz

Hz

¾

3V

Crystal oscillator

5V

32.768

256

f_SYS2

System Clock

3V

External clock source

5V

f_SYS3

256

f_SYS1/1024

On-chip RC oscillator

Crystal oscillator

¾

f_LCD

f

_SYS2/128

LCD Clock

Hz

f

_SYS3/1024

External clock source

n: Number of COM

Hz

¾

t_COM

f_CLK1

n/f_LCD

¾

LCD Common Period

s

¾

3V

5V

3V

5V

¾

150 kHz

300 kHz

Serial Data Clock (WR pin)

Duty cycle 50%

¾

75

kHz

¾

f_CLK2

Serial Data Clock (RD pin)

150 kHz

¾

f_TONE

Tone Frequency

On-chip RC oscillator

CS

2.0 or 4.0

kHz

ns

¾

Serial Interface Reset Pulse

(Figure 3)

t_CS

250

¾

Width

Write mode

Read mode

Write mode

Read mode

3.34

6.67

1.67

3.34

¾

3V

ms

ns

WR, RD Input Pulse Width

(Figure 1)

t_CLK

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

Rise/Fall Time Serial Data

(Figure 1)

t_r, t_f

120

100

¾

Clock Width

Setup Time for DATA to WR,

RD Clock Width (Figure 2)

t_su

Hold Time for DATA to WR,

RD Clock Width (Figure 2)

t_h

Setup Time for CS to WR, RD

(Figure 3)

t_su1

Clock Width

Hold Time for CS to WR, RD

Clock Width (Figure 3)

t_h1

8

April 21, 2000

HT1621

V

A

L

I

D

A

T

A

V

D

t

r

f

D

B

5

0

%

V

G

D

G

N

D

9 0

D

%

R

,

R

5

0

%

t

h

s

u

C

l

o

c

k

1

D

N

0

%

t

C

L

K

L

K

V

G

D

W

C

R

,

R

D

5

0

%

l

o

c

k

Figure 1

Figure 2

t

C

S

V

G

D

5

0

%

C

S

N

D

t

h

1

t

s

u

1

V

G

W

C

R

,

R

D

5

0

%

l

o

c

k

F

I

R

S

T

L

C

A

S

T

C

l

o

c

k

l

o

c

k

Figure 3

Functional Description

System oscillator

Display memory - RAM

The HT1621 system clock is used to generate

the time base/Watchdog Timer (WDT) clock fre-

quency, LCD driving clock, and tone frequency.

The source of the clock may be from an on-chip

RC oscillator (256kHz), a crystal oscillator

(32.768kHz), or an external 256kHz clock by

the S/W setting. The configuration of the sys-

tem oscillator is as shown. After the SYS DIS

command is executed, the system clock will

stop and the LCD bias generator will turn off.

That command is, however, available only for

the on-chip RC oscillator or for the crystal oscil-

lator. Once the system clock stops, the LCD dis-

play will become blank, and the time base/WDT

lose its function as well.

The static display memory (RAM) is organized

into 32´4 bits and stores the displayed data.

The contents of the RAM are directly mapped to

the contents of the LCD driver. Data in the

RAM can be accessed by the READ, WRITE,

and READ-MODIFY-WRITE commands. The

following is a mapping from the RAM to the

LCD pattern:

C

O

M

C

3

O

M

C

2

O

M

C

1

O

M

0

S

E

G

0

1

2

3

0

1

2

3

A

d

r

e

s

6

i

t

The ^bLCD_A^sOFF command is used to turn the

(

A

5

,

A

4

,

.

,

0

)

LCD bias generator off. After the LCD bias gen-

erator switches off by issuing the LCD OFF

command, using the SYS DIS command re-

duces power consumption, serving as a system

power down command. But if the external clock

source is chosen as the system clock, using the

SYS DIS command can neither turn the oscilla-

tor off nor carry out the power down mode. The

crystal oscillator option can be applied to con-

nect an external frequency source of 32kHz to

the OSCI pin. In this case, the system fails to

S

E

G

3

1

3

1

A

d

r

D

3

D

2

D

1

D

0

D

a

t

a

D

a

t

a

4

b

i

t

s

(

D

3

,

D

2

,

D

1

,

D

0

)

RAM mapping

9

April 21, 2000

HT1621

enter the power down mode, similar to the case

in the external 256kHz clock source operation.

At the initial system power on, the HT1621 is at

the SYS DIS state.

where the value of n ranges from 0 to 7 by com-

mand options. The 32kHz in the above equation

indicates that the source of the system fre-

quency is derived from a crystal oscillator of

32.768kHz, an on-chip oscillator (256kHz), or

an external frequency of 256kHz.

Time base and Watchdog Timer (WDT)

The time base generator is comprised by an

8-stage count-up ripple counter and is designed

to generate an accurate time base. The watch

dog timer (WDT), on the other hand, is com-

posed of an 8-stage time base generator along

with a 2-stage count-up counter, and is de-

signed to break the host controller or other sub-

systems from abnormal states such as

unknown or unwanted jump, execution errors,

etc. The WDT time-out will result in the setting

of an internal WDT time-out flag. The outputs

of the time base generator and of the WDT

time-out flag can be connected to the IRQ out-

put by a command option. There are totally

eight frequency sources available for the time

base generator and the WDT clock. The fre-

quency is calculated by the following equation.

If an on-chip oscillator (256kHz) or an external

256kHz frequency is chosen as the source of the

system frequency, the frequency source is by de-

fault prescaled to 32kHz by a 3-stage prescaler.

Employing both the time base generator and

the WDT related commands, one should be

careful since the time base generator and WDT

share the same 8-stage counter. For example,

invoking the WDT DIS command disables the

time base generator whereas executing the

WDT EN command not only enables the time

base generator but activates the WDT time-out

flag output (connect the WDT time-out flag to

the IRQ pin). After the TIMER EN command is

transferred, the WDT is disconnected from the

IRQ pin, and the output of the time base generator

is connected to the IRQ pin. The WDT can be

cleared by executing the CLR WDT command,

and the contents of the time base generator is

cleared by executing the CLR WDT or the CLR

32kHz

2ⁿ

f_WDT

=

C

r

y

s

t

a

l

O

s

c

i

l

a

t

o

r

O

S

C

I

3

2

7

6

8

H

z

O

S

C

O

E

x

t

e

r

n

a

l

C

l

o

c

k

S

o

u

r

c

e

S

C

y

s

t

c

e

m

2

5

6

k

H

z

l

o

k

1

/

8

O

n

-

c

h

i

p

R

C

O

s

c

i

l

a

t

o

r

2

5

6

k

H

z

System oscillator configuration

T

i

m

e

r

/

W

D

T

I

M

E

R

E

N

/

D

I

S

C

l

o

c

k

S

o

u

r

c

e

s

S

f

y

s

t

e

m

C

l

o

c

k

n

/

2

5

6

I

R

Q

/

2

W

D

T

E

N

/

D

I

S

=

3

2

k

H

z

n

=

0

~

7

V

D

Q

D

W

D

T

I

R

Q

E

N

/

D

I

S

C

K

/

4

R

C

L

R

W

D

T

Timer and WDT configurations

10

April 21, 2000

HT1621

Name

LCD OFF

Command Code

1 0 0 0 0 0 0 0 0 1 0 X

1 0 0 0 0 0 0 0 0 1 1 X

Function

Turn off LCD outputs

LCD ON

Turn on LCD outputs

c=0: 1/2 bias option

c=1: 1/3 bias option

BIAS & COM

1 0 0 0 0 1 0 a b X c X

ab=00: 2 commons option

ab=01: 3 commons option

ab=10: 4 commons option

Tone output

TIMER command. The CLR WDT or the CLR

TIMER command should be executed prior to

the WDT EN or the TIMER EN command re-

spectively. Before executing the IRQ EN com-

mand the CLR WDT or CLR TIMER command

should be executed first. The CLR TIMER com-

mand has to be executed before switching from

the WDT mode to the time base mode. Once the

WDT time-out occurs, the IRQ pin will stay at a

logic low level until the CLR WDT or the IRQ

DIS command is issued. After the IRQ output is

disabled the IRQ pin will remain at the floating

state. The IRQ output can be enabled or dis-

abled by executing the IRQ EN or the IRQ DIS

command, respectively. The IRQ EN makes the

output of the time base generator or of the WDT

time-out flag appear on the IRQ pin. The config-

uration of the time base generator along with

the WDT are as shown. In the case of on-chip

RC oscillator or crystal oscillator, the power

down mode can reduce power consumption

since the oscillator can be turned on or off by

the corresponding system commands. At the

power down mode the time base/WDT loses all

its functions.

A simple tone generator is implemented in the

HT1621. The tone generator can output a pair

of differential driving signals on the BZ and BZ,

which are used to generate a single tone. By ex-

ecuting the TONE4K and TONE2K commands

there are two tone frequency outputs

selectable. The TONE4K and TONE2K com-

mands set the tone frequency to 4kHz and

2kHz, respectively. The tone output can be

turned on or off by invoking the TONE ON or

the TONE OFF command. The tone outputs,

namely BZ and BZ, are a pair of differential

driving outputs used to drive a piezo buzzer.

Once the system is disabled or the tone output

is inhibited, the BZ and the BZ outputs will re-

main at low level.

LCD driver

The HT1621 is a 128 (32´4) pattern LCD driver.

It can be configured as 1/2 or 1/3 bias and 2 or 3

or 4 commons of LCD driver by the S/W configu-

ration. This feature makes the HT1621 suitable

for multiply LCD applications. The LCD driving

clock is derived from the system clock. The value

of the driving clock is always 256Hz even when it

is at a 32.768kHz crystal oscillator frequency, an

on-chip RC oscillator frequency, or an external

frequency. The LCD corresponding commands

are summarized in the table.

On the other hand, if an external clock is se-

lected as the source of system frequency the

SYS DIS command turns out invalid and the

power down mode fails to be carried out. That

is, after the external clock source is selected,

the HT1621 will continue working until system

power fails or the external clock source is re-

moved. After the system power on, the IRQ will

be disabled.

The bold form of 1 0 0, namely 1 0 0, indicates

the command mode ID. If successive commands

have been issued, the command mode ID except

for the first command, will be omitted. The LCD

11

April 21, 2000

HT1621

OFF command turns the LCD display off by dis-

abling the LCD bias generator. The LCD ON

command, on the other hand, turns the LCD

display on by enabling the LCD bias generator.

The BIAS and COM are the LCD panel related

commands. Using the LCD related commands,

the HT1621 can be compatible with most types

of LCD panels.

the system is operating in the non-successive

command or the non-successive address data

mode, the CS pin should be set to "1" and the

previous operation mode will be reset also.

Once the CS pin returns to "0" a new operation

mode ID should be issued first.

Interfacing

Only four lines are required to interface with

the HT1621. The CS line is used to initialize the

serial interface circuit and to terminate the com-

munication between the host controller and the

HT1621. If the CS pin is set to 1, the data and

command issued between the host controller and

the HT1621 are first disabled and then initial-

ized. Before issuing a mode command or mode

switching, a high level pulse is required to initial-

ize the serial interface of the HT1621. The DATA

line is the serial data input/output line. Data to

be read or written or commands to be written

have to be passed through the DATA line. The RD

line is the READ clock input. Data in the RAM

are clocked out on the falling edge of the RD sig-

nal, and the clocked out data will then appear on

the DATA line. It is recommended that the host

controller read in correct data during the interval

between the rising edge and the next falling edge

of the RD signal. The WR line is the WRITE clock

input. The data, address, and command on the

DATA line are all clocked into the HT1621 on the

rising edge of the WR signal. There is an optional

IRQ line to be used as an interface between the

host controller and the HT1621. The IRQ pin can

be selected as a timer output or a WDT overflow

flag output by the S/W setting. The host control-

ler can perform the time base or the WDT func-

tion by being connected with the IRQ pin of the

HT1621.

Command format

The HT1621 can be configured by the S/W set-

ting. There are two mode commands to configure

the HT1621 resources and to transfer the LCD

display data. The configuration mode of the

HT1621 is called command mode, and its com-

mand mode ID is 1 0 0. The command mode con-

sists of a system configuration command, a

system frequency selection command, a LCD con-

figuration command, a tone frequency selection

command, a timer/WDT setting command, and

an operating command. The data mode, on the

other hand, includes READ, WRITE, and

READ-MODIFY-WRITE operations. The follow-

ing are the data mode IDs and the command

mode ID:

Operation

Mode

Data

ID

READ

1 1 0

1 0 1

WRITE

READ-MODIFY-WRITE

COMMAND

Command 1 0 0

The mode command should be issued before the

data or command is transferred. If successive

commands have been issued, the command

mode ID, namely 1 0 0, can be omitted. While

12

April 21, 2000

HT1621

Timing Diagrams

READ mode (command code : 1 1 0)

C

W

R

D

S

R

D

A

0

A

5

A

3

A

2

D

2

D

3

0

A

5

A

3

A

2

D

2

D

1

3

A

4

A

1

A

0

D

0

D

1

A

4

A

1

A

0

D

0

D

1

T

A

M

e

m

o

r

y

A

d

D

d

a

r

e

t

a

s

(

M

1

A

(

1

M

)

A

1

)

M

e

m

o

r

y

A

d

r

e

s

2

D

(

a

M

READ mode (successive address reading)

C

W

R

D

S

R

D

A

0

A

5

A

3

A

2

D

2

D

3

D

2

D

3

D

2

D

3

D

2

D

3

D

A

4

A

1

A

0

D

0

D

1

D

0

D

1

D

0

D

1

D

0

D

1

0

1

T

A

M

e

m

o

r

y

A

d

r

e

s

D

s

a

t

(

a

M

A

(

)

M

D

A

a

+

t

1

a

)

(

D

M

a

A

t

a

)

(

M

A

+

2

)

D

a

t

a

13

April 21, 2000

HT1621

WRITE mode (command code : 1 0 1)

C

W

D

S

R

1

A

5

A

3

A

2

D

2

D

3

1

A

5

A

3

A

2

D

2

D

1

3

A

4

A

1

A

0

D

0

D

1

A

4

A

1

A

0

D

0

D

1

0

1

0

A

T

A

M

e

m

o

r

y

A

d

r

e

s

1

(

M

e

A

m

1

o

)

r

D

y

a

t

A

a

d

(

r

M

e

A

s

1

s

)

2

(

M

A

2

)

D

a

WRITE mode (successive address writing)

C

W

D

S

R

1

A

5

A

3

A

2

D

2

D

3

D

2

D

3

D

2

D

3

D

2

D

3

D

A

4

A

1

A

0

D

0

D

1

D

0

D

1

D

0

D

1

D

0

D

1

0

1

0

A

T

A

M

e

m

o

r

y

A

d

r

e

s

D

s

a

t

(

a

M

A

(

)

M

D

A

a

+

t

1

a

)

(

D

M

a

A

t

a

)

(

M

A

+

2

)

D

a

t

a

14

April 21, 2000

HT1621

READ-MODIFY-WRITE mode (command code : 1 0 1)

C

W

S

R

D

1

A

5

A

3

A

1

2

D

0

D

1

2

D

3

D

0

D

1

2

D

3

A

5

A

3

A

1

2

0

D

1

2

D

3

1

0

A

4

A

0

1

0

1

A

4

A

0

D

A

T

A

M

e

m

o

r

y

A

d

r

e

s

D

a

1

t

a

(

M

(

A

M

1

A

)

1

M

)

a

e

t

m

a

o

r

(

y

M

A

1

d

)

d

r

e

s

2

(

M

A

2

)

D

a

t

READ-MODIFY-WRITE mode (successive address accessing)

C

W

S

R

D

1

A

5

A

3

A

1

2

0

D

1

2

D

3

D

0

D

1

2

D

3

D

0

D

1

2

D

3

D

0

D

1

2

D

3

D

0

D

1

D

2

D

3

D

0

1

0

A

4

A

0

D

A

T

A

M

e

m

o

r

y

A

d

r

e

s

D

s

a

t

(

a

M

A

(

)

M

D

A

a

)

t

a

D

a

(

M

t

a

A

D

)

(

a

M

t

A

a

+

(

1

M

)

A

D

+

a

2

t

)

a

(

M

A

+

1

15

April 21, 2000

HT1621

Command mode (command code : 1 0 0)

C

W

D

S

R

0

C

8

C

6

C

5

C

0

C

8

C

6

C

5

C

0

1

C

7

C

4

C

3

C

2

C

1

C

7

C

4

C

3

C

2

C

1

0

A

T

A

C

o

m

a

n

C

d

o

1

m

a

n

C

d

.

o

.

m

.

m

a

n

d

i

C

o

m

a

n

d

o

r

D

a

t

a

M

o

d

e

Mode (data and command mode)

C

W

D

S

R

A

D

T

A

C

o

m

a

n

d

C

o

m

a

n

d

C

o

m

a

n

d

o

r

A

d

r

e

s

&

o

D

r

a

A

t

d

a

d

r

e

s

a

n

o

d

r

A

D

d

a

d

t

r

a

e

s

a

n

d

D

a

t

a

D

a

t

a

M

o

d

e

D

a

t

a

M

o

d

e

D

a

t

a

M

o

d

e

R

Note: It is recommended that the host controller should read in the data from the DATA line

between the rising edge of the RD line and the falling edge of the next RD line.

16

April 21, 2000

HT1621

Application Circuits

Host controller with an HT1621 display system

C

R

S

D

V

D

*

V

R

W

D

R

V

L

C

D

A

T

A

m

C

H

T

1

6

2

1

B

*

B

Z

R

P

i

e

z

o

I

O

R

Q

B

Z

S

C

I

O

C

l

o

c

k

O

u

t

C

O

M

0

~

C

O

M

3

S

E

G

0

~

S

E

G

3

1

E

x

t

e

r

n

a

l

C

o

l

c

k

1

2

1

/

2

o

r

1

/

3

B

i

a

s

;

1

/

2

,

1

/

3

o

r

1

/

4

D

u

O

n

-

c

h

i

p

O

S

C

L

C

D

P

a

n

e

l

C

r

y

s

t

a

l

3

2

7

6

8

H

z

Note:

The connection of IRQ and RD pin can be selected depending on the requirement of the mC.

The voltage applied to V_LCDpin must be lower than V_DD

.

Adjust VR to fit LCD display, at V_DD=5V, V_LCD=4V, VR=15kW±20%.

Adjust R (external pull-high resistance) to fit user s time base clock.

17

April 21, 2000

HT1621

Command Summary

Name

READ

ID

Command Code

D/C

D

Function

Read data from the RAM

Write data to the RAM

Def.

1 1 0 A5A4A3A2A1A0D0D1D2D3

1 0 1 A5A4A3A2A1A0D0D1D2D3

WRITE

D

READ-

MODIFY-

WRITE

1 0 1 A5A4A3A2A1A0D0D1D2D3

1 0 0 0000-0000-X

D

C

READ and WRITE to the RAM

Turn off both system oscillator

and LCD bias generator

SYS DIS

Yes

SYS EN

LCD OFF

LCD ON

1 0 0 0000-0001-X

1 0 0 0000-0010-X

1 0 0 0000-0011-X

C

Turn on system oscillator

Turn off LCD bias generator

Turn on LCD bias generator

Disable time base output

TIMER DIS 1 0 0 0000-0100-X

WDT DIS

1 0 0 0000-0101-X

TIMER EN 1 0 0 0000-0110-X

WDT EN

1 0 0 0000-0111-X

Disable WDT time-out flag

output

C

Enable time base output

Enable WDT time-out flag

output

TONE OFF 1 0 0 0000-1000-X

TONE ON

1 0 0 0000-1001-X

C

Turn off tone outputs

Turn on tone outputs

Yes

Clear the contents of time base

generator

CLR TIMER 1 0 0 0000-11XX-X

C

CLR WDT

XTAL 32K

1 0 0 0000-111X-X

1 0 0 0001-01XX-X

Clear the contents of WDT stage

System clock source, crystal

oscillator

System clock source, on-chip RC

oscillator

RC 256K

1 0 0 0001-10XX-X

1 0 0 0001-11XX-X

C

Yes

System clock source, external

clock source

EXT 256K

LCD 1/2 bias option

ab=00: 2 commons option

ab=01: 3 commons option

ab=10: 4 commons option

BIAS 1/2

BIAS 1/3

1 0 0 0010-abX0-X

1 0 0 0010-abX1-X

C

LCD 1/3 bias option

ab=00: 2 commons option

ab=01: 3 commons option

ab=10: 4 commons option

TONE 4K

TONE 2K

IRQ DIS

1 0 0 010X-XXXX-X

1 0 0 011X-XXXX-X

1 0 0 100X-0XXX-X

C

Tone frequency, 4kHz

Tone frequency, 2kHz

Disable IRQ output

Yes

18

April 21, 2000

HT1621

Name

ID

Command Code

D/C

Function

Enable IRQ output

Def.

IRQ EN

1 0 0 100X-1XXX-X

C

Time base/WDT clock

output:1Hz

The WDT time-out flag after: 4s

F1

1 0 0 101X-X000-X

C

Time base/WDT clock

output:2Hz

The WDT time-out flag after: 2s

F2

1 0 0 101X-X001-X

1 0 0 101X-X010-X

1 0 0 101X-X011-X

1 0 0 101X-X100-X

1 0 0 101X-X101-X

1 0 0 101X-X110-X

1 0 0 101X-X111-X

Time base/WDT clock

output:4Hz

The WDT time-out flag after: 1s

F4

Time base/WDT clock

output:8Hz

The WDT time-out flag after: 1/2 s

F8

Time base/WDT clock

output:16Hz

The WDT time-out flag after: 1/4 s

F16

F32

F64

F128

Time base/WDT clock

output:32Hz

The WDT time-out flag after: 1/8 s

Time base/WDT clock

output:64Hz

The WDT time-out flag after: 1/16 s

Time base/WDT clock

output:128Hz

The WDT time-out flag after: 1/32 s

Yes

TEST

1 0 0 1110-0000-X

1 0 0 1110-0011-X

C

Test mode, user don't use.

Normal mode

NORMAL

Note: X : Don^,t care

A5~A0 : RAM addresses

D3~D0 : RAM data

D/C : Data/command mode

Def. : Power on reset default

All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates

the command mode ID. If successive commands have been issued, the command mode ID ex-

cept for the first command will be omitted. The source of the tone frequency and of the time

base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz

crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the

system frequency sources as stated above. It is recommended that the host controller should

initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to

the malfunctioning of the HT1621.

19

April 21, 2000

HT1621

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.

Tel: 886-3-563-1999

Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.

Tel: 886-2-2782-9635

Fax: 886-2-2782-9636

Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong

Tel: 852-2-745-8288

Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek

assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are

used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications

will be suitable without further modification, nor recommends the use of its products for application that may pres-

ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior

notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

20

April 21, 2000

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